Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	2897305	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	2897305	0	0
T3	3469	1663	0	0
T4	655492	0	0	0
T5	323009	5443	0	0
T6	41103	1663	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	5002	0	0
T11	673593	7485	0	0
T12	4665	0	0	0
T14	0	1663	0	0
T15	0	17465	0	0
T16	0	20789	0	0
T17	0	1663	0	0
T18	0	9148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	3175489	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	3175489	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	4999	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	9010	0	0
T11	673593	4992	0	0
T12	4665	0	0	0
T14	0	832	0	0
T15	0	11648	0	0
T16	0	11648	0	0
T17	0	832	0	0
T18	0	15075	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	176610	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	176610	0	0
T1	315768	445	0	0
T2	99050	262	0	0
T3	3469	0	0	0
T4	655492	0	0	0
T5	323009	0	0	0
T6	41103	0	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	352	0	0
T11	0	942	0	0
T12	0	26	0	0
T15	0	2684	0	0
T16	0	288	0	0
T18	0	650	0	0
T24	0	1348	0	0
T25	0	369	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	378552	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	378552	0	0
T1	315768	445	0	0
T2	99050	262	0	0
T3	3469	0	0	0
T4	655492	0	0	0
T5	323009	0	0	0
T6	41103	0	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	1544	0	0
T11	0	940	0	0
T12	0	119	0	0
T15	0	2677	0	0
T16	0	288	0	0
T18	0	2923	0	0
T24	0	1344	0	0
T25	0	980	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	5404683	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	5404683	0	0
T1	315768	6178	0	0
T2	99050	2744	0	0
T3	3469	69	0	0
T4	655492	849	0	0
T5	323009	4575	0	0
T6	41103	1019	0	0
T7	4908	178	0	0
T8	1189	2	0	0
T9	1239	20	0	0
T10	591296	1189	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413899092	10118014	0	0
DepthKnown_A	413899092	413767798	0	0
RvalidKnown_A	413899092	413767798	0	0
WreadyKnown_A	413899092	413767798	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	10118014	0	0
T1	315768	6167	0	0
T2	99050	2718	0	0
T3	3469	211	0	0
T4	655492	849	0	0
T5	323009	14331	0	0
T6	41103	4556	0	0
T7	4908	178	0	0
T8	1189	2	0	0
T9	1239	20	0	0
T10	591296	5061	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413899092	413767798	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0