Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T10,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	711042279	559879332	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	711042279	3645879	0	0
GntImpliesValid_A	711042279	3645879	0	0
GrantKnown_A	711042279	559879332	0	0
IdxKnown_A	711042279	559879332	0	0
IndexIsCorrect_A	711042279	3645879	0	0
LockArbDecision_A	711042279	0	0	0
NoReadyValidNoGrant_A	711042279	0	0	0
ReadyAndValidImplyGrant_A	711042279	3645879	0	0
ReqAndReadyImplyGrant_A	711042279	3645879	0	0
ReqImpliesValid_A	711042279	3645879	0	0
ReqStaysHighUntilGranted0_M	711042279	0	0	0
RoundRobin_A	711042279	5	0	956
ValidKnown_A	711042279	559879332	0	0
gen_data_port_assertion.DataFlow_A	711042279	3645879	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	559879332	0	0
T1	388801	384943	0	0
T2	146164	143367	0	0
T3	3957	3650	0	0
T4	875360	761760	0	0
T5	412627	367732	0	0
T6	258093	149296	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	1140858	864258	0	0
T11	1300898	642746	0	0
T12	5360	2680	0	0
T14	115004	56996	0	0
T15	137850	1365550	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	583924	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	559879332	0	0
T1	388801	384943	0	0
T2	146164	143367	0	0
T3	3957	3650	0	0
T4	875360	761760	0	0
T5	412627	367732	0	0
T6	258093	149296	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	1140858	864258	0	0
T11	1300898	642746	0	0
T12	5360	2680	0	0
T14	115004	56996	0	0
T15	137850	1365550	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	583924	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	559879332	0	0
T1	388801	384943	0	0
T2	146164	143367	0	0
T3	3957	3650	0	0
T4	875360	761760	0	0
T5	412627	367732	0	0
T6	258093	149296	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	1140858	864258	0	0
T11	1300898	642746	0	0
T12	5360	2680	0	0
T14	115004	56996	0	0
T15	137850	1365550	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	583924	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	5	0	956
T43	824061	1	0	1
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	10086	0	0	1
T48	15485	0	0	1
T49	1364	0	0	1
T50	12641	0	0	1
T51	381423	0	0	1
T52	240844	0	0	1
T53	203229	0	0	1
T54	3882	0	0	1
T55	321359	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	559879332	0	0
T1	388801	384943	0	0
T2	146164	143367	0	0
T3	3957	3650	0	0
T4	875360	761760	0	0
T5	412627	367732	0	0
T6	258093	149296	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	1140858	864258	0	0
T11	1300898	642746	0	0
T12	5360	2680	0	0
T14	115004	56996	0	0
T15	137850	1365550	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	583924	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	711042279	3645879	0	0
T1	388801	4156	0	0
T2	146164	2269	0	0
T3	3713	832	0	0
T4	765426	0	0	0
T5	367818	3136	0	0
T6	149598	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	1140858	8020	0	0
T11	1300898	20124	0	0
T12	5360	195	0	0
T14	115004	832	0	0
T15	137850	36903	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	5859	0	0
T24	0	7431	0	0
T25	0	2219	0	0
T26	0	2533	0	0
T34	21901	0	0	0
T37	0	11918	0	0
T41	4800	0	0	0
T42	0	2404	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T2,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149778196	26817953	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149778196	576015	0	0
GntImpliesValid_A	149778196	576015	0	0
GrantKnown_A	149778196	26817953	0	0
IdxKnown_A	149778196	26817953	0	0
IndexIsCorrect_A	149778196	576015	0	0
LockArbDecision_A	149778196	0	0	0
NoReadyValidNoGrant_A	149778196	0	0	0
ReadyAndValidImplyGrant_A	149778196	576015	0	0
ReqAndReadyImplyGrant_A	149778196	576015	0	0
ReqImpliesValid_A	149778196	576015	0	0
ReqStaysHighUntilGranted0_M	149778196	0	0	0
RoundRobin_A	149778196	0	0	0
ValidKnown_A	149778196	26817953	0	0
gen_data_port_assertion.DataFlow_A	149778196	576015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	26817953	0	0
T1	73033	69256	0	0
T2	47114	44400	0	0
T3	244	0	0	0
T4	109934	106360	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	148088	0	0
T12	2680	2680	0	0
T14	57502	0	0	0
T15	0	811544	0	0
T18	0	193856	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	26817953	0	0
T1	73033	69256	0	0
T2	47114	44400	0	0
T3	244	0	0	0
T4	109934	106360	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	148088	0	0
T12	2680	2680	0	0
T14	57502	0	0	0
T15	0	811544	0	0
T18	0	193856	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	26817953	0	0
T1	73033	69256	0	0
T2	47114	44400	0	0
T3	244	0	0	0
T4	109934	106360	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	148088	0	0
T12	2680	2680	0	0
T14	57502	0	0	0
T15	0	811544	0	0
T18	0	193856	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	26817953	0	0
T1	73033	69256	0	0
T2	47114	44400	0	0
T3	244	0	0	0
T4	109934	106360	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	148088	0	0
T12	2680	2680	0	0
T14	57502	0	0	0
T15	0	811544	0	0
T18	0	193856	0	0
T24	0	181288	0	0
T25	0	56160	0	0
T26	0	19003	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	576015	0	0
T1	73033	2759	0	0
T2	47114	1526	0	0
T3	244	0	0	0
T4	109934	0	0	0
T5	44809	0	0	0
T6	108495	0	0	0
T10	274781	0	0	0
T11	650449	3437	0	0
T12	2680	136	0	0
T14	57502	0	0	0
T15	0	10110	0	0
T18	0	2974	0	0
T24	0	4605	0	0
T25	0	1542	0	0
T26	0	817	0	0
T37	0	3251	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T15
1	0	Covered	T10,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T10,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T11,T15
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149778196	121661526	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149778196	818893	0	0
GntImpliesValid_A	149778196	818893	0	0
GrantKnown_A	149778196	121661526	0	0
IdxKnown_A	149778196	121661526	0	0
IndexIsCorrect_A	149778196	818893	0	0
LockArbDecision_A	149778196	0	0	0
NoReadyValidNoGrant_A	149778196	0	0	0
ReadyAndValidImplyGrant_A	149778196	818893	0	0
ReqAndReadyImplyGrant_A	149778196	818893	0	0
ReqImpliesValid_A	149778196	818893	0	0
ReqStaysHighUntilGranted0_M	149778196	0	0	0
RoundRobin_A	149778196	0	0	0
ValidKnown_A	149778196	121661526	0	0
gen_data_port_assertion.DataFlow_A	149778196	818893	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	121661526	0	0
T3	244	244	0	0
T4	109934	0	0	0
T5	44809	44809	0	0
T6	108495	108260	0	0
T10	274781	273019	0	0
T11	650449	494658	0	0
T12	2680	0	0	0
T14	57502	56996	0	0
T15	137850	554006	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	390068	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	121661526	0	0
T3	244	244	0	0
T4	109934	0	0	0
T5	44809	44809	0	0
T6	108495	108260	0	0
T10	274781	273019	0	0
T11	650449	494658	0	0
T12	2680	0	0	0
T14	57502	56996	0	0
T15	137850	554006	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	390068	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	121661526	0	0
T3	244	244	0	0
T4	109934	0	0	0
T5	44809	44809	0	0
T6	108495	108260	0	0
T10	274781	273019	0	0
T11	650449	494658	0	0
T12	2680	0	0	0
T14	57502	56996	0	0
T15	137850	554006	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	390068	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	121661526	0	0
T3	244	244	0	0
T4	109934	0	0	0
T5	44809	44809	0	0
T6	108495	108260	0	0
T10	274781	273019	0	0
T11	650449	494658	0	0
T12	2680	0	0	0
T14	57502	56996	0	0
T15	137850	554006	0	0
T16	581919	578070	0	0
T17	0	136728	0	0
T18	0	390068	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149778196	818893	0	0
T10	274781	4325	0	0
T11	650449	9629	0	0
T12	2680	0	0	0
T14	57502	0	0	0
T15	137850	9874	0	0
T16	581919	1598	0	0
T17	136728	0	0	0
T18	587829	2885	0	0
T24	0	2826	0	0
T25	0	677	0	0
T26	0	1716	0	0
T34	21901	0	0	0
T37	0	8667	0	0
T41	4800	0	0	0
T42	0	2404	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411485887	411399853	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	411485887	2250971	0	0
GntImpliesValid_A	411485887	2250971	0	0
GrantKnown_A	411485887	411399853	0	0
IdxKnown_A	411485887	411399853	0	0
IndexIsCorrect_A	411485887	2250971	0	0
LockArbDecision_A	411485887	0	0	0
NoReadyValidNoGrant_A	411485887	0	0	0
ReadyAndValidImplyGrant_A	411485887	2250971	0	0
ReqAndReadyImplyGrant_A	411485887	2250971	0	0
ReqImpliesValid_A	411485887	2250971	0	0
ReqStaysHighUntilGranted0_M	411485887	0	0	0
RoundRobin_A	411485887	5	0	956
ValidKnown_A	411485887	411399853	0	0
gen_data_port_assertion.DataFlow_A	411485887	2250971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	411399853	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	411399853	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	411399853	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	5	0	956
T43	824061	1	0	1
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	10086	0	0	1
T48	15485	0	0	1
T49	1364	0	0	1
T50	12641	0	0	1
T51	381423	0	0	1
T52	240844	0	0	1
T53	203229	0	0	1
T54	3882	0	0	1
T55	321359	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	411399853	0	0
T1	315768	315687	0	0
T2	99050	98967	0	0
T3	3469	3406	0	0
T4	655492	655400	0	0
T5	323009	322923	0	0
T6	41103	41036	0	0
T7	4908	4719	0	0
T8	1189	1139	0	0
T9	1239	1165	0	0
T10	591296	591239	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411485887	2250971	0	0
T1	315768	1397	0	0
T2	99050	743	0	0
T3	3469	832	0	0
T4	655492	0	0	0
T5	323009	3136	0	0
T6	41103	832	0	0
T7	4908	0	0	0
T8	1189	0	0	0
T9	1239	0	0	0
T10	591296	3695	0	0
T11	0	7058	0	0
T12	0	59	0	0
T14	0	832	0	0
T15	0	16919	0	0