Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3548 | 
0 | 
0 | 
| T59 | 
4458 | 
3 | 
0 | 
0 | 
| T60 | 
13817 | 
7 | 
0 | 
0 | 
| T95 | 
7938 | 
126 | 
0 | 
0 | 
| T96 | 
7767 | 
88 | 
0 | 
0 | 
| T97 | 
19621 | 
5 | 
0 | 
0 | 
| T98 | 
29253 | 
3 | 
0 | 
0 | 
| T99 | 
8445 | 
78 | 
0 | 
0 | 
| T100 | 
13151 | 
151 | 
0 | 
0 | 
| T103 | 
6573 | 
44 | 
0 | 
0 | 
| T107 | 
13310 | 
6 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
873 | 
0 | 
0 | 
| T58 | 
37157 | 
52 | 
0 | 
0 | 
| T60 | 
13817 | 
26 | 
0 | 
0 | 
| T112 | 
7089 | 
13 | 
0 | 
0 | 
| T116 | 
7938 | 
1 | 
0 | 
0 | 
| T120 | 
8877 | 
8 | 
0 | 
0 | 
| T121 | 
9992 | 
5 | 
0 | 
0 | 
| T143 | 
13578 | 
31 | 
0 | 
0 | 
| T144 | 
6626 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
55 | 
0 | 
0 | 
| T146 | 
32483 | 
39 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
907 | 
0 | 
0 | 
| T58 | 
37157 | 
35 | 
0 | 
0 | 
| T60 | 
13817 | 
20 | 
0 | 
0 | 
| T112 | 
7089 | 
3 | 
0 | 
0 | 
| T116 | 
7938 | 
10 | 
0 | 
0 | 
| T120 | 
8877 | 
14 | 
0 | 
0 | 
| T121 | 
9992 | 
7 | 
0 | 
0 | 
| T143 | 
13578 | 
53 | 
0 | 
0 | 
| T144 | 
6626 | 
50 | 
0 | 
0 | 
| T145 | 
95724 | 
51 | 
0 | 
0 | 
| T146 | 
32483 | 
62 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1282 | 
0 | 
0 | 
| T58 | 
37157 | 
50 | 
0 | 
0 | 
| T60 | 
13817 | 
23 | 
0 | 
0 | 
| T112 | 
7089 | 
25 | 
0 | 
0 | 
| T116 | 
7938 | 
4 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
19 | 
0 | 
0 | 
| T143 | 
13578 | 
55 | 
0 | 
0 | 
| T144 | 
6626 | 
26 | 
0 | 
0 | 
| T145 | 
95724 | 
118 | 
0 | 
0 | 
| T146 | 
32483 | 
63 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6729 | 
0 | 
0 | 
| T58 | 
37157 | 
827 | 
0 | 
0 | 
| T60 | 
13817 | 
211 | 
0 | 
0 | 
| T112 | 
7089 | 
123 | 
0 | 
0 | 
| T116 | 
7938 | 
11 | 
0 | 
0 | 
| T120 | 
8877 | 
134 | 
0 | 
0 | 
| T121 | 
9992 | 
227 | 
0 | 
0 | 
| T143 | 
13578 | 
15 | 
0 | 
0 | 
| T144 | 
6626 | 
16 | 
0 | 
0 | 
| T145 | 
95724 | 
1069 | 
0 | 
0 | 
| T146 | 
32483 | 
521 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6475 | 
0 | 
0 | 
| T58 | 
37157 | 
534 | 
0 | 
0 | 
| T60 | 
13817 | 
125 | 
0 | 
0 | 
| T112 | 
7089 | 
13 | 
0 | 
0 | 
| T116 | 
7938 | 
115 | 
0 | 
0 | 
| T120 | 
8877 | 
4 | 
0 | 
0 | 
| T121 | 
9992 | 
7 | 
0 | 
0 | 
| T143 | 
13578 | 
47 | 
0 | 
0 | 
| T144 | 
6626 | 
22 | 
0 | 
0 | 
| T145 | 
95724 | 
1131 | 
0 | 
0 | 
| T146 | 
32483 | 
588 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6260 | 
0 | 
0 | 
| T58 | 
37157 | 
695 | 
0 | 
0 | 
| T60 | 
13817 | 
77 | 
0 | 
0 | 
| T112 | 
7089 | 
253 | 
0 | 
0 | 
| T116 | 
7938 | 
120 | 
0 | 
0 | 
| T120 | 
8877 | 
64 | 
0 | 
0 | 
| T121 | 
9992 | 
139 | 
0 | 
0 | 
| T143 | 
13578 | 
46 | 
0 | 
0 | 
| T144 | 
6626 | 
6 | 
0 | 
0 | 
| T145 | 
95724 | 
716 | 
0 | 
0 | 
| T146 | 
32483 | 
542 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
5391 | 
0 | 
0 | 
| T58 | 
37157 | 
245 | 
0 | 
0 | 
| T60 | 
13817 | 
46 | 
0 | 
0 | 
| T112 | 
7089 | 
235 | 
0 | 
0 | 
| T116 | 
7938 | 
129 | 
0 | 
0 | 
| T120 | 
8877 | 
131 | 
0 | 
0 | 
| T121 | 
9992 | 
16 | 
0 | 
0 | 
| T143 | 
13578 | 
77 | 
0 | 
0 | 
| T144 | 
6626 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
1227 | 
0 | 
0 | 
| T146 | 
32483 | 
441 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6880 | 
0 | 
0 | 
| T58 | 
37157 | 
692 | 
0 | 
0 | 
| T60 | 
13817 | 
73 | 
0 | 
0 | 
| T112 | 
7089 | 
121 | 
0 | 
0 | 
| T116 | 
7938 | 
285 | 
0 | 
0 | 
| T120 | 
8877 | 
72 | 
0 | 
0 | 
| T121 | 
9992 | 
234 | 
0 | 
0 | 
| T143 | 
13578 | 
37 | 
0 | 
0 | 
| T145 | 
95724 | 
711 | 
0 | 
0 | 
| T146 | 
32483 | 
561 | 
0 | 
0 | 
| T147 | 
6228 | 
7 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6242 | 
0 | 
0 | 
| T58 | 
37157 | 
578 | 
0 | 
0 | 
| T60 | 
13817 | 
9 | 
0 | 
0 | 
| T112 | 
7089 | 
112 | 
0 | 
0 | 
| T116 | 
7938 | 
207 | 
0 | 
0 | 
| T120 | 
8877 | 
186 | 
0 | 
0 | 
| T121 | 
9992 | 
252 | 
0 | 
0 | 
| T143 | 
13578 | 
9 | 
0 | 
0 | 
| T144 | 
6626 | 
7 | 
0 | 
0 | 
| T145 | 
95724 | 
978 | 
0 | 
0 | 
| T146 | 
32483 | 
550 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6792 | 
0 | 
0 | 
| T58 | 
37157 | 
921 | 
0 | 
0 | 
| T60 | 
13817 | 
17 | 
0 | 
0 | 
| T112 | 
7089 | 
122 | 
0 | 
0 | 
| T116 | 
7938 | 
3 | 
0 | 
0 | 
| T120 | 
8877 | 
29 | 
0 | 
0 | 
| T121 | 
9992 | 
245 | 
0 | 
0 | 
| T143 | 
13578 | 
41 | 
0 | 
0 | 
| T144 | 
6626 | 
20 | 
0 | 
0 | 
| T145 | 
95724 | 
1241 | 
0 | 
0 | 
| T146 | 
32483 | 
376 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
6178 | 
0 | 
0 | 
| T58 | 
37157 | 
348 | 
0 | 
0 | 
| T60 | 
13817 | 
141 | 
0 | 
0 | 
| T112 | 
7089 | 
79 | 
0 | 
0 | 
| T116 | 
7938 | 
96 | 
0 | 
0 | 
| T120 | 
8877 | 
93 | 
0 | 
0 | 
| T121 | 
9992 | 
223 | 
0 | 
0 | 
| T143 | 
13578 | 
49 | 
0 | 
0 | 
| T144 | 
6626 | 
2 | 
0 | 
0 | 
| T145 | 
95724 | 
1081 | 
0 | 
0 | 
| T146 | 
32483 | 
646 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3056 | 
0 | 
0 | 
| T58 | 
37157 | 
227 | 
0 | 
0 | 
| T60 | 
13817 | 
117 | 
0 | 
0 | 
| T112 | 
7089 | 
32 | 
0 | 
0 | 
| T116 | 
7938 | 
51 | 
0 | 
0 | 
| T120 | 
8877 | 
35 | 
0 | 
0 | 
| T121 | 
9992 | 
64 | 
0 | 
0 | 
| T143 | 
13578 | 
29 | 
0 | 
0 | 
| T144 | 
6626 | 
23 | 
0 | 
0 | 
| T145 | 
95724 | 
406 | 
0 | 
0 | 
| T146 | 
32483 | 
296 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3000 | 
0 | 
0 | 
| T58 | 
37157 | 
251 | 
0 | 
0 | 
| T60 | 
13817 | 
64 | 
0 | 
0 | 
| T112 | 
7089 | 
67 | 
0 | 
0 | 
| T116 | 
7938 | 
55 | 
0 | 
0 | 
| T120 | 
8877 | 
31 | 
0 | 
0 | 
| T121 | 
9992 | 
109 | 
0 | 
0 | 
| T143 | 
13578 | 
35 | 
0 | 
0 | 
| T144 | 
6626 | 
9 | 
0 | 
0 | 
| T145 | 
95724 | 
436 | 
0 | 
0 | 
| T146 | 
32483 | 
247 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2748 | 
0 | 
0 | 
| T58 | 
37157 | 
357 | 
0 | 
0 | 
| T60 | 
13817 | 
41 | 
0 | 
0 | 
| T112 | 
7089 | 
103 | 
0 | 
0 | 
| T116 | 
7938 | 
29 | 
0 | 
0 | 
| T120 | 
8877 | 
33 | 
0 | 
0 | 
| T121 | 
9992 | 
44 | 
0 | 
0 | 
| T143 | 
13578 | 
77 | 
0 | 
0 | 
| T144 | 
6626 | 
12 | 
0 | 
0 | 
| T145 | 
95724 | 
294 | 
0 | 
0 | 
| T146 | 
32483 | 
259 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3358 | 
0 | 
0 | 
| T58 | 
37157 | 
329 | 
0 | 
0 | 
| T60 | 
13817 | 
44 | 
0 | 
0 | 
| T112 | 
7089 | 
119 | 
0 | 
0 | 
| T116 | 
7938 | 
26 | 
0 | 
0 | 
| T120 | 
8877 | 
59 | 
0 | 
0 | 
| T121 | 
9992 | 
72 | 
0 | 
0 | 
| T143 | 
13578 | 
12 | 
0 | 
0 | 
| T144 | 
6626 | 
13 | 
0 | 
0 | 
| T145 | 
95724 | 
424 | 
0 | 
0 | 
| T146 | 
32483 | 
291 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3321 | 
0 | 
0 | 
| T58 | 
37157 | 
268 | 
0 | 
0 | 
| T60 | 
13817 | 
34 | 
0 | 
0 | 
| T112 | 
7089 | 
43 | 
0 | 
0 | 
| T116 | 
7938 | 
109 | 
0 | 
0 | 
| T120 | 
8877 | 
2 | 
0 | 
0 | 
| T121 | 
9992 | 
109 | 
0 | 
0 | 
| T143 | 
13578 | 
61 | 
0 | 
0 | 
| T144 | 
6626 | 
8 | 
0 | 
0 | 
| T145 | 
95724 | 
476 | 
0 | 
0 | 
| T146 | 
32483 | 
491 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3160 | 
0 | 
0 | 
| T58 | 
37157 | 
220 | 
0 | 
0 | 
| T60 | 
13817 | 
71 | 
0 | 
0 | 
| T112 | 
7089 | 
127 | 
0 | 
0 | 
| T116 | 
7938 | 
96 | 
0 | 
0 | 
| T120 | 
8877 | 
107 | 
0 | 
0 | 
| T121 | 
9992 | 
38 | 
0 | 
0 | 
| T143 | 
13578 | 
23 | 
0 | 
0 | 
| T144 | 
6626 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
498 | 
0 | 
0 | 
| T146 | 
32483 | 
294 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2971 | 
0 | 
0 | 
| T58 | 
37157 | 
332 | 
0 | 
0 | 
| T60 | 
13817 | 
25 | 
0 | 
0 | 
| T112 | 
7089 | 
4 | 
0 | 
0 | 
| T116 | 
7938 | 
80 | 
0 | 
0 | 
| T120 | 
8877 | 
84 | 
0 | 
0 | 
| T121 | 
9992 | 
7 | 
0 | 
0 | 
| T143 | 
13578 | 
18 | 
0 | 
0 | 
| T144 | 
6626 | 
4 | 
0 | 
0 | 
| T145 | 
95724 | 
370 | 
0 | 
0 | 
| T146 | 
32483 | 
173 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3249 | 
0 | 
0 | 
| T58 | 
37157 | 
423 | 
0 | 
0 | 
| T60 | 
13817 | 
59 | 
0 | 
0 | 
| T112 | 
7089 | 
50 | 
0 | 
0 | 
| T116 | 
7938 | 
50 | 
0 | 
0 | 
| T120 | 
8877 | 
41 | 
0 | 
0 | 
| T121 | 
9992 | 
83 | 
0 | 
0 | 
| T143 | 
13578 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
448 | 
0 | 
0 | 
| T146 | 
32483 | 
424 | 
0 | 
0 | 
| T147 | 
6228 | 
6 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3015 | 
0 | 
0 | 
| T58 | 
37157 | 
278 | 
0 | 
0 | 
| T60 | 
13817 | 
46 | 
0 | 
0 | 
| T112 | 
7089 | 
11 | 
0 | 
0 | 
| T116 | 
7938 | 
50 | 
0 | 
0 | 
| T120 | 
8877 | 
17 | 
0 | 
0 | 
| T121 | 
9992 | 
13 | 
0 | 
0 | 
| T143 | 
13578 | 
93 | 
0 | 
0 | 
| T144 | 
6626 | 
4 | 
0 | 
0 | 
| T145 | 
95724 | 
286 | 
0 | 
0 | 
| T146 | 
32483 | 
253 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3079 | 
0 | 
0 | 
| T58 | 
37157 | 
225 | 
0 | 
0 | 
| T60 | 
13817 | 
18 | 
0 | 
0 | 
| T112 | 
7089 | 
14 | 
0 | 
0 | 
| T116 | 
7938 | 
91 | 
0 | 
0 | 
| T120 | 
8877 | 
71 | 
0 | 
0 | 
| T121 | 
9992 | 
98 | 
0 | 
0 | 
| T143 | 
13578 | 
42 | 
0 | 
0 | 
| T144 | 
6626 | 
11 | 
0 | 
0 | 
| T145 | 
95724 | 
486 | 
0 | 
0 | 
| T146 | 
32483 | 
227 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2902 | 
0 | 
0 | 
| T58 | 
37157 | 
321 | 
0 | 
0 | 
| T60 | 
13817 | 
23 | 
0 | 
0 | 
| T112 | 
7089 | 
18 | 
0 | 
0 | 
| T116 | 
7938 | 
43 | 
0 | 
0 | 
| T121 | 
9992 | 
76 | 
0 | 
0 | 
| T143 | 
13578 | 
36 | 
0 | 
0 | 
| T144 | 
6626 | 
36 | 
0 | 
0 | 
| T145 | 
95724 | 
456 | 
0 | 
0 | 
| T146 | 
32483 | 
191 | 
0 | 
0 | 
| T147 | 
6228 | 
27 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3517 | 
0 | 
0 | 
| T58 | 
37157 | 
245 | 
0 | 
0 | 
| T60 | 
13817 | 
57 | 
0 | 
0 | 
| T112 | 
7089 | 
61 | 
0 | 
0 | 
| T116 | 
7938 | 
103 | 
0 | 
0 | 
| T120 | 
8877 | 
53 | 
0 | 
0 | 
| T121 | 
9992 | 
51 | 
0 | 
0 | 
| T143 | 
13578 | 
77 | 
0 | 
0 | 
| T144 | 
6626 | 
30 | 
0 | 
0 | 
| T145 | 
95724 | 
459 | 
0 | 
0 | 
| T146 | 
32483 | 
349 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2884 | 
0 | 
0 | 
| T58 | 
37157 | 
335 | 
0 | 
0 | 
| T60 | 
13817 | 
47 | 
0 | 
0 | 
| T112 | 
7089 | 
10 | 
0 | 
0 | 
| T116 | 
7938 | 
6 | 
0 | 
0 | 
| T120 | 
8877 | 
12 | 
0 | 
0 | 
| T121 | 
9992 | 
65 | 
0 | 
0 | 
| T143 | 
13578 | 
68 | 
0 | 
0 | 
| T144 | 
6626 | 
2 | 
0 | 
0 | 
| T145 | 
95724 | 
387 | 
0 | 
0 | 
| T146 | 
32483 | 
110 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2890 | 
0 | 
0 | 
| T58 | 
37157 | 
299 | 
0 | 
0 | 
| T60 | 
13817 | 
53 | 
0 | 
0 | 
| T112 | 
7089 | 
36 | 
0 | 
0 | 
| T116 | 
7938 | 
7 | 
0 | 
0 | 
| T120 | 
8877 | 
58 | 
0 | 
0 | 
| T121 | 
9992 | 
9 | 
0 | 
0 | 
| T143 | 
13578 | 
22 | 
0 | 
0 | 
| T144 | 
6626 | 
6 | 
0 | 
0 | 
| T145 | 
95724 | 
382 | 
0 | 
0 | 
| T146 | 
32483 | 
402 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3139 | 
0 | 
0 | 
| T58 | 
37157 | 
373 | 
0 | 
0 | 
| T60 | 
13817 | 
53 | 
0 | 
0 | 
| T112 | 
7089 | 
83 | 
0 | 
0 | 
| T116 | 
7938 | 
45 | 
0 | 
0 | 
| T120 | 
8877 | 
33 | 
0 | 
0 | 
| T121 | 
9992 | 
92 | 
0 | 
0 | 
| T143 | 
13578 | 
45 | 
0 | 
0 | 
| T144 | 
6626 | 
20 | 
0 | 
0 | 
| T145 | 
95724 | 
350 | 
0 | 
0 | 
| T146 | 
32483 | 
372 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3238 | 
0 | 
0 | 
| T58 | 
37157 | 
319 | 
0 | 
0 | 
| T60 | 
13817 | 
28 | 
0 | 
0 | 
| T112 | 
7089 | 
53 | 
0 | 
0 | 
| T116 | 
7938 | 
52 | 
0 | 
0 | 
| T120 | 
8877 | 
33 | 
0 | 
0 | 
| T121 | 
9992 | 
122 | 
0 | 
0 | 
| T143 | 
13578 | 
17 | 
0 | 
0 | 
| T144 | 
6626 | 
13 | 
0 | 
0 | 
| T145 | 
95724 | 
456 | 
0 | 
0 | 
| T146 | 
32483 | 
310 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3012 | 
0 | 
0 | 
| T58 | 
37157 | 
266 | 
0 | 
0 | 
| T60 | 
13817 | 
33 | 
0 | 
0 | 
| T112 | 
7089 | 
45 | 
0 | 
0 | 
| T116 | 
7938 | 
35 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
7 | 
0 | 
0 | 
| T143 | 
13578 | 
47 | 
0 | 
0 | 
| T144 | 
6626 | 
13 | 
0 | 
0 | 
| T145 | 
95724 | 
416 | 
0 | 
0 | 
| T146 | 
32483 | 
306 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3093 | 
0 | 
0 | 
| T58 | 
37157 | 
308 | 
0 | 
0 | 
| T60 | 
13817 | 
42 | 
0 | 
0 | 
| T112 | 
7089 | 
10 | 
0 | 
0 | 
| T116 | 
7938 | 
98 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
118 | 
0 | 
0 | 
| T143 | 
13578 | 
20 | 
0 | 
0 | 
| T144 | 
6626 | 
32 | 
0 | 
0 | 
| T145 | 
95724 | 
475 | 
0 | 
0 | 
| T146 | 
32483 | 
210 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3278 | 
0 | 
0 | 
| T58 | 
37157 | 
304 | 
0 | 
0 | 
| T60 | 
13817 | 
64 | 
0 | 
0 | 
| T99 | 
8445 | 
5 | 
0 | 
0 | 
| T112 | 
7089 | 
59 | 
0 | 
0 | 
| T116 | 
7938 | 
34 | 
0 | 
0 | 
| T120 | 
8877 | 
102 | 
0 | 
0 | 
| T121 | 
9992 | 
92 | 
0 | 
0 | 
| T143 | 
13578 | 
61 | 
0 | 
0 | 
| T144 | 
6626 | 
13 | 
0 | 
0 | 
| T145 | 
95724 | 
467 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3230 | 
0 | 
0 | 
| T58 | 
37157 | 
286 | 
0 | 
0 | 
| T60 | 
13817 | 
47 | 
0 | 
0 | 
| T99 | 
8445 | 
4 | 
0 | 
0 | 
| T112 | 
7089 | 
55 | 
0 | 
0 | 
| T116 | 
7938 | 
60 | 
0 | 
0 | 
| T120 | 
8877 | 
39 | 
0 | 
0 | 
| T121 | 
9992 | 
77 | 
0 | 
0 | 
| T143 | 
13578 | 
40 | 
0 | 
0 | 
| T144 | 
6626 | 
14 | 
0 | 
0 | 
| T145 | 
95724 | 
395 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3176 | 
0 | 
0 | 
| T58 | 
37157 | 
329 | 
0 | 
0 | 
| T60 | 
13817 | 
106 | 
0 | 
0 | 
| T112 | 
7089 | 
86 | 
0 | 
0 | 
| T116 | 
7938 | 
35 | 
0 | 
0 | 
| T120 | 
8877 | 
12 | 
0 | 
0 | 
| T121 | 
9992 | 
55 | 
0 | 
0 | 
| T143 | 
13578 | 
51 | 
0 | 
0 | 
| T144 | 
6626 | 
4 | 
0 | 
0 | 
| T145 | 
95724 | 
488 | 
0 | 
0 | 
| T146 | 
32483 | 
246 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3147 | 
0 | 
0 | 
| T58 | 
37157 | 
225 | 
0 | 
0 | 
| T60 | 
13817 | 
50 | 
0 | 
0 | 
| T112 | 
7089 | 
9 | 
0 | 
0 | 
| T116 | 
7938 | 
12 | 
0 | 
0 | 
| T120 | 
8877 | 
71 | 
0 | 
0 | 
| T121 | 
9992 | 
88 | 
0 | 
0 | 
| T143 | 
13578 | 
24 | 
0 | 
0 | 
| T144 | 
6626 | 
5 | 
0 | 
0 | 
| T145 | 
95724 | 
287 | 
0 | 
0 | 
| T146 | 
32483 | 
476 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3132 | 
0 | 
0 | 
| T58 | 
37157 | 
275 | 
0 | 
0 | 
| T60 | 
13817 | 
34 | 
0 | 
0 | 
| T112 | 
7089 | 
29 | 
0 | 
0 | 
| T116 | 
7938 | 
57 | 
0 | 
0 | 
| T120 | 
8877 | 
67 | 
0 | 
0 | 
| T121 | 
9992 | 
107 | 
0 | 
0 | 
| T143 | 
13578 | 
26 | 
0 | 
0 | 
| T144 | 
6626 | 
11 | 
0 | 
0 | 
| T145 | 
95724 | 
577 | 
0 | 
0 | 
| T146 | 
32483 | 
268 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
3143 | 
0 | 
0 | 
| T58 | 
37157 | 
256 | 
0 | 
0 | 
| T60 | 
13817 | 
7 | 
0 | 
0 | 
| T99 | 
8445 | 
10 | 
0 | 
0 | 
| T112 | 
7089 | 
49 | 
0 | 
0 | 
| T116 | 
7938 | 
88 | 
0 | 
0 | 
| T120 | 
8877 | 
26 | 
0 | 
0 | 
| T121 | 
9992 | 
100 | 
0 | 
0 | 
| T143 | 
13578 | 
53 | 
0 | 
0 | 
| T144 | 
6626 | 
17 | 
0 | 
0 | 
| T145 | 
95724 | 
490 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1016 | 
0 | 
0 | 
| T58 | 
37157 | 
41 | 
0 | 
0 | 
| T60 | 
13817 | 
5 | 
0 | 
0 | 
| T112 | 
7089 | 
15 | 
0 | 
0 | 
| T116 | 
7938 | 
16 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
16 | 
0 | 
0 | 
| T143 | 
13578 | 
45 | 
0 | 
0 | 
| T144 | 
6626 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
81 | 
0 | 
0 | 
| T146 | 
32483 | 
33 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1031 | 
0 | 
0 | 
| T58 | 
37157 | 
53 | 
0 | 
0 | 
| T60 | 
13817 | 
12 | 
0 | 
0 | 
| T112 | 
7089 | 
14 | 
0 | 
0 | 
| T116 | 
7938 | 
5 | 
0 | 
0 | 
| T120 | 
8877 | 
7 | 
0 | 
0 | 
| T121 | 
9992 | 
12 | 
0 | 
0 | 
| T143 | 
13578 | 
22 | 
0 | 
0 | 
| T144 | 
6626 | 
16 | 
0 | 
0 | 
| T145 | 
95724 | 
87 | 
0 | 
0 | 
| T146 | 
32483 | 
56 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
999 | 
0 | 
0 | 
| T58 | 
37157 | 
47 | 
0 | 
0 | 
| T60 | 
13817 | 
9 | 
0 | 
0 | 
| T112 | 
7089 | 
13 | 
0 | 
0 | 
| T116 | 
7938 | 
11 | 
0 | 
0 | 
| T120 | 
8877 | 
19 | 
0 | 
0 | 
| T121 | 
9992 | 
15 | 
0 | 
0 | 
| T143 | 
13578 | 
67 | 
0 | 
0 | 
| T144 | 
6626 | 
5 | 
0 | 
0 | 
| T145 | 
95724 | 
97 | 
0 | 
0 | 
| T146 | 
32483 | 
67 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1111 | 
0 | 
0 | 
| T58 | 
37157 | 
64 | 
0 | 
0 | 
| T60 | 
13817 | 
15 | 
0 | 
0 | 
| T112 | 
7089 | 
4 | 
0 | 
0 | 
| T116 | 
7938 | 
9 | 
0 | 
0 | 
| T120 | 
8877 | 
14 | 
0 | 
0 | 
| T121 | 
9992 | 
8 | 
0 | 
0 | 
| T143 | 
13578 | 
39 | 
0 | 
0 | 
| T144 | 
6626 | 
17 | 
0 | 
0 | 
| T145 | 
95724 | 
104 | 
0 | 
0 | 
| T146 | 
32483 | 
52 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1436 | 
0 | 
0 | 
| T58 | 
37157 | 
100 | 
0 | 
0 | 
| T60 | 
13817 | 
11 | 
0 | 
0 | 
| T112 | 
7089 | 
19 | 
0 | 
0 | 
| T116 | 
7938 | 
15 | 
0 | 
0 | 
| T121 | 
9992 | 
13 | 
0 | 
0 | 
| T143 | 
13578 | 
74 | 
0 | 
0 | 
| T144 | 
6626 | 
16 | 
0 | 
0 | 
| T145 | 
95724 | 
160 | 
0 | 
0 | 
| T146 | 
32483 | 
83 | 
0 | 
0 | 
| T147 | 
6228 | 
8 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
2953 | 
0 | 
0 | 
| T27 | 
6936 | 
40 | 
0 | 
0 | 
| T28 | 
3649 | 
0 | 
0 | 
0 | 
| T29 | 
116935 | 
3 | 
0 | 
0 | 
| T30 | 
135495 | 
0 | 
0 | 
0 | 
| T148 | 
0 | 
29 | 
0 | 
0 | 
| T149 | 
0 | 
65 | 
0 | 
0 | 
| T150 | 
0 | 
19 | 
0 | 
0 | 
| T151 | 
0 | 
3 | 
0 | 
0 | 
| T152 | 
0 | 
36 | 
0 | 
0 | 
| T153 | 
0 | 
23 | 
0 | 
0 | 
| T154 | 
0 | 
32 | 
0 | 
0 | 
| T155 | 
0 | 
33 | 
0 | 
0 | 
| T156 | 
73880 | 
0 | 
0 | 
0 | 
| T157 | 
106331 | 
0 | 
0 | 
0 | 
| T158 | 
49582 | 
0 | 
0 | 
0 | 
| T159 | 
2471 | 
0 | 
0 | 
0 | 
| T160 | 
349403 | 
0 | 
0 | 
0 | 
| T161 | 
89772 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1154 | 
0 | 
0 | 
| T58 | 
37157 | 
54 | 
0 | 
0 | 
| T60 | 
13817 | 
16 | 
0 | 
0 | 
| T112 | 
7089 | 
10 | 
0 | 
0 | 
| T116 | 
7938 | 
15 | 
0 | 
0 | 
| T120 | 
8877 | 
4 | 
0 | 
0 | 
| T121 | 
9992 | 
10 | 
0 | 
0 | 
| T143 | 
13578 | 
62 | 
0 | 
0 | 
| T144 | 
6626 | 
5 | 
0 | 
0 | 
| T145 | 
95724 | 
102 | 
0 | 
0 | 
| T146 | 
32483 | 
43 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
976 | 
0 | 
0 | 
| T58 | 
37157 | 
50 | 
0 | 
0 | 
| T60 | 
13817 | 
13 | 
0 | 
0 | 
| T112 | 
7089 | 
8 | 
0 | 
0 | 
| T116 | 
7938 | 
7 | 
0 | 
0 | 
| T121 | 
9992 | 
29 | 
0 | 
0 | 
| T143 | 
13578 | 
57 | 
0 | 
0 | 
| T145 | 
95724 | 
87 | 
0 | 
0 | 
| T146 | 
32483 | 
36 | 
0 | 
0 | 
| T147 | 
6228 | 
26 | 
0 | 
0 | 
| T162 | 
14181 | 
7 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
964 | 
0 | 
0 | 
| T58 | 
37157 | 
35 | 
0 | 
0 | 
| T60 | 
13817 | 
26 | 
0 | 
0 | 
| T112 | 
7089 | 
10 | 
0 | 
0 | 
| T116 | 
7938 | 
14 | 
0 | 
0 | 
| T120 | 
8877 | 
4 | 
0 | 
0 | 
| T121 | 
9992 | 
6 | 
0 | 
0 | 
| T143 | 
13578 | 
7 | 
0 | 
0 | 
| T144 | 
6626 | 
18 | 
0 | 
0 | 
| T145 | 
95724 | 
62 | 
0 | 
0 | 
| T146 | 
32483 | 
46 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
884 | 
0 | 
0 | 
| T58 | 
37157 | 
32 | 
0 | 
0 | 
| T60 | 
13817 | 
15 | 
0 | 
0 | 
| T112 | 
7089 | 
7 | 
0 | 
0 | 
| T116 | 
7938 | 
16 | 
0 | 
0 | 
| T120 | 
8877 | 
3 | 
0 | 
0 | 
| T121 | 
9992 | 
9 | 
0 | 
0 | 
| T143 | 
13578 | 
24 | 
0 | 
0 | 
| T144 | 
6626 | 
10 | 
0 | 
0 | 
| T145 | 
95724 | 
79 | 
0 | 
0 | 
| T146 | 
32483 | 
47 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
825 | 
0 | 
0 | 
| T58 | 
37157 | 
44 | 
0 | 
0 | 
| T60 | 
13817 | 
8 | 
0 | 
0 | 
| T112 | 
7089 | 
12 | 
0 | 
0 | 
| T116 | 
7938 | 
10 | 
0 | 
0 | 
| T120 | 
8877 | 
6 | 
0 | 
0 | 
| T121 | 
9992 | 
14 | 
0 | 
0 | 
| T143 | 
13578 | 
17 | 
0 | 
0 | 
| T145 | 
95724 | 
43 | 
0 | 
0 | 
| T146 | 
32483 | 
33 | 
0 | 
0 | 
| T147 | 
6228 | 
8 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
836 | 
0 | 
0 | 
| T58 | 
37157 | 
25 | 
0 | 
0 | 
| T60 | 
13817 | 
18 | 
0 | 
0 | 
| T112 | 
7089 | 
8 | 
0 | 
0 | 
| T116 | 
7938 | 
3 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
19 | 
0 | 
0 | 
| T143 | 
13578 | 
44 | 
0 | 
0 | 
| T144 | 
6626 | 
6 | 
0 | 
0 | 
| T145 | 
95724 | 
57 | 
0 | 
0 | 
| T146 | 
32483 | 
39 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1445 | 
0 | 
0 | 
| T58 | 
37157 | 
94 | 
0 | 
0 | 
| T60 | 
13817 | 
23 | 
0 | 
0 | 
| T112 | 
7089 | 
25 | 
0 | 
0 | 
| T116 | 
7938 | 
8 | 
0 | 
0 | 
| T120 | 
8877 | 
11 | 
0 | 
0 | 
| T121 | 
9992 | 
29 | 
0 | 
0 | 
| T143 | 
13578 | 
57 | 
0 | 
0 | 
| T144 | 
6626 | 
8 | 
0 | 
0 | 
| T145 | 
95724 | 
180 | 
0 | 
0 | 
| T146 | 
32483 | 
94 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
903 | 
0 | 
0 | 
| T58 | 
37157 | 
29 | 
0 | 
0 | 
| T60 | 
13817 | 
9 | 
0 | 
0 | 
| T112 | 
7089 | 
7 | 
0 | 
0 | 
| T116 | 
7938 | 
5 | 
0 | 
0 | 
| T120 | 
8877 | 
13 | 
0 | 
0 | 
| T121 | 
9992 | 
6 | 
0 | 
0 | 
| T143 | 
13578 | 
58 | 
0 | 
0 | 
| T144 | 
6626 | 
3 | 
0 | 
0 | 
| T145 | 
95724 | 
66 | 
0 | 
0 | 
| T146 | 
32483 | 
44 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
1681 | 
0 | 
0 | 
| T58 | 
37157 | 
138 | 
0 | 
0 | 
| T60 | 
13817 | 
11 | 
0 | 
0 | 
| T112 | 
7089 | 
27 | 
0 | 
0 | 
| T116 | 
7938 | 
38 | 
0 | 
0 | 
| T120 | 
8877 | 
24 | 
0 | 
0 | 
| T121 | 
9992 | 
26 | 
0 | 
0 | 
| T143 | 
13578 | 
73 | 
0 | 
0 | 
| T144 | 
6626 | 
30 | 
0 | 
0 | 
| T145 | 
95724 | 
137 | 
0 | 
0 | 
| T146 | 
32483 | 
93 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
945 | 
0 | 
0 | 
| T58 | 
37157 | 
58 | 
0 | 
0 | 
| T60 | 
13817 | 
17 | 
0 | 
0 | 
| T112 | 
7089 | 
5 | 
0 | 
0 | 
| T116 | 
7938 | 
15 | 
0 | 
0 | 
| T120 | 
8877 | 
9 | 
0 | 
0 | 
| T121 | 
9992 | 
13 | 
0 | 
0 | 
| T143 | 
13578 | 
17 | 
0 | 
0 | 
| T144 | 
6626 | 
7 | 
0 | 
0 | 
| T145 | 
95724 | 
89 | 
0 | 
0 | 
| T146 | 
32483 | 
50 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
925 | 
0 | 
0 | 
| T58 | 
37157 | 
49 | 
0 | 
0 | 
| T60 | 
13817 | 
13 | 
0 | 
0 | 
| T112 | 
7089 | 
4 | 
0 | 
0 | 
| T116 | 
7938 | 
13 | 
0 | 
0 | 
| T120 | 
8877 | 
13 | 
0 | 
0 | 
| T121 | 
9992 | 
14 | 
0 | 
0 | 
| T143 | 
13578 | 
70 | 
0 | 
0 | 
| T144 | 
6626 | 
23 | 
0 | 
0 | 
| T145 | 
95724 | 
59 | 
0 | 
0 | 
| T146 | 
32483 | 
44 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
847 | 
0 | 
0 | 
| T58 | 
37157 | 
43 | 
0 | 
0 | 
| T60 | 
13817 | 
9 | 
0 | 
0 | 
| T112 | 
7089 | 
11 | 
0 | 
0 | 
| T116 | 
7938 | 
6 | 
0 | 
0 | 
| T120 | 
8877 | 
6 | 
0 | 
0 | 
| T121 | 
9992 | 
13 | 
0 | 
0 | 
| T143 | 
13578 | 
24 | 
0 | 
0 | 
| T144 | 
6626 | 
35 | 
0 | 
0 | 
| T145 | 
95724 | 
61 | 
0 | 
0 | 
| T146 | 
32483 | 
26 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
900 | 
0 | 
0 | 
| T58 | 
37157 | 
27 | 
0 | 
0 | 
| T60 | 
13817 | 
12 | 
0 | 
0 | 
| T112 | 
7089 | 
9 | 
0 | 
0 | 
| T120 | 
8877 | 
13 | 
0 | 
0 | 
| T121 | 
9992 | 
4 | 
0 | 
0 | 
| T143 | 
13578 | 
9 | 
0 | 
0 | 
| T144 | 
6626 | 
23 | 
0 | 
0 | 
| T145 | 
95724 | 
92 | 
0 | 
0 | 
| T146 | 
32483 | 
37 | 
0 | 
0 | 
| T147 | 
6228 | 
6 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
897 | 
0 | 
0 | 
| T58 | 
37157 | 
49 | 
0 | 
0 | 
| T60 | 
13817 | 
12 | 
0 | 
0 | 
| T112 | 
7089 | 
3 | 
0 | 
0 | 
| T116 | 
7938 | 
7 | 
0 | 
0 | 
| T120 | 
8877 | 
11 | 
0 | 
0 | 
| T121 | 
9992 | 
12 | 
0 | 
0 | 
| T143 | 
13578 | 
47 | 
0 | 
0 | 
| T144 | 
6626 | 
5 | 
0 | 
0 | 
| T145 | 
95724 | 
49 | 
0 | 
0 | 
| T146 | 
32483 | 
44 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
813 | 
0 | 
0 | 
| T58 | 
37157 | 
23 | 
0 | 
0 | 
| T60 | 
13817 | 
19 | 
0 | 
0 | 
| T83 | 
2407 | 
7 | 
0 | 
0 | 
| T112 | 
7089 | 
12 | 
0 | 
0 | 
| T116 | 
7938 | 
10 | 
0 | 
0 | 
| T121 | 
9992 | 
12 | 
0 | 
0 | 
| T143 | 
13578 | 
25 | 
0 | 
0 | 
| T145 | 
95724 | 
55 | 
0 | 
0 | 
| T146 | 
32483 | 
32 | 
0 | 
0 | 
| T147 | 
6228 | 
10 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
413899092 | 
700 | 
0 | 
0 | 
| T58 | 
37157 | 
42 | 
0 | 
0 | 
| T60 | 
13817 | 
3 | 
0 | 
0 | 
| T116 | 
7938 | 
2 | 
0 | 
0 | 
| T120 | 
8877 | 
8 | 
0 | 
0 | 
| T121 | 
9992 | 
6 | 
0 | 
0 | 
| T143 | 
13578 | 
11 | 
0 | 
0 | 
| T144 | 
6626 | 
24 | 
0 | 
0 | 
| T145 | 
95724 | 
51 | 
0 | 
0 | 
| T146 | 
32483 | 
40 | 
0 | 
0 | 
| T162 | 
14181 | 
5 | 
0 | 
0 |