Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3584429	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4246138

1

T1

1718

T2

4139

T3

1084

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4331146	1			T1	1716		T2	12427		T3	401
values[0x0]	1747417	1			T1	420		T2	2007		T3	439
values[0x1]	1752004	1			T1	462		T2	2093		T3	458

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2545298	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5285269

1

T1

1879

T2

8127

T3

1134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31006	1			T1	16		T2	66		T3	64
valid_sources[0x01]	30034	1			T1	9		T2	66		T3	16
valid_sources[0x02]	29923	1			T1	12		T2	57		T3	10
valid_sources[0x03]	30872	1			T1	10		T2	77		T3	10
valid_sources[0x04]	28654	1			T1	10		T2	74		T4	5
valid_sources[0x05]	28239	1			T1	7		T2	50		T5	2
valid_sources[0x06]	27848	1			T1	10		T2	65		T4	5
valid_sources[0x07]	30639	1			T1	3		T2	75		T4	4
valid_sources[0x08]	27934	1			T1	12		T2	52		T4	6
valid_sources[0x09]	32749	1			T1	13		T2	65		T4	7
valid_sources[0x0a]	29211	1			T1	4		T2	79		T3	26
valid_sources[0x0b]	50700	1			T1	9		T2	61		T4	4
valid_sources[0x0c]	28514	1			T1	16		T2	56		T4	7
valid_sources[0x0d]	29063	1			T1	7		T2	52		T4	3
valid_sources[0x0e]	29389	1			T1	13		T2	77		T4	6
valid_sources[0x0f]	26863	1			T1	3		T2	60		T4	2
valid_sources[0x10]	31973	1			T1	8		T2	50		T4	3
valid_sources[0x11]	29664	1			T1	8		T2	52		T4	6
valid_sources[0x12]	31257	1			T1	17		T2	72		T5	8
valid_sources[0x13]	34718	1			T1	11		T2	54		T4	4
valid_sources[0x14]	31362	1			T1	11		T2	64		T4	4
valid_sources[0x15]	29056	1			T1	8		T2	72		T4	3
valid_sources[0x16]	29225	1			T1	11		T2	69		T4	5
valid_sources[0x17]	28380	1			T1	6		T2	56		T4	3
valid_sources[0x18]	30208	1			T1	2		T2	77		T4	2
valid_sources[0x19]	28949	1			T1	15		T2	73		T4	4
valid_sources[0x1a]	28160	1			T1	13		T2	71		T3	19
valid_sources[0x1b]	31773	1			T1	11		T2	56		T4	2
valid_sources[0x1c]	28104	1			T1	16		T2	66		T4	3
valid_sources[0x1d]	29446	1			T1	11		T2	83		T4	4
valid_sources[0x1e]	30921	1			T1	24		T2	47		T4	2
valid_sources[0x1f]	30924	1			T1	7		T2	65		T4	9
valid_sources[0x20]	38420	1			T1	5		T2	87		T4	1
valid_sources[0x21]	34802	1			T1	14		T2	57		T4	1
valid_sources[0x22]	30280	1			T1	11		T2	71		T4	3
valid_sources[0x23]	30165	1			T1	5		T2	62		T4	4
valid_sources[0x24]	28573	1			T1	12		T2	63		T4	2
valid_sources[0x25]	28805	1			T1	5		T2	65		T4	7
valid_sources[0x26]	29357	1			T1	5		T2	59		T4	3
valid_sources[0x27]	31177	1			T1	12		T2	65		T4	3
valid_sources[0x28]	30650	1			T1	9		T2	75		T4	2
valid_sources[0x29]	33835	1			T1	6		T2	70		T3	1
valid_sources[0x2a]	30012	1			T1	18		T2	75		T4	4
valid_sources[0x2b]	29047	1			T1	11		T2	79		T4	3
valid_sources[0x2c]	30907	1			T1	7		T2	65		T4	2
valid_sources[0x2d]	29088	1			T1	14		T2	59		T3	20
valid_sources[0x2e]	26511	1			T1	15		T2	54		T4	2
valid_sources[0x2f]	32047	1			T1	13		T2	58		T4	3
valid_sources[0x30]	31082	1			T1	10		T2	54		T4	5
valid_sources[0x31]	28180	1			T1	10		T2	57		T4	1
valid_sources[0x32]	28593	1			T1	2		T2	55		T4	4
valid_sources[0x33]	29410	1			T1	6		T2	59		T3	34
valid_sources[0x34]	33135	1			T1	7		T2	57		T4	3
valid_sources[0x35]	29801	1			T1	11		T2	75		T4	8
valid_sources[0x36]	28240	1			T1	6		T2	69		T3	9
valid_sources[0x37]	29150	1			T1	10		T2	67		T4	7
valid_sources[0x38]	27896	1			T1	10		T2	51		T3	17
valid_sources[0x39]	28633	1			T1	10		T2	67		T3	44
valid_sources[0x3a]	28663	1			T1	12		T2	59		T4	4
valid_sources[0x3b]	31675	1			T1	16		T2	65		T4	5
valid_sources[0x3c]	40958	1			T1	16		T2	68		T4	3
valid_sources[0x3d]	27835	1			T1	11		T2	64		T4	2
valid_sources[0x3e]	27142	1			T1	8		T2	55		T4	2
valid_sources[0x3f]	26763	1			T1	12		T2	57		T4	4
valid_sources[0x40]	30325	1			T1	10		T2	67		T4	2
valid_sources[0x41]	31741	1			T1	10		T2	84		T4	10
valid_sources[0x42]	26786	1			T1	26		T2	57		T4	3
valid_sources[0x43]	27513	1			T1	9		T2	72		T4	6
valid_sources[0x44]	27227	1			T1	9		T2	61		T4	3
valid_sources[0x45]	28554	1			T1	15		T2	63		T4	5
valid_sources[0x46]	31720	1			T1	10		T2	41		T3	15
valid_sources[0x47]	31975	1			T1	6		T2	69		T4	5
valid_sources[0x48]	27905	1			T1	14		T2	56		T3	10
valid_sources[0x49]	34323	1			T1	8		T2	66		T3	35
valid_sources[0x4a]	28740	1			T1	7		T2	52		T4	4
valid_sources[0x4b]	30243	1			T1	7		T2	62		T4	6
valid_sources[0x4c]	27757	1			T1	26		T2	80		T3	31
valid_sources[0x4d]	30696	1			T1	8		T2	69		T4	9
valid_sources[0x4e]	31452	1			T1	13		T2	53		T3	1
valid_sources[0x4f]	29719	1			T1	3		T2	67		T3	46
valid_sources[0x50]	27131	1			T1	11		T2	59		T4	3
valid_sources[0x51]	27715	1			T1	9		T2	57		T4	8
valid_sources[0x52]	29816	1			T1	6		T2	75		T4	3
valid_sources[0x53]	30478	1			T1	8		T2	83		T3	28
valid_sources[0x54]	27478	1			T1	6		T2	60		T3	22
valid_sources[0x55]	32525	1			T1	12		T2	64		T4	5
valid_sources[0x56]	28230	1			T1	16		T2	65		T4	3
valid_sources[0x57]	35736	1			T1	11		T2	68		T4	2
valid_sources[0x58]	33724	1			T1	10		T2	60		T4	2
valid_sources[0x59]	30503	1			T1	17		T2	58		T4	4
valid_sources[0x5a]	31727	1			T1	23		T2	71		T3	67
valid_sources[0x5b]	26778	1			T1	7		T2	81		T4	2
valid_sources[0x5c]	29908	1			T1	7		T2	66		T4	1
valid_sources[0x5d]	31253	1			T1	7		T2	85		T4	4
valid_sources[0x5e]	29218	1			T1	13		T2	59		T4	5
valid_sources[0x5f]	29556	1			T1	14		T2	55		T4	5
valid_sources[0x60]	29518	1			T1	6		T2	62		T4	3
valid_sources[0x61]	32375	1			T1	3		T2	56		T3	84
valid_sources[0x62]	28981	1			T1	5		T2	48		T4	4
valid_sources[0x63]	29870	1			T1	10		T2	57		T4	5
valid_sources[0x64]	28474	1			T1	11		T2	64		T4	4
valid_sources[0x65]	28882	1			T1	8		T2	55		T4	3
valid_sources[0x66]	29464	1			T1	10		T2	68		T4	2
valid_sources[0x67]	27265	1			T1	12		T2	64		T4	3
valid_sources[0x68]	26493	1			T1	9		T2	67		T4	6
valid_sources[0x69]	29186	1			T1	18		T2	56		T3	14
valid_sources[0x6a]	33181	1			T1	10		T2	82		T4	3
valid_sources[0x6b]	29832	1			T1	15		T2	71		T4	5
valid_sources[0x6c]	83047	1			T1	9		T2	64		T3	55
valid_sources[0x6d]	63553	1			T1	8		T2	56		T4	4
valid_sources[0x6e]	26569	1			T1	6		T2	76		T4	4
valid_sources[0x6f]	31667	1			T1	9		T2	52		T4	3
valid_sources[0x70]	28431	1			T1	10		T2	68		T4	5
valid_sources[0x71]	41633	1			T1	16		T2	69		T3	18
valid_sources[0x72]	30269	1			T1	6		T2	63		T3	1
valid_sources[0x73]	28527	1			T1	8		T2	54		T4	2
valid_sources[0x74]	28331	1			T1	6		T2	72		T4	3
valid_sources[0x75]	30316	1			T1	10		T2	53		T4	1
valid_sources[0x76]	26630	1			T1	11		T2	62		T4	2
valid_sources[0x77]	28260	1			T1	1		T2	76		T4	1
valid_sources[0x78]	31152	1			T1	9		T2	70		T4	6
valid_sources[0x79]	31893	1			T1	10		T2	72		T5	16
valid_sources[0x7a]	29063	1			T1	5		T2	55		T4	3
valid_sources[0x7b]	26952	1			T1	2		T2	67		T4	2
valid_sources[0x7c]	29771	1			T1	12		T2	76		T4	3
valid_sources[0x7d]	34193	1			T1	14		T2	54		T4	1
valid_sources[0x7e]	31475	1			T1	5		T2	59		T4	2
valid_sources[0x7f]	32251	1			T1	9		T2	74		T4	3
valid_sources[0x80]	29711	1			T1	9		T2	66		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1072940

1

T1

840

T2

1115

T3

193

values[0x0]

all_enables

biggest_size

1597593

1

T1

418

T2

1495

T3

438

values[0x1]

all_enables

biggest_size

1575605

1

T1

460

T2

1529

T3

453