Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3606348

1

T1

880

T2

12388

T3

214

full_word

4247288

1

T1

1718

T2

4139

T3

1084

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7853206	1			T1	2598		T2	16527		T3	1298
auto[TlIntgErrCmd]	157	1			T61	7		T88	11		T90	7
auto[TlIntgErrData]	111	1			T61	6		T88	8		T90	5
auto[TlIntgErrBoth]	162	1			T61	7		T88	11		T90	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4334399

1

T1

1716

T2

12427

T3

401

auto[1]

3519237

1

T1

882

T2

4100

T3

897

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3260985	1			T1	876		T2	11312		T3	208
auto[TlIntgErrNone]	partial	auto[1]	344966	1			T1	4		T2	1076		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	1073204	1			T1	840		T2	1115		T3	193
auto[TlIntgErrNone]	full_word	auto[1]	3174051	1			T1	878		T2	3024		T3	891
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T61	1		T88	6		T90	3
auto[TlIntgErrCmd]	partial	auto[1]	82	1			T61	5		T88	5		T90	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T61	1		T134	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T135	1		T159	1		T160	1
auto[TlIntgErrData]	partial	auto[0]	64	1			T61	4		T88	4		T90	2
auto[TlIntgErrData]	partial	auto[1]	42	1			T61	2		T88	3		T90	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T88	1		T160	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T135	1		T160	1		T161	1
auto[TlIntgErrBoth]	partial	auto[0]	71	1			T61	5		T88	7		T90	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T61	1		T88	4		T90	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T162	1		T163	1		T164	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T61	1		T90	2		T134	1