Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	2879600	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	2879600	0	0
T1	48591	1664	0	0
T2	946766	0	0	0
T3	10062	1663	0	0
T4	30476	1663	0	0
T5	13729	0	0	0
T6	627459	9161	0	0
T7	15597	0	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	8320	0	0
T11	0	5829	0	0
T12	0	1663	0	0
T14	0	832	0	0
T49	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	3472779	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	3472779	0	0
T1	48591	833	0	0
T2	946766	0	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	0	0	0
T6	627459	14599	0	0
T7	15597	0	0	0
T8	20460	3899	0	0
T9	85733	0	0	0
T10	774843	17619	0	0
T11	0	13466	0	0
T12	0	832	0	0
T14	0	832	0	0
T49	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	195015	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	195015	0	0
T2	946766	922	0	0
T3	10062	0	0	0
T4	30476	0	0	0
T5	13729	28	0	0
T6	627459	192	0	0
T7	15597	56	0	0
T8	20460	0	0	0
T9	85733	0	0	0
T10	774843	367	0	0
T11	268485	1232	0	0
T15	0	1093	0	0
T27	0	1142	0	0
T29	0	205	0	0
T40	0	160	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	451792	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	451792	0	0
T2	946766	922	0	0
T3	10062	0	0	0
T4	30476	0	0	0
T5	13729	28	0	0
T6	627459	828	0	0
T7	15597	56	0	0
T8	20460	0	0	0
T9	85733	0	0	0
T10	774843	1171	0	0
T11	268485	5517	0	0
T15	0	1093	0	0
T27	0	1142	0	0
T29	0	1004	0	0
T40	0	537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	6156161	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	6156161	0	0
T1	48591	1774	0	0
T2	946766	15678	0	0
T3	10062	466	0	0
T4	30476	130	0	0
T5	13729	4008	0	0
T6	627459	1481	0	0
T7	15597	5170	0	0
T8	20460	505	0	0
T9	85733	246	0	0
T10	774843	12163	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430518798	12535929	0	0
DepthKnown_A	430518798	430385738	0	0
RvalidKnown_A	430518798	430385738	0	0
WreadyKnown_A	430518798	430385738	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	12535929	0	0
T1	48591	7662	0	0
T2	946766	15605	0	0
T3	10062	466	0	0
T4	30476	128	0	0
T5	13729	4008	0	0
T6	627459	6383	0	0
T7	15597	5170	0	0
T8	20460	2113	0	0
T9	85733	246	0	0
T10	774843	35028	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430518798	430385738	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0