Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Unreachable
1	1	Covered	T2,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T6,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T6,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	718015268	571400890	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	718015268	3730551	0	0
GntImpliesValid_A	718015268	3730551	0	0
GrantKnown_A	718015268	571400890	0	0
IdxKnown_A	718015268	571400890	0	0
IndexIsCorrect_A	718015268	3730551	0	0
LockArbDecision_A	718015268	0	0	0
NoReadyValidNoGrant_A	718015268	0	0	0
ReadyAndValidImplyGrant_A	718015268	3730551	0	0
ReqAndReadyImplyGrant_A	718015268	3730551	0	0
ReqImpliesValid_A	718015268	3730551	0	0
ReqStaysHighUntilGranted0_M	718015268	0	0	0
RoundRobin_A	718015268	2	0	956
ValidKnown_A	718015268	571400890	0	0
gen_data_port_assertion.DataFlow_A	718015268	3730551	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	571400890	0	0
T1	93783	93731	0	0
T2	1208222	1070450	0	0
T3	13158	10870	0	0
T4	134772	82268	0	0
T5	18001	15805	0	0
T6	1197081	909759	0	0
T7	21345	18253	0	0
T8	98604	59446	0	0
T9	136469	109929	0	0
T10	1281267	1024580	0	0
T11	736096	728842	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	225729	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	571400890	0	0
T1	93783	93731	0	0
T2	1208222	1070450	0	0
T3	13158	10870	0	0
T4	134772	82268	0	0
T5	18001	15805	0	0
T6	1197081	909759	0	0
T7	21345	18253	0	0
T8	98604	59446	0	0
T9	136469	109929	0	0
T10	1281267	1024580	0	0
T11	736096	728842	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	225729	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	571400890	0	0
T1	93783	93731	0	0
T2	1208222	1070450	0	0
T3	13158	10870	0	0
T4	134772	82268	0	0
T5	18001	15805	0	0
T6	1197081	909759	0	0
T7	21345	18253	0	0
T8	98604	59446	0	0
T9	136469	109929	0	0
T10	1281267	1024580	0	0
T11	736096	728842	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	225729	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	2	0	956
T16	539418	0	0	1
T22	369964	0	0	1
T30	363314	1	0	1
T44	86603	0	0	1
T50	158167	0	0	1
T51	620647	0	0	1
T52	0	1	0	0
T53	75104	0	0	1
T54	3228	0	0	1
T55	80905	0	0	1
T56	33590	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	571400890	0	0
T1	93783	93731	0	0
T2	1208222	1070450	0	0
T3	13158	10870	0	0
T4	134772	82268	0	0
T5	18001	15805	0	0
T6	1197081	909759	0	0
T7	21345	18253	0	0
T8	98604	59446	0	0
T9	136469	109929	0	0
T10	1281267	1024580	0	0
T11	736096	728842	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	225729	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	718015268	3730551	0	0
T1	48591	832	0	0
T2	1077494	7550	0	0
T3	11610	832	0	0
T4	82624	832	0	0
T5	15865	185	0	0
T6	1197081	9256	0	0
T7	21345	314	0	0
T8	98604	832	0	0
T9	136469	0	0	0
T10	1281267	10286	0	0
T11	1472192	16482	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	5947	0	0
T27	158522	6693	0	0
T28	544	16	0	0
T29	0	1000	0	0
T30	0	13772	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
1	0	Covered	T2,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T7
1	0	Unreachable
1	1	Covered	T2,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T2,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145140211	27880150	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145140211	663002	0	0
GntImpliesValid_A	145140211	663002	0	0
GrantKnown_A	145140211	27880150	0	0
IdxKnown_A	145140211	27880150	0	0
IndexIsCorrect_A	145140211	663002	0	0
LockArbDecision_A	145140211	0	0	0
NoReadyValidNoGrant_A	145140211	0	0	0
ReadyAndValidImplyGrant_A	145140211	663002	0	0
ReqAndReadyImplyGrant_A	145140211	663002	0	0
ReqImpliesValid_A	145140211	663002	0	0
ReqStaysHighUntilGranted0_M	145140211	0	0	0
RoundRobin_A	145140211	0	0	0
ValidKnown_A	145140211	27880150	0	0
gen_data_port_assertion.DataFlow_A	145140211	663002	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	27880150	0	0
T2	130728	123784	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	2136	0	0
T6	284811	0	0	0
T7	2874	2728	0	0
T8	39072	0	0	0
T9	25368	24296	0	0
T10	253212	49032	0	0
T11	736096	373360	0	0
T15	0	118216	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	27880150	0	0
T2	130728	123784	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	2136	0	0
T6	284811	0	0	0
T7	2874	2728	0	0
T8	39072	0	0	0
T9	25368	24296	0	0
T10	253212	49032	0	0
T11	736096	373360	0	0
T15	0	118216	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	27880150	0	0
T2	130728	123784	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	2136	0	0
T6	284811	0	0	0
T7	2874	2728	0	0
T8	39072	0	0	0
T9	25368	24296	0	0
T10	253212	49032	0	0
T11	736096	373360	0	0
T15	0	118216	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	27880150	0	0
T2	130728	123784	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	2136	0	0
T6	284811	0	0	0
T7	2874	2728	0	0
T8	39072	0	0	0
T9	25368	24296	0	0
T10	253212	49032	0	0
T11	736096	373360	0	0
T15	0	118216	0	0
T27	0	151704	0	0
T28	0	544	0	0
T29	0	27152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	663002	0	0
T2	130728	5170	0	0
T3	1548	0	0	0
T4	52148	0	0	0
T5	2136	134	0	0
T6	284811	0	0	0
T7	2874	237	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1578	0	0
T11	736096	4884	0	0
T15	0	4915	0	0
T27	0	6693	0	0
T28	0	16	0	0
T29	0	499	0	0
T30	0	2845	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T11
1	0	Covered	T6,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T6,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145140211	115871872	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145140211	781690	0	0
GntImpliesValid_A	145140211	781690	0	0
GrantKnown_A	145140211	115871872	0	0
IdxKnown_A	145140211	115871872	0	0
IndexIsCorrect_A	145140211	781690	0	0
LockArbDecision_A	145140211	0	0	0
NoReadyValidNoGrant_A	145140211	0	0	0
ReadyAndValidImplyGrant_A	145140211	781690	0	0
ReqAndReadyImplyGrant_A	145140211	781690	0	0
ReqImpliesValid_A	145140211	781690	0	0
ReqStaysHighUntilGranted0_M	145140211	0	0	0
RoundRobin_A	145140211	0	0	0
ValidKnown_A	145140211	115871872	0	0
gen_data_port_assertion.DataFlow_A	145140211	781690	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	115871872	0	0
T1	45192	45192	0	0
T2	130728	0	0	0
T3	1548	880	0	0
T4	52148	51878	0	0
T5	2136	0	0	0
T6	284811	282380	0	0
T7	2874	0	0	0
T8	39072	39072	0	0
T9	25368	0	0	0
T10	253212	200794	0	0
T11	0	355482	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	107513	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	115871872	0	0
T1	45192	45192	0	0
T2	130728	0	0	0
T3	1548	880	0	0
T4	52148	51878	0	0
T5	2136	0	0	0
T6	284811	282380	0	0
T7	2874	0	0	0
T8	39072	39072	0	0
T9	25368	0	0	0
T10	253212	200794	0	0
T11	0	355482	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	107513	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	115871872	0	0
T1	45192	45192	0	0
T2	130728	0	0	0
T3	1548	880	0	0
T4	52148	51878	0	0
T5	2136	0	0	0
T6	284811	282380	0	0
T7	2874	0	0	0
T8	39072	39072	0	0
T9	25368	0	0	0
T10	253212	200794	0	0
T11	0	355482	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	107513	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	115871872	0	0
T1	45192	45192	0	0
T2	130728	0	0	0
T3	1548	880	0	0
T4	52148	51878	0	0
T5	2136	0	0	0
T6	284811	282380	0	0
T7	2874	0	0	0
T8	39072	39072	0	0
T9	25368	0	0	0
T10	253212	200794	0	0
T11	0	355482	0	0
T12	0	105968	0	0
T14	0	106428	0	0
T15	0	107513	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145140211	781690	0	0
T6	284811	3228	0	0
T7	2874	0	0	0
T8	39072	0	0	0
T9	25368	0	0	0
T10	253212	1104	0	0
T11	736096	5035	0	0
T12	106884	0	0	0
T14	106889	0	0	0
T15	0	1032	0	0
T27	158522	0	0	0
T28	544	0	0	0
T29	0	501	0	0
T30	0	10927	0	0
T40	0	659	0	0
T41	0	5572	0	0
T50	0	1531	0	0
T51	0	3012	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427734846	427648868	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	427734846	2285859	0	0
GntImpliesValid_A	427734846	2285859	0	0
GrantKnown_A	427734846	427648868	0	0
IdxKnown_A	427734846	427648868	0	0
IndexIsCorrect_A	427734846	2285859	0	0
LockArbDecision_A	427734846	0	0	0
NoReadyValidNoGrant_A	427734846	0	0	0
ReadyAndValidImplyGrant_A	427734846	2285859	0	0
ReqAndReadyImplyGrant_A	427734846	2285859	0	0
ReqImpliesValid_A	427734846	2285859	0	0
ReqStaysHighUntilGranted0_M	427734846	0	0	0
RoundRobin_A	427734846	2	0	956
ValidKnown_A	427734846	427648868	0	0
gen_data_port_assertion.DataFlow_A	427734846	2285859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	427648868	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	427648868	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	427648868	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2	0	956
T16	539418	0	0	1
T22	369964	0	0	1
T30	363314	1	0	1
T44	86603	0	0	1
T50	158167	0	0	1
T51	620647	0	0	1
T52	0	1	0	0
T53	75104	0	0	1
T54	3228	0	0	1
T55	80905	0	0	1
T56	33590	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	427648868	0	0
T1	48591	48539	0	0
T2	946766	946666	0	0
T3	10062	9990	0	0
T4	30476	30390	0	0
T5	13729	13669	0	0
T6	627459	627379	0	0
T7	15597	15525	0	0
T8	20460	20374	0	0
T9	85733	85633	0	0
T10	774843	774754	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427734846	2285859	0	0
T1	48591	832	0	0
T2	946766	2380	0	0
T3	10062	832	0	0
T4	30476	832	0	0
T5	13729	51	0	0
T6	627459	6028	0	0
T7	15597	77	0	0
T8	20460	832	0	0
T9	85733	0	0	0
T10	774843	7604	0	0
T11	0	6563	0	0