Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
3597 |
0 |
0 |
T60 |
4279 |
1 |
0 |
0 |
T61 |
55303 |
4 |
0 |
0 |
T62 |
15679 |
220 |
0 |
0 |
T87 |
5046 |
9 |
0 |
0 |
T88 |
79409 |
5 |
0 |
0 |
T89 |
15463 |
153 |
0 |
0 |
T90 |
64041 |
5 |
0 |
0 |
T91 |
6964 |
236 |
0 |
0 |
T101 |
2384 |
3 |
0 |
0 |
T102 |
5542 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
963 |
0 |
0 |
T90 |
64041 |
60 |
0 |
0 |
T98 |
106326 |
107 |
0 |
0 |
T103 |
35586 |
41 |
0 |
0 |
T110 |
11345 |
10 |
0 |
0 |
T123 |
12469 |
22 |
0 |
0 |
T132 |
6968 |
11 |
0 |
0 |
T133 |
4642 |
5 |
0 |
0 |
T134 |
96209 |
83 |
0 |
0 |
T135 |
67792 |
85 |
0 |
0 |
T136 |
96698 |
105 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1045 |
0 |
0 |
T90 |
64041 |
32 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
48 |
0 |
0 |
T110 |
11345 |
7 |
0 |
0 |
T123 |
12469 |
57 |
0 |
0 |
T132 |
6968 |
45 |
0 |
0 |
T133 |
4642 |
5 |
0 |
0 |
T134 |
96209 |
39 |
0 |
0 |
T135 |
67792 |
81 |
0 |
0 |
T136 |
96698 |
125 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1628 |
0 |
0 |
T90 |
64041 |
69 |
0 |
0 |
T102 |
5542 |
17 |
0 |
0 |
T103 |
35586 |
75 |
0 |
0 |
T110 |
11345 |
48 |
0 |
0 |
T123 |
12469 |
32 |
0 |
0 |
T132 |
6968 |
39 |
0 |
0 |
T133 |
4642 |
12 |
0 |
0 |
T134 |
96209 |
130 |
0 |
0 |
T135 |
67792 |
125 |
0 |
0 |
T136 |
96698 |
206 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
12180 |
0 |
0 |
T90 |
64041 |
593 |
0 |
0 |
T102 |
5542 |
99 |
0 |
0 |
T103 |
35586 |
692 |
0 |
0 |
T110 |
11345 |
18 |
0 |
0 |
T123 |
12469 |
62 |
0 |
0 |
T132 |
6968 |
6 |
0 |
0 |
T133 |
4642 |
9 |
0 |
0 |
T134 |
96209 |
1244 |
0 |
0 |
T135 |
67792 |
1337 |
0 |
0 |
T136 |
96698 |
1602 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
12181 |
0 |
0 |
T90 |
64041 |
629 |
0 |
0 |
T98 |
106326 |
2116 |
0 |
0 |
T102 |
5542 |
10 |
0 |
0 |
T103 |
35586 |
256 |
0 |
0 |
T110 |
11345 |
292 |
0 |
0 |
T123 |
12469 |
22 |
0 |
0 |
T132 |
6968 |
5 |
0 |
0 |
T134 |
96209 |
945 |
0 |
0 |
T135 |
67792 |
1270 |
0 |
0 |
T136 |
96698 |
1925 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
14462 |
0 |
0 |
T90 |
64041 |
755 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
993 |
0 |
0 |
T110 |
11345 |
388 |
0 |
0 |
T123 |
12469 |
8 |
0 |
0 |
T132 |
6968 |
16 |
0 |
0 |
T133 |
4642 |
123 |
0 |
0 |
T134 |
96209 |
1149 |
0 |
0 |
T135 |
67792 |
1337 |
0 |
0 |
T136 |
96698 |
1543 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
14584 |
0 |
0 |
T90 |
64041 |
870 |
0 |
0 |
T102 |
5542 |
5 |
0 |
0 |
T103 |
35586 |
931 |
0 |
0 |
T110 |
11345 |
244 |
0 |
0 |
T123 |
12469 |
25 |
0 |
0 |
T132 |
6968 |
33 |
0 |
0 |
T133 |
4642 |
132 |
0 |
0 |
T134 |
96209 |
1013 |
0 |
0 |
T135 |
67792 |
1893 |
0 |
0 |
T136 |
96698 |
2155 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
12804 |
0 |
0 |
T90 |
64041 |
714 |
0 |
0 |
T102 |
5542 |
130 |
0 |
0 |
T103 |
35586 |
907 |
0 |
0 |
T110 |
11345 |
413 |
0 |
0 |
T123 |
12469 |
17 |
0 |
0 |
T132 |
6968 |
11 |
0 |
0 |
T133 |
4642 |
111 |
0 |
0 |
T134 |
96209 |
1218 |
0 |
0 |
T135 |
67792 |
943 |
0 |
0 |
T136 |
96698 |
2031 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
11615 |
0 |
0 |
T90 |
64041 |
433 |
0 |
0 |
T102 |
5542 |
138 |
0 |
0 |
T103 |
35586 |
659 |
0 |
0 |
T110 |
11345 |
235 |
0 |
0 |
T123 |
12469 |
26 |
0 |
0 |
T132 |
6968 |
44 |
0 |
0 |
T133 |
4642 |
110 |
0 |
0 |
T134 |
96209 |
1119 |
0 |
0 |
T135 |
67792 |
1445 |
0 |
0 |
T136 |
96698 |
1547 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
11540 |
0 |
0 |
T90 |
64041 |
758 |
0 |
0 |
T102 |
5542 |
145 |
0 |
0 |
T103 |
35586 |
769 |
0 |
0 |
T110 |
11345 |
109 |
0 |
0 |
T123 |
12469 |
30 |
0 |
0 |
T132 |
6968 |
8 |
0 |
0 |
T133 |
4642 |
120 |
0 |
0 |
T134 |
96209 |
960 |
0 |
0 |
T135 |
67792 |
1249 |
0 |
0 |
T136 |
96698 |
1333 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
11654 |
0 |
0 |
T90 |
64041 |
616 |
0 |
0 |
T102 |
5542 |
10 |
0 |
0 |
T103 |
35586 |
503 |
0 |
0 |
T110 |
11345 |
378 |
0 |
0 |
T123 |
12469 |
38 |
0 |
0 |
T132 |
6968 |
14 |
0 |
0 |
T133 |
4642 |
123 |
0 |
0 |
T134 |
96209 |
1310 |
0 |
0 |
T135 |
67792 |
669 |
0 |
0 |
T136 |
96698 |
1562 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5691 |
0 |
0 |
T90 |
64041 |
221 |
0 |
0 |
T102 |
5542 |
51 |
0 |
0 |
T103 |
35586 |
414 |
0 |
0 |
T110 |
11345 |
51 |
0 |
0 |
T123 |
12469 |
39 |
0 |
0 |
T132 |
6968 |
40 |
0 |
0 |
T133 |
4642 |
1 |
0 |
0 |
T134 |
96209 |
363 |
0 |
0 |
T135 |
67792 |
535 |
0 |
0 |
T136 |
96698 |
878 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
6187 |
0 |
0 |
T90 |
64041 |
307 |
0 |
0 |
T102 |
5542 |
60 |
0 |
0 |
T103 |
35586 |
140 |
0 |
0 |
T110 |
11345 |
104 |
0 |
0 |
T123 |
12469 |
32 |
0 |
0 |
T132 |
6968 |
14 |
0 |
0 |
T133 |
4642 |
5 |
0 |
0 |
T134 |
96209 |
315 |
0 |
0 |
T135 |
67792 |
768 |
0 |
0 |
T136 |
96698 |
917 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5278 |
0 |
0 |
T90 |
64041 |
213 |
0 |
0 |
T102 |
5542 |
9 |
0 |
0 |
T103 |
35586 |
199 |
0 |
0 |
T110 |
11345 |
96 |
0 |
0 |
T123 |
12469 |
73 |
0 |
0 |
T132 |
6968 |
21 |
0 |
0 |
T133 |
4642 |
41 |
0 |
0 |
T134 |
96209 |
372 |
0 |
0 |
T135 |
67792 |
523 |
0 |
0 |
T136 |
96698 |
659 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
4992 |
0 |
0 |
T90 |
64041 |
273 |
0 |
0 |
T102 |
5542 |
12 |
0 |
0 |
T103 |
35586 |
282 |
0 |
0 |
T110 |
11345 |
43 |
0 |
0 |
T123 |
12469 |
43 |
0 |
0 |
T132 |
6968 |
18 |
0 |
0 |
T133 |
4642 |
53 |
0 |
0 |
T134 |
96209 |
415 |
0 |
0 |
T135 |
67792 |
368 |
0 |
0 |
T136 |
96698 |
700 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5156 |
0 |
0 |
T90 |
64041 |
192 |
0 |
0 |
T102 |
5542 |
56 |
0 |
0 |
T103 |
35586 |
226 |
0 |
0 |
T110 |
11345 |
20 |
0 |
0 |
T123 |
12469 |
21 |
0 |
0 |
T132 |
6968 |
25 |
0 |
0 |
T133 |
4642 |
8 |
0 |
0 |
T134 |
96209 |
377 |
0 |
0 |
T135 |
67792 |
335 |
0 |
0 |
T136 |
96698 |
834 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5401 |
0 |
0 |
T90 |
64041 |
263 |
0 |
0 |
T102 |
5542 |
9 |
0 |
0 |
T103 |
35586 |
369 |
0 |
0 |
T110 |
11345 |
13 |
0 |
0 |
T123 |
12469 |
15 |
0 |
0 |
T132 |
6968 |
47 |
0 |
0 |
T133 |
4642 |
8 |
0 |
0 |
T134 |
96209 |
450 |
0 |
0 |
T135 |
67792 |
538 |
0 |
0 |
T136 |
96698 |
729 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
4949 |
0 |
0 |
T89 |
15463 |
2 |
0 |
0 |
T90 |
64041 |
307 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
211 |
0 |
0 |
T123 |
12469 |
30 |
0 |
0 |
T132 |
6968 |
13 |
0 |
0 |
T133 |
4642 |
9 |
0 |
0 |
T134 |
96209 |
434 |
0 |
0 |
T135 |
67792 |
504 |
0 |
0 |
T136 |
96698 |
731 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5405 |
0 |
0 |
T90 |
64041 |
313 |
0 |
0 |
T102 |
5542 |
11 |
0 |
0 |
T103 |
35586 |
207 |
0 |
0 |
T110 |
11345 |
16 |
0 |
0 |
T123 |
12469 |
21 |
0 |
0 |
T132 |
6968 |
23 |
0 |
0 |
T133 |
4642 |
63 |
0 |
0 |
T134 |
96209 |
547 |
0 |
0 |
T135 |
67792 |
435 |
0 |
0 |
T136 |
96698 |
688 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5755 |
0 |
0 |
T90 |
64041 |
246 |
0 |
0 |
T102 |
5542 |
39 |
0 |
0 |
T103 |
35586 |
345 |
0 |
0 |
T110 |
11345 |
130 |
0 |
0 |
T123 |
12469 |
47 |
0 |
0 |
T132 |
6968 |
47 |
0 |
0 |
T133 |
4642 |
47 |
0 |
0 |
T134 |
96209 |
359 |
0 |
0 |
T135 |
67792 |
449 |
0 |
0 |
T136 |
96698 |
920 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5281 |
0 |
0 |
T90 |
64041 |
359 |
0 |
0 |
T102 |
5542 |
10 |
0 |
0 |
T103 |
35586 |
312 |
0 |
0 |
T110 |
11345 |
149 |
0 |
0 |
T123 |
12469 |
30 |
0 |
0 |
T132 |
6968 |
23 |
0 |
0 |
T133 |
4642 |
57 |
0 |
0 |
T134 |
96209 |
425 |
0 |
0 |
T135 |
67792 |
476 |
0 |
0 |
T136 |
96698 |
781 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5680 |
0 |
0 |
T90 |
64041 |
290 |
0 |
0 |
T102 |
5542 |
55 |
0 |
0 |
T103 |
35586 |
365 |
0 |
0 |
T110 |
11345 |
50 |
0 |
0 |
T123 |
12469 |
34 |
0 |
0 |
T132 |
6968 |
44 |
0 |
0 |
T133 |
4642 |
6 |
0 |
0 |
T134 |
96209 |
366 |
0 |
0 |
T135 |
67792 |
500 |
0 |
0 |
T136 |
96698 |
785 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5202 |
0 |
0 |
T90 |
64041 |
314 |
0 |
0 |
T102 |
5542 |
8 |
0 |
0 |
T103 |
35586 |
252 |
0 |
0 |
T110 |
11345 |
65 |
0 |
0 |
T123 |
12469 |
38 |
0 |
0 |
T132 |
6968 |
24 |
0 |
0 |
T133 |
4642 |
57 |
0 |
0 |
T134 |
96209 |
374 |
0 |
0 |
T135 |
67792 |
672 |
0 |
0 |
T136 |
96698 |
597 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5160 |
0 |
0 |
T90 |
64041 |
310 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
262 |
0 |
0 |
T110 |
11345 |
61 |
0 |
0 |
T123 |
12469 |
52 |
0 |
0 |
T132 |
6968 |
17 |
0 |
0 |
T133 |
4642 |
4 |
0 |
0 |
T134 |
96209 |
418 |
0 |
0 |
T135 |
67792 |
550 |
0 |
0 |
T136 |
96698 |
714 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5970 |
0 |
0 |
T90 |
64041 |
378 |
0 |
0 |
T102 |
5542 |
9 |
0 |
0 |
T103 |
35586 |
441 |
0 |
0 |
T110 |
11345 |
83 |
0 |
0 |
T123 |
12469 |
32 |
0 |
0 |
T132 |
6968 |
31 |
0 |
0 |
T133 |
4642 |
2 |
0 |
0 |
T134 |
96209 |
402 |
0 |
0 |
T135 |
67792 |
531 |
0 |
0 |
T136 |
96698 |
751 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5503 |
0 |
0 |
T90 |
64041 |
264 |
0 |
0 |
T102 |
5542 |
9 |
0 |
0 |
T103 |
35586 |
393 |
0 |
0 |
T110 |
11345 |
165 |
0 |
0 |
T123 |
12469 |
59 |
0 |
0 |
T132 |
6968 |
8 |
0 |
0 |
T133 |
4642 |
50 |
0 |
0 |
T134 |
96209 |
493 |
0 |
0 |
T135 |
67792 |
652 |
0 |
0 |
T136 |
96698 |
678 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5552 |
0 |
0 |
T90 |
64041 |
207 |
0 |
0 |
T102 |
5542 |
1 |
0 |
0 |
T103 |
35586 |
282 |
0 |
0 |
T110 |
11345 |
125 |
0 |
0 |
T123 |
12469 |
21 |
0 |
0 |
T132 |
6968 |
53 |
0 |
0 |
T133 |
4642 |
2 |
0 |
0 |
T134 |
96209 |
505 |
0 |
0 |
T135 |
67792 |
573 |
0 |
0 |
T136 |
96698 |
874 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5765 |
0 |
0 |
T90 |
64041 |
308 |
0 |
0 |
T102 |
5542 |
1 |
0 |
0 |
T103 |
35586 |
264 |
0 |
0 |
T110 |
11345 |
130 |
0 |
0 |
T123 |
12469 |
15 |
0 |
0 |
T132 |
6968 |
33 |
0 |
0 |
T133 |
4642 |
68 |
0 |
0 |
T134 |
96209 |
258 |
0 |
0 |
T135 |
67792 |
572 |
0 |
0 |
T136 |
96698 |
876 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5675 |
0 |
0 |
T90 |
64041 |
411 |
0 |
0 |
T102 |
5542 |
1 |
0 |
0 |
T103 |
35586 |
246 |
0 |
0 |
T110 |
11345 |
88 |
0 |
0 |
T123 |
12469 |
50 |
0 |
0 |
T132 |
6968 |
42 |
0 |
0 |
T133 |
4642 |
53 |
0 |
0 |
T134 |
96209 |
382 |
0 |
0 |
T135 |
67792 |
326 |
0 |
0 |
T136 |
96698 |
914 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
4804 |
0 |
0 |
T90 |
64041 |
262 |
0 |
0 |
T102 |
5542 |
54 |
0 |
0 |
T103 |
35586 |
250 |
0 |
0 |
T110 |
11345 |
61 |
0 |
0 |
T123 |
12469 |
38 |
0 |
0 |
T132 |
6968 |
3 |
0 |
0 |
T133 |
4642 |
45 |
0 |
0 |
T134 |
96209 |
450 |
0 |
0 |
T135 |
67792 |
520 |
0 |
0 |
T136 |
96698 |
576 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5799 |
0 |
0 |
T90 |
64041 |
253 |
0 |
0 |
T98 |
106326 |
780 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
319 |
0 |
0 |
T110 |
11345 |
58 |
0 |
0 |
T123 |
12469 |
40 |
0 |
0 |
T132 |
6968 |
8 |
0 |
0 |
T134 |
96209 |
493 |
0 |
0 |
T135 |
67792 |
772 |
0 |
0 |
T136 |
96698 |
895 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5635 |
0 |
0 |
T90 |
64041 |
329 |
0 |
0 |
T98 |
106326 |
872 |
0 |
0 |
T102 |
5542 |
50 |
0 |
0 |
T103 |
35586 |
286 |
0 |
0 |
T110 |
11345 |
66 |
0 |
0 |
T123 |
12469 |
34 |
0 |
0 |
T133 |
4642 |
2 |
0 |
0 |
T134 |
96209 |
344 |
0 |
0 |
T135 |
67792 |
621 |
0 |
0 |
T136 |
96698 |
751 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
6014 |
0 |
0 |
T90 |
64041 |
182 |
0 |
0 |
T98 |
106326 |
1104 |
0 |
0 |
T102 |
5542 |
66 |
0 |
0 |
T103 |
35586 |
251 |
0 |
0 |
T110 |
11345 |
82 |
0 |
0 |
T123 |
12469 |
21 |
0 |
0 |
T133 |
4642 |
46 |
0 |
0 |
T134 |
96209 |
428 |
0 |
0 |
T135 |
67792 |
489 |
0 |
0 |
T136 |
96698 |
791 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
5009 |
0 |
0 |
T90 |
64041 |
345 |
0 |
0 |
T102 |
5542 |
58 |
0 |
0 |
T103 |
35586 |
234 |
0 |
0 |
T110 |
11345 |
8 |
0 |
0 |
T123 |
12469 |
64 |
0 |
0 |
T132 |
6968 |
1 |
0 |
0 |
T133 |
4642 |
7 |
0 |
0 |
T134 |
96209 |
359 |
0 |
0 |
T135 |
67792 |
754 |
0 |
0 |
T136 |
96698 |
533 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
6084 |
0 |
0 |
T90 |
64041 |
285 |
0 |
0 |
T98 |
106326 |
872 |
0 |
0 |
T102 |
5542 |
11 |
0 |
0 |
T103 |
35586 |
329 |
0 |
0 |
T110 |
11345 |
94 |
0 |
0 |
T123 |
12469 |
32 |
0 |
0 |
T132 |
6968 |
14 |
0 |
0 |
T134 |
96209 |
480 |
0 |
0 |
T135 |
67792 |
598 |
0 |
0 |
T136 |
96698 |
976 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1413 |
0 |
0 |
T89 |
15463 |
4 |
0 |
0 |
T90 |
64041 |
67 |
0 |
0 |
T102 |
5542 |
15 |
0 |
0 |
T103 |
35586 |
50 |
0 |
0 |
T123 |
12469 |
10 |
0 |
0 |
T132 |
6968 |
8 |
0 |
0 |
T133 |
4642 |
1 |
0 |
0 |
T134 |
96209 |
111 |
0 |
0 |
T135 |
67792 |
149 |
0 |
0 |
T136 |
96698 |
198 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1366 |
0 |
0 |
T62 |
15679 |
7 |
0 |
0 |
T90 |
64041 |
38 |
0 |
0 |
T102 |
5542 |
19 |
0 |
0 |
T103 |
35586 |
32 |
0 |
0 |
T123 |
12469 |
49 |
0 |
0 |
T132 |
6968 |
7 |
0 |
0 |
T133 |
4642 |
5 |
0 |
0 |
T134 |
96209 |
105 |
0 |
0 |
T135 |
67792 |
116 |
0 |
0 |
T136 |
96698 |
185 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1328 |
0 |
0 |
T90 |
64041 |
55 |
0 |
0 |
T102 |
5542 |
8 |
0 |
0 |
T103 |
35586 |
44 |
0 |
0 |
T110 |
11345 |
23 |
0 |
0 |
T123 |
12469 |
18 |
0 |
0 |
T132 |
6968 |
4 |
0 |
0 |
T133 |
4642 |
4 |
0 |
0 |
T134 |
96209 |
57 |
0 |
0 |
T135 |
67792 |
132 |
0 |
0 |
T136 |
96698 |
181 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1421 |
0 |
0 |
T90 |
64041 |
77 |
0 |
0 |
T102 |
5542 |
11 |
0 |
0 |
T103 |
35586 |
70 |
0 |
0 |
T110 |
11345 |
13 |
0 |
0 |
T123 |
12469 |
43 |
0 |
0 |
T132 |
6968 |
2 |
0 |
0 |
T133 |
4642 |
4 |
0 |
0 |
T134 |
96209 |
92 |
0 |
0 |
T135 |
67792 |
102 |
0 |
0 |
T136 |
96698 |
174 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
2141 |
0 |
0 |
T90 |
64041 |
53 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
88 |
0 |
0 |
T110 |
11345 |
12 |
0 |
0 |
T123 |
12469 |
56 |
0 |
0 |
T132 |
6968 |
35 |
0 |
0 |
T133 |
4642 |
1 |
0 |
0 |
T134 |
96209 |
123 |
0 |
0 |
T135 |
67792 |
206 |
0 |
0 |
T136 |
96698 |
289 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
3943 |
0 |
0 |
T18 |
532943 |
24 |
0 |
0 |
T21 |
0 |
28 |
0 |
0 |
T137 |
0 |
10 |
0 |
0 |
T138 |
0 |
29 |
0 |
0 |
T139 |
0 |
50 |
0 |
0 |
T140 |
0 |
39 |
0 |
0 |
T141 |
0 |
11 |
0 |
0 |
T142 |
0 |
17 |
0 |
0 |
T143 |
0 |
46 |
0 |
0 |
T144 |
0 |
26 |
0 |
0 |
T145 |
886 |
0 |
0 |
0 |
T146 |
9933 |
0 |
0 |
0 |
T147 |
134803 |
0 |
0 |
0 |
T148 |
1662 |
0 |
0 |
0 |
T149 |
388607 |
0 |
0 |
0 |
T150 |
11108 |
0 |
0 |
0 |
T151 |
170709 |
0 |
0 |
0 |
T152 |
16383 |
0 |
0 |
0 |
T153 |
1345 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1428 |
0 |
0 |
T62 |
15679 |
9 |
0 |
0 |
T90 |
64041 |
51 |
0 |
0 |
T102 |
5542 |
18 |
0 |
0 |
T103 |
35586 |
60 |
0 |
0 |
T123 |
12469 |
37 |
0 |
0 |
T132 |
6968 |
17 |
0 |
0 |
T133 |
4642 |
7 |
0 |
0 |
T134 |
96209 |
112 |
0 |
0 |
T135 |
67792 |
120 |
0 |
0 |
T136 |
96698 |
167 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1326 |
0 |
0 |
T90 |
64041 |
57 |
0 |
0 |
T102 |
5542 |
16 |
0 |
0 |
T103 |
35586 |
80 |
0 |
0 |
T110 |
11345 |
4 |
0 |
0 |
T123 |
12469 |
23 |
0 |
0 |
T132 |
6968 |
40 |
0 |
0 |
T133 |
4642 |
9 |
0 |
0 |
T134 |
96209 |
59 |
0 |
0 |
T135 |
67792 |
129 |
0 |
0 |
T136 |
96698 |
170 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
984 |
0 |
0 |
T90 |
64041 |
48 |
0 |
0 |
T102 |
5542 |
13 |
0 |
0 |
T103 |
35586 |
49 |
0 |
0 |
T110 |
11345 |
10 |
0 |
0 |
T123 |
12469 |
20 |
0 |
0 |
T132 |
6968 |
10 |
0 |
0 |
T133 |
4642 |
7 |
0 |
0 |
T134 |
96209 |
59 |
0 |
0 |
T135 |
67792 |
82 |
0 |
0 |
T136 |
96698 |
100 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
944 |
0 |
0 |
T90 |
64041 |
56 |
0 |
0 |
T102 |
5542 |
3 |
0 |
0 |
T103 |
35586 |
24 |
0 |
0 |
T110 |
11345 |
23 |
0 |
0 |
T123 |
12469 |
53 |
0 |
0 |
T132 |
6968 |
8 |
0 |
0 |
T133 |
4642 |
8 |
0 |
0 |
T134 |
96209 |
72 |
0 |
0 |
T135 |
67792 |
87 |
0 |
0 |
T136 |
96698 |
101 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1129 |
0 |
0 |
T90 |
64041 |
62 |
0 |
0 |
T102 |
5542 |
3 |
0 |
0 |
T103 |
35586 |
40 |
0 |
0 |
T110 |
11345 |
12 |
0 |
0 |
T123 |
12469 |
44 |
0 |
0 |
T132 |
6968 |
55 |
0 |
0 |
T133 |
4642 |
5 |
0 |
0 |
T134 |
96209 |
63 |
0 |
0 |
T135 |
67792 |
74 |
0 |
0 |
T136 |
96698 |
105 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1123 |
0 |
0 |
T90 |
64041 |
48 |
0 |
0 |
T102 |
5542 |
2 |
0 |
0 |
T103 |
35586 |
25 |
0 |
0 |
T110 |
11345 |
10 |
0 |
0 |
T123 |
12469 |
76 |
0 |
0 |
T132 |
6968 |
21 |
0 |
0 |
T133 |
4642 |
6 |
0 |
0 |
T134 |
96209 |
68 |
0 |
0 |
T135 |
67792 |
72 |
0 |
0 |
T136 |
96698 |
95 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
2227 |
0 |
0 |
T90 |
64041 |
127 |
0 |
0 |
T102 |
5542 |
12 |
0 |
0 |
T103 |
35586 |
111 |
0 |
0 |
T110 |
11345 |
23 |
0 |
0 |
T123 |
12469 |
50 |
0 |
0 |
T132 |
6968 |
28 |
0 |
0 |
T133 |
4642 |
1 |
0 |
0 |
T134 |
96209 |
149 |
0 |
0 |
T135 |
67792 |
162 |
0 |
0 |
T136 |
96698 |
297 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1063 |
0 |
0 |
T90 |
64041 |
40 |
0 |
0 |
T102 |
5542 |
15 |
0 |
0 |
T103 |
35586 |
41 |
0 |
0 |
T110 |
11345 |
16 |
0 |
0 |
T123 |
12469 |
31 |
0 |
0 |
T132 |
6968 |
2 |
0 |
0 |
T133 |
4642 |
8 |
0 |
0 |
T134 |
96209 |
70 |
0 |
0 |
T135 |
67792 |
66 |
0 |
0 |
T136 |
96698 |
98 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
2404 |
0 |
0 |
T90 |
64041 |
97 |
0 |
0 |
T102 |
5542 |
5 |
0 |
0 |
T103 |
35586 |
147 |
0 |
0 |
T110 |
11345 |
50 |
0 |
0 |
T123 |
12469 |
24 |
0 |
0 |
T132 |
6968 |
9 |
0 |
0 |
T133 |
4642 |
20 |
0 |
0 |
T134 |
96209 |
143 |
0 |
0 |
T135 |
67792 |
280 |
0 |
0 |
T136 |
96698 |
375 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1424 |
0 |
0 |
T90 |
64041 |
72 |
0 |
0 |
T102 |
5542 |
16 |
0 |
0 |
T103 |
35586 |
60 |
0 |
0 |
T110 |
11345 |
12 |
0 |
0 |
T123 |
12469 |
70 |
0 |
0 |
T132 |
6968 |
22 |
0 |
0 |
T133 |
4642 |
9 |
0 |
0 |
T134 |
96209 |
93 |
0 |
0 |
T135 |
67792 |
110 |
0 |
0 |
T136 |
96698 |
151 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
842 |
0 |
0 |
T90 |
64041 |
42 |
0 |
0 |
T102 |
5542 |
7 |
0 |
0 |
T103 |
35586 |
32 |
0 |
0 |
T110 |
11345 |
14 |
0 |
0 |
T123 |
12469 |
52 |
0 |
0 |
T132 |
6968 |
4 |
0 |
0 |
T133 |
4642 |
4 |
0 |
0 |
T134 |
96209 |
45 |
0 |
0 |
T135 |
67792 |
50 |
0 |
0 |
T136 |
96698 |
117 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
902 |
0 |
0 |
T90 |
64041 |
17 |
0 |
0 |
T102 |
5542 |
9 |
0 |
0 |
T103 |
35586 |
40 |
0 |
0 |
T110 |
11345 |
7 |
0 |
0 |
T123 |
12469 |
74 |
0 |
0 |
T132 |
6968 |
11 |
0 |
0 |
T133 |
4642 |
9 |
0 |
0 |
T134 |
96209 |
79 |
0 |
0 |
T135 |
67792 |
78 |
0 |
0 |
T136 |
96698 |
130 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
930 |
0 |
0 |
T90 |
64041 |
44 |
0 |
0 |
T102 |
5542 |
5 |
0 |
0 |
T103 |
35586 |
28 |
0 |
0 |
T110 |
11345 |
11 |
0 |
0 |
T123 |
12469 |
29 |
0 |
0 |
T132 |
6968 |
6 |
0 |
0 |
T133 |
4642 |
3 |
0 |
0 |
T134 |
96209 |
62 |
0 |
0 |
T135 |
67792 |
91 |
0 |
0 |
T136 |
96698 |
124 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
880 |
0 |
0 |
T90 |
64041 |
33 |
0 |
0 |
T102 |
5542 |
12 |
0 |
0 |
T103 |
35586 |
44 |
0 |
0 |
T110 |
11345 |
7 |
0 |
0 |
T123 |
12469 |
26 |
0 |
0 |
T132 |
6968 |
5 |
0 |
0 |
T133 |
4642 |
6 |
0 |
0 |
T134 |
96209 |
62 |
0 |
0 |
T135 |
67792 |
75 |
0 |
0 |
T136 |
96698 |
105 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
980 |
0 |
0 |
T90 |
64041 |
27 |
0 |
0 |
T98 |
106326 |
138 |
0 |
0 |
T103 |
35586 |
47 |
0 |
0 |
T110 |
11345 |
13 |
0 |
0 |
T123 |
12469 |
72 |
0 |
0 |
T132 |
6968 |
42 |
0 |
0 |
T133 |
4642 |
3 |
0 |
0 |
T134 |
96209 |
39 |
0 |
0 |
T135 |
67792 |
87 |
0 |
0 |
T136 |
96698 |
100 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
430518798 |
1007 |
0 |
0 |
T90 |
64041 |
58 |
0 |
0 |
T98 |
106326 |
113 |
0 |
0 |
T102 |
5542 |
13 |
0 |
0 |
T103 |
35586 |
45 |
0 |
0 |
T110 |
11345 |
14 |
0 |
0 |
T123 |
12469 |
18 |
0 |
0 |
T132 |
6968 |
11 |
0 |
0 |
T134 |
96209 |
80 |
0 |
0 |
T135 |
67792 |
99 |
0 |
0 |
T136 |
96698 |
119 |
0 |
0 |