Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4101106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4567746

1

T1

5

T2

2196

T3

38186

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4817614	1			T1	1		T2	2676		T3	55070
values[0x0]	1924552	1			T1	2		T2	435		T3	19600
values[0x1]	1926686	1			T1	2		T2	445		T3	19569

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2897312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5771540

1

T1

5

T2

2462

T3

55918

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35316	1			T2	17		T3	152		T4	23
valid_sources[0x01]	32939	1			T2	11		T3	347		T4	20
valid_sources[0x02]	32528	1			T2	10		T3	146		T4	26
valid_sources[0x03]	33890	1			T2	11		T3	580		T4	21
valid_sources[0x04]	30326	1			T2	11		T3	336		T4	11
valid_sources[0x05]	30546	1			T2	14		T3	64		T4	16
valid_sources[0x06]	34364	1			T2	12		T3	608		T4	9
valid_sources[0x07]	33497	1			T2	25		T3	184		T4	23
valid_sources[0x08]	34076	1			T2	12		T3	440		T4	12
valid_sources[0x09]	31563	1			T2	21		T3	152		T4	21
valid_sources[0x0a]	31092	1			T2	19		T3	459		T4	15
valid_sources[0x0b]	36956	1			T2	3		T3	431		T4	15
valid_sources[0x0c]	39390	1			T2	11		T3	189		T4	21
valid_sources[0x0d]	31289	1			T2	11		T3	291		T4	19
valid_sources[0x0e]	31534	1			T2	16		T3	401		T4	21
valid_sources[0x0f]	33638	1			T2	25		T3	119		T4	16
valid_sources[0x10]	31688	1			T2	20		T3	309		T4	13
valid_sources[0x11]	30097	1			T2	18		T3	283		T4	12
valid_sources[0x12]	32458	1			T2	10		T3	509		T4	14
valid_sources[0x13]	31617	1			T2	16		T3	543		T4	8
valid_sources[0x14]	36515	1			T2	11		T3	405		T4	18
valid_sources[0x15]	31221	1			T2	10		T3	250		T4	11
valid_sources[0x16]	32303	1			T2	19		T3	667		T4	11
valid_sources[0x17]	35639	1			T2	13		T3	73		T4	14
valid_sources[0x18]	33289	1			T2	31		T3	211		T4	15
valid_sources[0x19]	48243	1			T2	12		T3	15		T4	12
valid_sources[0x1a]	37147	1			T2	2		T3	551		T4	16
valid_sources[0x1b]	33132	1			T2	14		T3	553		T4	18
valid_sources[0x1c]	33698	1			T2	3		T3	298		T4	15
valid_sources[0x1d]	32331	1			T2	17		T3	384		T4	12
valid_sources[0x1e]	31372	1			T2	17		T3	171		T4	13
valid_sources[0x1f]	31215	1			T2	8		T3	543		T4	14
valid_sources[0x20]	30425	1			T2	21		T3	125		T4	14
valid_sources[0x21]	33891	1			T2	34		T3	311		T4	13
valid_sources[0x22]	31978	1			T2	20		T3	915		T4	19
valid_sources[0x23]	33269	1			T2	8		T3	368		T4	14
valid_sources[0x24]	31435	1			T2	16		T3	132		T4	13
valid_sources[0x25]	37282	1			T2	32		T3	680		T4	20
valid_sources[0x26]	34965	1			T2	12		T3	181		T4	16
valid_sources[0x27]	32904	1			T2	18		T3	452		T4	16
valid_sources[0x28]	55143	1			T2	15		T3	75		T4	26
valid_sources[0x29]	33797	1			T2	13		T3	594		T4	21
valid_sources[0x2a]	31919	1			T2	13		T3	256		T4	20
valid_sources[0x2b]	36890	1			T2	10		T3	280		T4	20
valid_sources[0x2c]	43540	1			T2	21		T3	246		T4	21
valid_sources[0x2d]	32699	1			T2	5		T3	473		T4	24
valid_sources[0x2e]	32995	1			T2	7		T3	190		T4	25
valid_sources[0x2f]	30177	1			T2	16		T3	266		T4	23
valid_sources[0x30]	31896	1			T2	10		T3	728		T4	15
valid_sources[0x31]	29269	1			T2	5		T3	446		T4	23
valid_sources[0x32]	28826	1			T2	12		T3	159		T4	13
valid_sources[0x33]	30078	1			T2	20		T3	630		T4	15
valid_sources[0x34]	33624	1			T2	27		T3	143		T4	16
valid_sources[0x35]	34014	1			T2	17		T3	496		T4	18
valid_sources[0x36]	58484	1			T2	21		T3	218		T4	21
valid_sources[0x37]	35882	1			T2	21		T3	268		T4	23
valid_sources[0x38]	29254	1			T2	11		T3	701		T4	15
valid_sources[0x39]	32588	1			T2	3		T3	756		T4	13
valid_sources[0x3a]	35622	1			T1	3		T2	16		T3	438
valid_sources[0x3b]	31093	1			T2	5		T3	216		T4	21
valid_sources[0x3c]	32887	1			T2	4		T3	97		T4	12
valid_sources[0x3d]	32512	1			T2	10		T3	710		T4	22
valid_sources[0x3e]	35533	1			T2	23		T3	458		T4	18
valid_sources[0x3f]	31020	1			T2	22		T3	385		T4	20
valid_sources[0x40]	33280	1			T2	17		T3	234		T4	12
valid_sources[0x41]	28822	1			T2	6		T3	254		T4	25
valid_sources[0x42]	38720	1			T2	6		T3	208		T4	17
valid_sources[0x43]	33667	1			T2	11		T3	523		T4	19
valid_sources[0x44]	32080	1			T2	12		T3	484		T4	24
valid_sources[0x45]	35607	1			T2	17		T3	151		T4	22
valid_sources[0x46]	33722	1			T2	28		T3	591		T4	16
valid_sources[0x47]	29834	1			T2	12		T3	486		T4	13
valid_sources[0x48]	33395	1			T2	12		T3	230		T4	14
valid_sources[0x49]	33965	1			T2	22		T3	223		T4	25
valid_sources[0x4a]	29137	1			T2	4		T3	263		T4	20
valid_sources[0x4b]	42443	1			T2	28		T3	179		T4	11
valid_sources[0x4c]	37138	1			T2	11		T3	206		T4	15
valid_sources[0x4d]	50338	1			T2	25		T3	124		T4	18
valid_sources[0x4e]	31062	1			T2	11		T3	670		T4	21
valid_sources[0x4f]	28889	1			T2	14		T3	348		T4	23
valid_sources[0x50]	37801	1			T2	12		T3	459		T4	21
valid_sources[0x51]	34749	1			T2	10		T3	370		T4	21
valid_sources[0x52]	31171	1			T2	12		T3	1186		T4	17
valid_sources[0x53]	31026	1			T2	33		T3	344		T4	13
valid_sources[0x54]	32321	1			T2	22		T3	646		T4	14
valid_sources[0x55]	36312	1			T2	6		T3	206		T4	14
valid_sources[0x56]	29719	1			T2	34		T3	179		T4	16
valid_sources[0x57]	40316	1			T2	9		T3	423		T4	19
valid_sources[0x58]	32920	1			T2	6		T3	179		T4	14
valid_sources[0x59]	28920	1			T2	8		T3	375		T4	25
valid_sources[0x5a]	32330	1			T2	12		T3	362		T4	20
valid_sources[0x5b]	32926	1			T2	3		T3	779		T4	14
valid_sources[0x5c]	37118	1			T2	16		T3	437		T4	18
valid_sources[0x5d]	34101	1			T2	2		T3	533		T4	20
valid_sources[0x5e]	28257	1			T2	12		T3	659		T4	22
valid_sources[0x5f]	31876	1			T2	13		T3	376		T4	24
valid_sources[0x60]	31625	1			T2	10		T3	426		T4	14
valid_sources[0x61]	33992	1			T2	22		T3	390		T4	15
valid_sources[0x62]	36222	1			T2	23		T3	627		T4	21
valid_sources[0x63]	31643	1			T2	16		T3	126		T4	15
valid_sources[0x64]	30934	1			T2	24		T3	311		T4	16
valid_sources[0x65]	33534	1			T2	11		T3	378		T4	14
valid_sources[0x66]	32179	1			T2	28		T3	257		T4	15
valid_sources[0x67]	33237	1			T2	7		T3	1201		T4	16
valid_sources[0x68]	32225	1			T2	7		T3	262		T4	28
valid_sources[0x69]	42097	1			T2	4		T3	536		T4	20
valid_sources[0x6a]	48322	1			T2	14		T3	232		T4	15
valid_sources[0x6b]	38560	1			T2	16		T3	35		T4	21
valid_sources[0x6c]	31923	1			T2	17		T3	361		T4	16
valid_sources[0x6d]	34760	1			T2	6		T3	774		T4	18
valid_sources[0x6e]	34968	1			T2	18		T3	530		T4	21
valid_sources[0x6f]	38126	1			T2	11		T3	173		T4	18
valid_sources[0x70]	30639	1			T2	13		T3	223		T4	23
valid_sources[0x71]	31919	1			T2	32		T3	246		T4	14
valid_sources[0x72]	43298	1			T2	19		T3	237		T4	15
valid_sources[0x73]	37863	1			T2	17		T3	294		T4	20
valid_sources[0x74]	37786	1			T3	1035		T4	20		T6	3
valid_sources[0x75]	34134	1			T2	5		T3	422		T4	17
valid_sources[0x76]	37038	1			T2	11		T3	105		T4	23
valid_sources[0x77]	32224	1			T2	7		T3	327		T4	14
valid_sources[0x78]	31455	1			T2	7		T3	367		T4	20
valid_sources[0x79]	33548	1			T2	13		T3	267		T4	17
valid_sources[0x7a]	38904	1			T2	19		T3	185		T4	17
valid_sources[0x7b]	32757	1			T2	5		T3	407		T4	15
valid_sources[0x7c]	34505	1			T2	8		T3	127		T4	22
valid_sources[0x7d]	29563	1			T2	7		T3	298		T4	26
valid_sources[0x7e]	32959	1			T2	3		T3	169		T4	16
valid_sources[0x7f]	29299	1			T2	32		T3	386		T4	20
valid_sources[0x80]	32378	1			T2	11		T3	117		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1092341

1

T1

1

T2

1318

T3

5162

values[0x0]

all_enables

biggest_size

1750390

1

T1

2

T2

434

T3

16750

values[0x1]

all_enables

biggest_size

1725015

1

T1

2

T2

444

T3

16274