Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4120682

1

T2

1360

T3

56053

T4

1882

full_word

4568808

1

T1

5

T2

2196

T3

38186

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8689080	1			T1	5		T2	3556		T3	94239
auto[TlIntgErrCmd]	128	1			T53	6		T87	10		T89	3
auto[TlIntgErrData]	134	1			T53	6		T87	10		T89	5
auto[TlIntgErrBoth]	148	1			T53	8		T87	10		T89	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4821141

1

T1

1

T2

2676

T3

55070

auto[1]

3868349

1

T1

4

T2

880

T3

39169

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3728383	1			T2	1358		T3	49908		T4	1873
auto[TlIntgErrNone]	partial	auto[1]	391928	1			T2	2		T3	6145		T4	9
auto[TlIntgErrNone]	full_word	auto[0]	1092575	1			T1	1		T2	1318		T3	5162
auto[TlIntgErrNone]	full_word	auto[1]	3476194	1			T1	4		T2	878		T3	33024
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T53	1		T87	4		T103	4
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T53	5		T87	5		T89	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T87	1		T89	1		T151	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T152	1		T153	2		T154	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T53	1		T87	5		T89	2
auto[TlIntgErrData]	partial	auto[1]	55	1			T53	4		T87	5		T89	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T53	1		T106	1		T97	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T155	1		T151	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T53	2		T87	5		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T53	5		T87	4		T89	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T87	1		T97	1		T157	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T53	1		T89	1		T103	2