Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	651642571	3553267	0	0
gen_wmask[1].MaskCheckPortA_A	651642571	3553267	0	0
gen_wmask[2].MaskCheckPortA_A	651642571	3553267	0	0
gen_wmask[3].MaskCheckPortA_A	651642571	3553267	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651642571	3553267	0	0
T2	116237	832	0	0
T3	1402502	25056	0	0
T4	92857	832	0	0
T5	230678	832	0	0
T6	516519	0	0	0
T7	1206119	19685	0	0
T8	231762	18284	0	0
T9	197095	832	0	0
T10	991	0	0	0
T11	106264	832	0	0
T12	0	11615	0	0
T14	0	7867	0	0
T23	3665	282	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651642571	3553267	0	0
T2	116237	832	0	0
T3	1402502	25056	0	0
T4	92857	832	0	0
T5	230678	832	0	0
T6	516519	0	0	0
T7	1206119	19685	0	0
T8	231762	18284	0	0
T9	197095	832	0	0
T10	991	0	0	0
T11	106264	832	0	0
T12	0	11615	0	0
T14	0	7867	0	0
T23	3665	282	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651642571	3553267	0	0
T2	116237	832	0	0
T3	1402502	25056	0	0
T4	92857	832	0	0
T5	230678	832	0	0
T6	516519	0	0	0
T7	1206119	19685	0	0
T8	231762	18284	0	0
T9	197095	832	0	0
T10	991	0	0	0
T11	106264	832	0	0
T12	0	11615	0	0
T14	0	7867	0	0
T23	3665	282	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	651642571	3553267	0	0
T2	116237	832	0	0
T3	1402502	25056	0	0
T4	92857	832	0	0
T5	230678	832	0	0
T6	516519	0	0	0
T7	1206119	19685	0	0
T8	231762	18284	0	0
T9	197095	832	0	0
T10	991	0	0	0
T11	106264	832	0	0
T12	0	11615	0	0
T14	0	7867	0	0
T23	3665	282	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	497641328	2186405	0	0
gen_wmask[1].MaskCheckPortA_A	497641328	2186405	0	0
gen_wmask[2].MaskCheckPortA_A	497641328	2186405	0	0
gen_wmask[3].MaskCheckPortA_A	497641328	2186405	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2186405	0	0
T2	116237	832	0	0
T3	449440	12958	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	9584	0	0
T8	117239	11476	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	10816	0	0
T23	0	20	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2186405	0	0
T2	116237	832	0	0
T3	449440	12958	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	9584	0	0
T8	117239	11476	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	10816	0	0
T23	0	20	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2186405	0	0
T2	116237	832	0	0
T3	449440	12958	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	9584	0	0
T8	117239	11476	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	10816	0	0
T23	0	20	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2186405	0	0
T2	116237	832	0	0
T3	449440	12958	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	9584	0	0
T8	117239	11476	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	10816	0	0
T23	0	20	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	154001243	1366862	0	0
gen_wmask[1].MaskCheckPortA_A	154001243	1366862	0	0
gen_wmask[2].MaskCheckPortA_A	154001243	1366862	0	0
gen_wmask[3].MaskCheckPortA_A	154001243	1366862	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	1366862	0	0
T3	953062	12098	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	10101	0	0
T8	114523	6808	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	7867	0	0
T23	3665	262	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	1366862	0	0
T3	953062	12098	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	10101	0	0
T8	114523	6808	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	7867	0	0
T23	3665	262	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	1366862	0	0
T3	953062	12098	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	10101	0	0
T8	114523	6808	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	7867	0	0
T23	3665	262	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	1366862	0	0
T3	953062	12098	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	10101	0	0
T8	114523	6808	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	7867	0	0
T23	3665	262	0	0
T24	81800	0	0	0
T25	0	10312	0	0
T26	0	895	0	0
T27	0	4301	0	0
T28	0	2370	0	0