Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	3034671	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	3034671	0	0
T2	116237	832	0	0
T3	449440	14146	0	0
T4	70462	1663	0	0
T5	205398	1671	0	0
T6	416021	0	0	0
T7	494648	10813	0	0
T8	117239	19126	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	1663	0	0
T12	0	14140	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	3370858	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	3370858	0	0
T2	116237	2617	0	0
T3	449440	21918	0	0
T4	70462	832	0	0
T5	205398	840	0	0
T6	416021	0	0	0
T7	494648	8320	0	0
T8	117239	10816	0	0
T9	150263	3778	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	10816	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	198147	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	198147	0	0
T3	449440	2068	0	0
T4	70462	0	0	0
T5	205398	0	0	0
T6	416021	0	0	0
T7	494648	1233	0	0
T8	117239	805	0	0
T9	150263	0	0	0
T10	991	0	0	0
T11	89060	0	0	0
T12	0	192	0	0
T14	0	1872	0	0
T23	16117	67	0	0
T25	0	1154	0	0
T26	0	232	0	0
T27	0	425	0	0
T28	0	612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	488556	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	488556	0	0
T3	449440	6009	0	0
T4	70462	0	0	0
T5	205398	0	0	0
T6	416021	0	0	0
T7	494648	1233	0	0
T8	117239	805	0	0
T9	150263	0	0	0
T10	991	0	0	0
T11	89060	0	0	0
T12	0	192	0	0
T14	0	5748	0	0
T23	16117	67	0	0
T25	0	3290	0	0
T26	0	992	0	0
T27	0	425	0	0
T28	0	612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	6987409	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	6987409	0	0
T1	1272	5	0	0
T2	116237	2724	0	0
T3	449440	86700	0	0
T4	70462	3716	0	0
T5	205398	6211	0	0
T6	416021	840	0	0
T7	494648	91827	0	0
T8	117239	16892	0	0
T9	150263	47	0	0
T10	991	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500117165	15260148	0	0
DepthKnown_A	500117165	499985014	0	0
RvalidKnown_A	500117165	499985014	0	0
WreadyKnown_A	500117165	499985014	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	15260148	0	0
T1	1272	5	0	0
T2	116237	8191	0	0
T3	449440	254461	0	0
T4	70462	3716	0	0
T5	205398	26665	0	0
T6	416021	840	0	0
T7	494648	91383	0	0
T8	117239	16772	0	0
T9	150263	190	0	0
T10	991	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500117165	499985014	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0