Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	805643814	650138870	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	805643814	3963977	0	0
GntImpliesValid_A	805643814	3963977	0	0
GrantKnown_A	805643814	650138870	0	0
IdxKnown_A	805643814	650138870	0	0
IndexIsCorrect_A	805643814	3963977	0	0
LockArbDecision_A	805643814	0	0	0
NoReadyValidNoGrant_A	805643814	0	0	0
ReadyAndValidImplyGrant_A	805643814	3963977	0	0
ReqAndReadyImplyGrant_A	805643814	3963977	0	0
ReqImpliesValid_A	805643814	3963977	0	0
ReqStaysHighUntilGranted0_M	805643814	0	0	0
RoundRobin_A	805643814	7	0	955
ValidKnown_A	805643814	650138870	0	0
gen_data_port_assertion.DataFlow_A	805643814	3963977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	650138870	0	0
T1	1344	1247	0	0
T2	159053	137566	0	0
T3	2355564	1387481	0	0
T4	115252	92757	0	0
T5	255958	230429	0	0
T6	617017	512047	0	0
T7	1917590	1199221	0	0
T8	346285	326624	0	0
T9	243927	197004	0	0
T10	991	937	0	0
T11	34408	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	650138870	0	0
T1	1344	1247	0	0
T2	159053	137566	0	0
T3	2355564	1387481	0	0
T4	115252	92757	0	0
T5	255958	230429	0	0
T6	617017	512047	0	0
T7	1917590	1199221	0	0
T8	346285	326624	0	0
T9	243927	197004	0	0
T10	991	937	0	0
T11	34408	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	650138870	0	0
T1	1344	1247	0	0
T2	159053	137566	0	0
T3	2355564	1387481	0	0
T4	115252	92757	0	0
T5	255958	230429	0	0
T6	617017	512047	0	0
T7	1917590	1199221	0	0
T8	346285	326624	0	0
T9	243927	197004	0	0
T10	991	937	0	0
T11	34408	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	7	0	955
T14	586905	1	0	1
T29	0	1	0	0
T31	107643	0	0	1
T36	56179	0	0	1
T37	179698	0	0	1
T38	630790	0	0	1
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	1031	0	0	1
T45	118222	0	0	1
T46	1897	0	0	1
T47	17215	0	0	1
T48	40758	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	650138870	0	0
T1	1344	1247	0	0
T2	159053	137566	0	0
T3	2355564	1387481	0	0
T4	115252	92757	0	0
T5	255958	230429	0	0
T6	617017	512047	0	0
T7	1917590	1199221	0	0
T8	346285	326624	0	0
T9	243927	197004	0	0
T10	991	937	0	0
T11	34408	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805643814	3963977	0	0
T2	116237	832	0	0
T3	2355564	30397	0	0
T4	115252	832	0	0
T5	255958	832	0	0
T6	617017	0	0	0
T7	1917590	22328	0	0
T8	346285	19806	0	0
T9	243927	832	0	0
T10	991	0	0	0
T11	123468	832	0	0
T12	0	11833	0	0
T14	0	11228	0	0
T23	7330	372	0	0
T24	163600	0	0	0
T25	0	11705	0	0
T26	0	1243	0	0
T27	0	5056	0	0
T28	0	3849	0	0
T31	0	4247	0	0
T36	0	351	0	0
T37	0	240	0	0
T38	0	1812	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154001243	27584078	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	154001243	666787	0	0
GntImpliesValid_A	154001243	666787	0	0
GrantKnown_A	154001243	27584078	0	0
IdxKnown_A	154001243	27584078	0	0
IndexIsCorrect_A	154001243	666787	0	0
LockArbDecision_A	154001243	0	0	0
NoReadyValidNoGrant_A	154001243	0	0	0
ReadyAndValidImplyGrant_A	154001243	666787	0	0
ReqAndReadyImplyGrant_A	154001243	666787	0	0
ReqImpliesValid_A	154001243	666787	0	0
ReqStaysHighUntilGranted0_M	154001243	0	0	0
RoundRobin_A	154001243	0	0	0
ValidKnown_A	154001243	27584078	0	0
gen_data_port_assertion.DataFlow_A	154001243	666787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	27584078	0	0
T1	72	72	0	0
T2	21408	0	0	0
T3	953062	258664	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	96120	0	0
T7	711471	110616	0	0
T8	114523	105984	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T23	0	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	27584078	0	0
T1	72	72	0	0
T2	21408	0	0	0
T3	953062	258664	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	96120	0	0
T7	711471	110616	0	0
T8	114523	105984	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T23	0	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	27584078	0	0
T1	72	72	0	0
T2	21408	0	0	0
T3	953062	258664	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	96120	0	0
T7	711471	110616	0	0
T8	114523	105984	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T23	0	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	27584078	0	0
T1	72	72	0	0
T2	21408	0	0	0
T3	953062	258664	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	96120	0	0
T7	711471	110616	0	0
T8	114523	105984	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T23	0	3208	0	0
T24	0	77296	0	0
T25	0	169552	0	0
T26	0	31000	0	0
T27	0	46960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	666787	0	0
T3	953062	9700	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	5033	0	0
T8	114523	2372	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T14	0	8832	0	0
T23	3665	285	0	0
T24	81800	0	0	0
T25	0	4109	0	0
T26	0	1243	0	0
T27	0	2156	0	0
T28	0	3849	0	0
T36	0	351	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154001243	124999840	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	154001243	919703	0	0
GntImpliesValid_A	154001243	919703	0	0
GrantKnown_A	154001243	124999840	0	0
IdxKnown_A	154001243	124999840	0	0
IndexIsCorrect_A	154001243	919703	0	0
LockArbDecision_A	154001243	0	0	0
NoReadyValidNoGrant_A	154001243	0	0	0
ReadyAndValidImplyGrant_A	154001243	919703	0	0
ReqAndReadyImplyGrant_A	154001243	919703	0	0
ReqImpliesValid_A	154001243	919703	0	0
ReqStaysHighUntilGranted0_M	154001243	0	0	0
RoundRobin_A	154001243	0	0	0
ValidKnown_A	154001243	124999840	0	0
gen_data_port_assertion.DataFlow_A	154001243	919703	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	124999840	0	0
T2	21408	21408	0	0
T3	953062	679402	0	0
T4	22395	22395	0	0
T5	25280	25102	0	0
T6	100498	0	0	0
T7	711471	593966	0	0
T8	114523	103411	0	0
T9	46832	46832	0	0
T11	17204	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	124999840	0	0
T2	21408	21408	0	0
T3	953062	679402	0	0
T4	22395	22395	0	0
T5	25280	25102	0	0
T6	100498	0	0	0
T7	711471	593966	0	0
T8	114523	103411	0	0
T9	46832	46832	0	0
T11	17204	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	124999840	0	0
T2	21408	21408	0	0
T3	953062	679402	0	0
T4	22395	22395	0	0
T5	25280	25102	0	0
T6	100498	0	0	0
T7	711471	593966	0	0
T8	114523	103411	0	0
T9	46832	46832	0	0
T11	17204	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	124999840	0	0
T2	21408	21408	0	0
T3	953062	679402	0	0
T4	22395	22395	0	0
T5	25280	25102	0	0
T6	100498	0	0	0
T7	711471	593966	0	0
T8	114523	103411	0	0
T9	46832	46832	0	0
T11	17204	17204	0	0
T12	0	500368	0	0
T13	0	5254	0	0
T23	3665	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154001243	919703	0	0
T3	953062	5668	0	0
T4	22395	0	0	0
T5	25280	0	0	0
T6	100498	0	0	0
T7	711471	6457	0	0
T8	114523	5138	0	0
T9	46832	0	0	0
T11	17204	0	0	0
T12	0	799	0	0
T14	0	2396	0	0
T23	3665	0	0	0
T24	81800	0	0	0
T25	0	7596	0	0
T27	0	2900	0	0
T31	0	4247	0	0
T37	0	240	0	0
T38	0	1812	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	497641328	497554952	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	497641328	2377487	0	0
GntImpliesValid_A	497641328	2377487	0	0
GrantKnown_A	497641328	497554952	0	0
IdxKnown_A	497641328	497554952	0	0
IndexIsCorrect_A	497641328	2377487	0	0
LockArbDecision_A	497641328	0	0	0
NoReadyValidNoGrant_A	497641328	0	0	0
ReadyAndValidImplyGrant_A	497641328	2377487	0	0
ReqAndReadyImplyGrant_A	497641328	2377487	0	0
ReqImpliesValid_A	497641328	2377487	0	0
ReqStaysHighUntilGranted0_M	497641328	0	0	0
RoundRobin_A	497641328	7	0	955
ValidKnown_A	497641328	497554952	0	0
gen_data_port_assertion.DataFlow_A	497641328	2377487	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	497554952	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	497554952	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	497554952	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	7	0	955
T14	586905	1	0	1
T29	0	1	0	0
T31	107643	0	0	1
T36	56179	0	0	1
T37	179698	0	0	1
T38	630790	0	0	1
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	1031	0	0	1
T45	118222	0	0	1
T46	1897	0	0	1
T47	17215	0	0	1
T48	40758	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	497554952	0	0
T1	1272	1175	0	0
T2	116237	116158	0	0
T3	449440	449415	0	0
T4	70462	70362	0	0
T5	205398	205327	0	0
T6	416021	415927	0	0
T7	494648	494639	0	0
T8	117239	117229	0	0
T9	150263	150172	0	0
T10	991	937	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	497641328	2377487	0	0
T2	116237	832	0	0
T3	449440	15029	0	0
T4	70462	832	0	0
T5	205398	832	0	0
T6	416021	0	0	0
T7	494648	10838	0	0
T8	117239	12296	0	0
T9	150263	832	0	0
T10	991	0	0	0
T11	89060	832	0	0
T12	0	11034	0	0
T23	0	87	0	0