Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3643746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4339987

1

T1

1155

T2

2332

T4

877

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4338654	1			T1	3125		T2	1284		T3	67
values[0x0]	1822299	1			T1	544		T2	828		T4	432
values[0x1]	1822780	1			T1	590		T2	831		T4	446

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2581287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5402446

1

T1

2124

T2

2451

T3

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	42535	1			T1	14		T4	2		T8	269
valid_sources[0x01]	29231	1			T1	19		T4	1		T8	46
valid_sources[0x02]	28210	1			T1	19		T2	7		T3	1
valid_sources[0x03]	39265	1			T1	18		T2	13		T3	1
valid_sources[0x04]	30394	1			T1	5		T2	1		T4	5
valid_sources[0x05]	29980	1			T1	14		T2	16		T3	1
valid_sources[0x06]	35963	1			T1	19		T2	1		T4	6
valid_sources[0x07]	29739	1			T1	15		T2	32		T4	4
valid_sources[0x08]	26974	1			T1	19		T2	2		T4	4
valid_sources[0x09]	34401	1			T1	5		T2	37		T4	5
valid_sources[0x0a]	28017	1			T1	10		T4	7		T8	49
valid_sources[0x0b]	29652	1			T1	33		T4	4		T8	42
valid_sources[0x0c]	30093	1			T1	34		T2	23		T4	4
valid_sources[0x0d]	26614	1			T1	19		T2	10		T3	1
valid_sources[0x0e]	25891	1			T1	37		T4	3		T8	116
valid_sources[0x0f]	29568	1			T1	23		T2	18		T4	1
valid_sources[0x10]	27559	1			T1	8		T2	11		T4	2
valid_sources[0x11]	29739	1			T1	46		T2	34		T4	5
valid_sources[0x12]	32998	1			T1	23		T2	2		T4	5
valid_sources[0x13]	30107	1			T1	33		T2	19		T4	4
valid_sources[0x14]	29630	1			T1	17		T2	39		T4	2
valid_sources[0x15]	34089	1			T1	4		T2	9		T3	1
valid_sources[0x16]	29991	1			T1	16		T2	15		T3	1
valid_sources[0x17]	35519	1			T1	24		T4	4		T8	279
valid_sources[0x18]	27922	1			T1	16		T2	24		T4	5
valid_sources[0x19]	32023	1			T1	21		T2	13		T4	2
valid_sources[0x1a]	35705	1			T1	3		T2	4		T4	7
valid_sources[0x1b]	29431	1			T1	14		T2	1		T3	1
valid_sources[0x1c]	32280	1			T1	5		T2	3		T3	1
valid_sources[0x1d]	28081	1			T1	9		T2	5		T3	1
valid_sources[0x1e]	38252	1			T1	6		T3	1		T4	3
valid_sources[0x1f]	33963	1			T1	7		T2	4		T4	1
valid_sources[0x20]	26607	1			T1	39		T2	16		T4	4
valid_sources[0x21]	26751	1			T1	15		T2	3		T4	7
valid_sources[0x22]	31273	1			T1	22		T3	2		T4	6
valid_sources[0x23]	28592	1			T1	18		T3	1		T4	4
valid_sources[0x24]	27768	1			T1	19		T2	22		T4	5
valid_sources[0x25]	32224	1			T1	12		T4	1		T8	10
valid_sources[0x26]	27384	1			T1	16		T2	45		T4	7
valid_sources[0x27]	28535	1			T1	6		T2	10		T4	2
valid_sources[0x28]	27958	1			T1	7		T2	11		T4	3
valid_sources[0x29]	25665	1			T1	15		T2	18		T4	3
valid_sources[0x2a]	27593	1			T1	10		T3	1		T4	2
valid_sources[0x2b]	59871	1			T1	8		T2	30		T4	2
valid_sources[0x2c]	28201	1			T1	2		T2	7		T4	2
valid_sources[0x2d]	38512	1			T1	11		T2	16		T3	1
valid_sources[0x2e]	34734	1			T1	10		T2	21		T4	4
valid_sources[0x2f]	32402	1			T1	17		T2	3		T3	1
valid_sources[0x30]	29011	1			T1	21		T2	25		T4	1
valid_sources[0x31]	25750	1			T1	17		T2	11		T4	3
valid_sources[0x32]	32490	1			T1	5		T2	1		T4	5
valid_sources[0x33]	29599	1			T1	28		T2	7		T4	3
valid_sources[0x34]	27329	1			T1	9		T2	11		T4	4
valid_sources[0x35]	29091	1			T1	35		T2	12		T3	1
valid_sources[0x36]	28878	1			T1	23		T2	20		T3	1
valid_sources[0x37]	29574	1			T1	13		T4	3		T8	135
valid_sources[0x38]	29484	1			T1	8		T3	1		T4	5
valid_sources[0x39]	53720	1			T1	13		T2	22		T4	2
valid_sources[0x3a]	32765	1			T1	10		T2	25		T4	3
valid_sources[0x3b]	30688	1			T1	7		T4	4		T8	35
valid_sources[0x3c]	29280	1			T1	15		T2	9		T8	98
valid_sources[0x3d]	36230	1			T1	16		T2	14		T3	2
valid_sources[0x3e]	27258	1			T1	27		T2	22		T4	2
valid_sources[0x3f]	26392	1			T1	4		T2	29		T4	4
valid_sources[0x40]	42249	1			T1	21		T2	10		T8	2544
valid_sources[0x41]	27841	1			T1	19		T2	17		T4	2
valid_sources[0x42]	29860	1			T1	11		T4	3		T8	122
valid_sources[0x43]	39902	1			T1	28		T2	17		T4	2
valid_sources[0x44]	27839	1			T1	28		T2	90		T4	7
valid_sources[0x45]	29877	1			T1	16		T2	1		T4	2
valid_sources[0x46]	28890	1			T1	20		T2	22		T4	1
valid_sources[0x47]	28106	1			T1	30		T2	4		T3	2
valid_sources[0x48]	28119	1			T1	10		T4	6		T8	216
valid_sources[0x49]	28438	1			T1	15		T2	8		T3	1
valid_sources[0x4a]	27832	1			T1	21		T2	1		T4	4
valid_sources[0x4b]	27141	1			T1	10		T2	8		T3	1
valid_sources[0x4c]	32126	1			T1	36		T2	1		T4	4
valid_sources[0x4d]	32952	1			T1	20		T2	30		T4	5
valid_sources[0x4e]	36915	1			T1	23		T2	7		T4	4
valid_sources[0x4f]	27265	1			T1	21		T2	2		T4	2
valid_sources[0x50]	31804	1			T1	9		T2	4		T4	1
valid_sources[0x51]	29964	1			T1	8		T2	15		T4	2
valid_sources[0x52]	30426	1			T1	2		T2	8		T4	4
valid_sources[0x53]	29447	1			T1	13		T2	21		T4	5
valid_sources[0x54]	32006	1			T1	13		T2	8		T4	6
valid_sources[0x55]	32074	1			T1	5		T4	3		T8	459
valid_sources[0x56]	29132	1			T1	41		T2	7		T3	1
valid_sources[0x57]	27947	1			T1	13		T2	31		T4	2
valid_sources[0x58]	31114	1			T1	23		T2	10		T3	1
valid_sources[0x59]	28541	1			T1	9		T2	21		T4	2
valid_sources[0x5a]	27838	1			T1	15		T2	20		T4	3
valid_sources[0x5b]	27661	1			T1	4		T4	3		T8	116
valid_sources[0x5c]	28331	1			T1	15		T2	12		T3	1
valid_sources[0x5d]	30766	1			T1	20		T4	5		T8	66
valid_sources[0x5e]	27267	1			T1	14		T4	8		T6	1
valid_sources[0x5f]	31758	1			T1	13		T2	4		T4	6
valid_sources[0x60]	28754	1			T1	6		T2	5		T3	1
valid_sources[0x61]	28099	1			T1	10		T2	15		T3	1
valid_sources[0x62]	33558	1			T1	17		T2	5		T4	1
valid_sources[0x63]	33002	1			T1	20		T2	6		T4	4
valid_sources[0x64]	32005	1			T1	12		T4	3		T8	255
valid_sources[0x65]	26313	1			T1	14		T2	19		T4	4
valid_sources[0x66]	48910	1			T1	14		T2	12		T4	5
valid_sources[0x67]	30503	1			T1	19		T2	23		T4	2
valid_sources[0x68]	29968	1			T1	13		T2	3		T4	3
valid_sources[0x69]	42841	1			T1	17		T2	30		T4	1
valid_sources[0x6a]	33966	1			T1	15		T2	9		T4	1
valid_sources[0x6b]	68947	1			T1	12		T4	2		T8	46
valid_sources[0x6c]	30287	1			T1	3		T2	2		T8	43
valid_sources[0x6d]	30763	1			T1	6		T2	19		T3	1
valid_sources[0x6e]	31041	1			T1	7		T2	37		T4	2
valid_sources[0x6f]	26437	1			T1	6		T4	4		T8	2
valid_sources[0x70]	26027	1			T1	22		T2	2		T4	5
valid_sources[0x71]	35527	1			T1	23		T2	12		T3	1
valid_sources[0x72]	29124	1			T1	27		T2	11		T4	4
valid_sources[0x73]	28497	1			T1	31		T4	5		T8	121
valid_sources[0x74]	33037	1			T1	23		T2	13		T4	7
valid_sources[0x75]	27695	1			T1	6		T2	11		T8	181
valid_sources[0x76]	28859	1			T1	22		T2	15		T3	1
valid_sources[0x77]	29136	1			T1	18		T4	1		T8	3
valid_sources[0x78]	26145	1			T1	13		T2	8		T4	2
valid_sources[0x79]	30033	1			T1	32		T2	1		T4	2
valid_sources[0x7a]	27812	1			T1	18		T2	12		T4	3
valid_sources[0x7b]	27496	1			T1	17		T2	12		T3	1
valid_sources[0x7c]	30741	1			T1	13		T2	28		T4	4
valid_sources[0x7d]	31925	1			T1	36		T2	9		T4	3
valid_sources[0x7e]	29418	1			T1	17		T2	21		T4	7
valid_sources[0x7f]	29225	1			T1	10		T2	6		T4	6
valid_sources[0x80]	30721	1			T1	19		T2	9		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1028464

1

T1

299

T2

682

T4

2

values[0x0]

all_enables

biggest_size

1668239

1

T1

432

T2

823

T4

431

values[0x1]

all_enables

biggest_size

1643284

1

T1

424

T2

827

T4

444