Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3665126

1

T1

3104

T2

611

T3

67

full_word

4341221

1

T1

1155

T2

2332

T4

877

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8005857	1			T1	4259		T2	2943		T3	67
auto[TlIntgErrCmd]	154	1			T70	3		T102	11		T104	11
auto[TlIntgErrData]	168	1			T70	4		T102	11		T104	9
auto[TlIntgErrBoth]	168	1			T70	3		T102	8		T104	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4341712

1

T1

3125

T2

1284

T3

67

auto[1]

3664635

1

T1

1134

T2

1659

T4

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3312793	1			T1	2826		T2	602		T3	67
auto[TlIntgErrNone]	partial	auto[1]	351885	1			T1	278		T2	9		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	1028701	1			T1	299		T2	682		T4	2
auto[TlIntgErrNone]	full_word	auto[1]	3312478	1			T1	856		T2	1650		T4	875
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T102	7		T104	5		T166	5
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T70	2		T102	3		T104	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T70	1		T102	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T168	1		T169	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	76	1			T70	1		T102	4		T104	4
auto[TlIntgErrData]	partial	auto[1]	81	1			T70	3		T102	7		T104	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T104	1		T171	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T104	1		T171	3		T168	1
auto[TlIntgErrBoth]	partial	auto[0]	64	1			T70	3		T102	1		T104	4
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T102	5		T104	5		T166	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T102	1		T104	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T102	1		T166	2		T167	1