Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	639956843	3528715	0	0
gen_wmask[1].MaskCheckPortA_A	639956843	3528715	0	0
gen_wmask[2].MaskCheckPortA_A	639956843	3528715	0	0
gen_wmask[3].MaskCheckPortA_A	639956843	3528715	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639956843	3528715	0	0
T1	266206	1391	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	11139	836	0	0
T8	847634	14093	0	0
T9	1323	0	0	0
T10	1464	5	0	0
T13	57136	832	0	0
T14	96186	0	0	0
T15	0	12208	0	0
T17	0	12712	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639956843	3528715	0	0
T1	266206	1391	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	11139	836	0	0
T8	847634	14093	0	0
T9	1323	0	0	0
T10	1464	5	0	0
T13	57136	832	0	0
T14	96186	0	0	0
T15	0	12208	0	0
T17	0	12712	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639956843	3528715	0	0
T1	266206	1391	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	11139	836	0	0
T8	847634	14093	0	0
T9	1323	0	0	0
T10	1464	5	0	0
T13	57136	832	0	0
T14	96186	0	0	0
T15	0	12208	0	0
T17	0	12712	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	639956843	3528715	0	0
T1	266206	1391	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	11139	836	0	0
T8	847634	14093	0	0
T9	1323	0	0	0
T10	1464	5	0	0
T13	57136	832	0	0
T14	96186	0	0	0
T15	0	12208	0	0
T17	0	12712	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	486287355	2177257	0	0
gen_wmask[1].MaskCheckPortA_A	486287355	2177257	0	0
gen_wmask[2].MaskCheckPortA_A	486287355	2177257	0	0
gen_wmask[3].MaskCheckPortA_A	486287355	2177257	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2177257	0	0
T1	232582	482	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	832	0	0
T8	379277	8584	0	0
T9	1323	0	0	0
T10	1256	1	0	0
T13	0	832	0	0
T15	0	832	0	0
T17	0	9152	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2177257	0	0
T1	232582	482	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	832	0	0
T8	379277	8584	0	0
T9	1323	0	0	0
T10	1256	1	0	0
T13	0	832	0	0
T15	0	832	0	0
T17	0	9152	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2177257	0	0
T1	232582	482	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	832	0	0
T8	379277	8584	0	0
T9	1323	0	0	0
T10	1256	1	0	0
T13	0	832	0	0
T15	0	832	0	0
T17	0	9152	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2177257	0	0
T1	232582	482	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	832	0	0
T8	379277	8584	0	0
T9	1323	0	0	0
T10	1256	1	0	0
T13	0	832	0	0
T15	0	832	0	0
T17	0	9152	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	153669488	1351458	0	0
gen_wmask[1].MaskCheckPortA_A	153669488	1351458	0	0
gen_wmask[2].MaskCheckPortA_A	153669488	1351458	0	0
gen_wmask[3].MaskCheckPortA_A	153669488	1351458	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	1351458	0	0
T1	33624	909	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	4	0	0
T8	468357	5509	0	0
T10	208	4	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	0	11376	0	0
T17	0	3560	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	1351458	0	0
T1	33624	909	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	4	0	0
T8	468357	5509	0	0
T10	208	4	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	0	11376	0	0
T17	0	3560	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	1351458	0	0
T1	33624	909	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	4	0	0
T8	468357	5509	0	0
T10	208	4	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	0	11376	0	0
T17	0	3560	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	1351458	0	0
T1	33624	909	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	4	0	0
T8	468357	5509	0	0
T10	208	4	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	0	11376	0	0
T17	0	3560	0	0
T18	0	1059	0	0
T21	0	10299	0	0
T26	0	85	0	0
T36	0	278	0	0