Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.80	100.00	86.11		100.00	97.87	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1458862065	2913	0	0
SrcPulseCheck_M	461008464	2913	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1458862065	2913	0	0
T2	62542	6	0	0
T3	3158	0	0	0
T4	174416	0	0	0
T5	10044	0	0	0
T6	5746	0	0	0
T7	30756	2	0	0
T8	1137831	7	0	0
T9	3969	0	0	0
T10	3768	0	0	0
T11	5331	0	0	0
T12	1953	0	0	0
T13	60011	0	0	0
T14	151304	0	0	0
T15	80056	4	0	0
T16	6716	0	0	0
T17	0	14	0	0
T18	0	4	0	0
T19	0	5	0	0
T21	0	9	0	0
T36	0	6	0	0
T37	0	14	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	7	0	0
T42	0	7	0	0
T43	0	7	0	0
T46	0	9	0	0
T135	0	2	0	0
T150	0	7	0	0
T151	0	7	0	0
T152	0	7	0	0
T153	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	461008464	2913	0	0
T2	40910	6	0	0
T4	55968	0	0	0
T5	4112	0	0	0
T6	1440	0	0	0
T7	2661	2	0	0
T8	1405071	7	0	0
T10	624	0	0	0
T13	171408	0	0	0
T14	288558	0	0	0
T15	403542	4	0	0
T17	423394	14	0	0
T18	276298	4	0	0
T19	0	5	0	0
T21	0	9	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	6	0	0
T37	0	14	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	7	0	0
T42	0	7	0	0
T43	0	7	0	0
T46	0	9	0	0
T135	0	2	0	0
T150	0	7	0	0
T151	0	7	0	0
T152	0	7	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T40,T41
1	0	Covered	T2,T40,T41
1	1	Covered	T2,T40,T41

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T40,T41
1	0	Covered	T2,T40,T41
1	1	Covered	T2,T40,T41

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486287355	165	0	0
SrcPulseCheck_M	153669488	165	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	165	0	0
T2	31271	3	0	0
T3	1579	0	0	0
T4	87208	0	0	0
T5	5022	0	0	0
T6	2873	0	0	0
T7	10252	0	0	0
T8	379277	0	0	0
T9	1323	0	0	0
T10	1256	0	0	0
T11	1777	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T135	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	165	0	0
T2	20455	3	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	0	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T135	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T19,T39
1	0	Covered	T2,T19,T39
1	1	Covered	T2,T19,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T19,T39
1	0	Covered	T2,T19,T39
1	1	Covered	T2,T19,T39

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486287355	324	0	0
SrcPulseCheck_M	153669488	324	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	324	0	0
T2	31271	3	0	0
T3	1579	0	0	0
T4	87208	0	0	0
T5	5022	0	0	0
T6	2873	0	0	0
T7	10252	0	0	0
T8	379277	0	0	0
T9	1323	0	0	0
T10	1256	0	0	0
T11	1777	0	0	0
T19	0	5	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	5	0	0
T43	0	5	0	0
T150	0	5	0	0
T151	0	5	0	0
T152	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	324	0	0
T2	20455	3	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	0	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	0	0	0
T19	0	5	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	5	0	0
T42	0	5	0	0
T43	0	5	0	0
T150	0	5	0	0
T151	0	5	0	0
T152	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T7,T8,T15
1	0	Covered	T7,T8,T15
1	1	Covered	T7,T8,T15

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T15
1	0	Covered	T7,T8,T15
1	1	Covered	T7,T8,T15

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	486287355	2424	0	0
SrcPulseCheck_M	153669488	2424	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2424	0	0
T7	10252	2	0	0
T8	379277	7	0	0
T9	1323	0	0	0
T10	1256	0	0	0
T11	1777	0	0	0
T12	1953	0	0	0
T13	60011	0	0	0
T14	151304	0	0	0
T15	80056	4	0	0
T16	6716	0	0	0
T17	0	14	0	0
T18	0	4	0	0
T21	0	9	0	0
T36	0	6	0	0
T37	0	14	0	0
T46	0	9	0	0
T52	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	2424	0	0
T7	887	2	0	0
T8	468357	7	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	4	0	0
T17	423394	14	0	0
T18	276298	4	0	0
T21	0	9	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	6	0	0
T37	0	14	0	0
T46	0	9	0	0
T52	0	20	0	0