Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	3021445	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	3021445	0	0
T2	31271	2365	0	0
T3	1579	0	0	0
T4	87208	1663	0	0
T5	5022	1663	0	0
T6	2873	0	0	0
T7	10252	1663	0	0
T8	379277	12491	0	0
T9	1323	0	0	0
T10	1256	0	0	0
T11	1777	0	0	0
T13	0	832	0	0
T15	0	1663	0	0
T17	0	15800	0	0
T18	0	4990	0	0
T25	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	3235960	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	3235960	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	832	0	0
T8	379277	22715	0	0
T9	1323	0	0	0
T10	1256	0	0	0
T11	1777	0	0	0
T13	0	832	0	0
T15	0	832	0	0
T17	0	9152	0	0
T18	0	3328	0	0
T25	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	189085	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	189085	0	0
T1	232582	236	0	0
T2	31271	0	0	0
T3	1579	0	0	0
T4	87208	0	0	0
T5	5022	0	0	0
T6	2873	0	0	0
T7	10252	0	0	0
T8	379277	480	0	0
T9	1323	0	0	0
T10	1256	1	0	0
T15	0	256	0	0
T17	0	354	0	0
T18	0	267	0	0
T21	0	1376	0	0
T26	0	23	0	0
T36	0	65	0	0
T37	0	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	432241	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	432241	0	0
T1	232582	732	0	0
T2	31271	0	0	0
T3	1579	0	0	0
T4	87208	0	0	0
T5	5022	0	0	0
T6	2873	0	0	0
T7	10252	0	0	0
T8	379277	2144	0	0
T9	1323	0	0	0
T10	1256	5	0	0
T15	0	1149	0	0
T17	0	354	0	0
T18	0	267	0	0
T21	0	1375	0	0
T26	0	23	0	0
T36	0	282	0	0
T37	0	478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	6281431	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	6281431	0	0
T1	232582	4151	0	0
T2	31271	1344	0	0
T3	1579	67	0	0
T4	87208	49	0	0
T5	5022	48	0	0
T6	2873	32	0	0
T7	10252	80	0	0
T8	379277	31205	0	0
T9	1323	33	0	0
T10	1256	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	488727432	12499081	0	0
DepthKnown_A	488727432	488587277	0	0
RvalidKnown_A	488727432	488587277	0	0
WreadyKnown_A	488727432	488587277	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	12499081	0	0
T1	232582	12500	0	0
T2	31271	1343	0	0
T3	1579	67	0	0
T4	87208	49	0	0
T5	5022	123	0	0
T6	2873	32	0	0
T7	10252	80	0	0
T8	379277	127216	0	0
T9	1323	33	0	0
T10	1256	123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488727432	488587277	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0