Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T15
1	0	Covered	T7,T8,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	793626331	638496129	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	793626331	3916408	0	0
GntImpliesValid_A	793626331	3916408	0	0
GrantKnown_A	793626331	638496129	0	0
IdxKnown_A	793626331	638496129	0	0
IndexIsCorrect_A	793626331	3916408	0	0
LockArbDecision_A	793626331	0	0	0
NoReadyValidNoGrant_A	793626331	0	0	0
ReadyAndValidImplyGrant_A	793626331	3916408	0	0
ReqAndReadyImplyGrant_A	793626331	3916408	0	0
ReqImpliesValid_A	793626331	3916408	0	0
ReqStaysHighUntilGranted0_M	793626331	0	0	0
RoundRobin_A	793626331	4	0	956
ValidKnown_A	793626331	638496129	0	0
gen_data_port_assertion.DataFlow_A	793626331	3916408	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	638496129	0	0
T1	266206	264562	0	0
T2	72181	51314	0	0
T3	1579	1522	0	0
T4	143176	115127	0	0
T5	9134	6996	0	0
T6	4313	3529	0	0
T7	12026	10817	0	0
T8	1315991	843639	0	0
T9	1323	1249	0	0
T10	1672	1376	0	0
T13	114272	57136	0	0
T14	192372	90624	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	274280	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T25	0	2080	0	0
T26	0	1408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	638496129	0	0
T1	266206	264562	0	0
T2	72181	51314	0	0
T3	1579	1522	0	0
T4	143176	115127	0	0
T5	9134	6996	0	0
T6	4313	3529	0	0
T7	12026	10817	0	0
T8	1315991	843639	0	0
T9	1323	1249	0	0
T10	1672	1376	0	0
T13	114272	57136	0	0
T14	192372	90624	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	274280	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T25	0	2080	0	0
T26	0	1408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	638496129	0	0
T1	266206	264562	0	0
T2	72181	51314	0	0
T3	1579	1522	0	0
T4	143176	115127	0	0
T5	9134	6996	0	0
T6	4313	3529	0	0
T7	12026	10817	0	0
T8	1315991	843639	0	0
T9	1323	1249	0	0
T10	1672	1376	0	0
T13	114272	57136	0	0
T14	192372	90624	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	274280	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T25	0	2080	0	0
T26	0	1408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	4	0	956
T53	110695	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	209165	0	0	1
T58	1328	0	0	1
T59	1951	0	0	1
T60	66014	0	0	1
T61	809480	0	0	1
T62	24009	0	0	1
T63	1353	0	0	1
T64	752	0	0	1
T65	763798	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	638496129	0	0
T1	266206	264562	0	0
T2	72181	51314	0	0
T3	1579	1522	0	0
T4	143176	115127	0	0
T5	9134	6996	0	0
T6	4313	3529	0	0
T7	12026	10817	0	0
T8	1315991	843639	0	0
T9	1323	1249	0	0
T10	1672	1376	0	0
T13	114272	57136	0	0
T14	192372	90624	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	274280	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T25	0	2080	0	0
T26	0	1408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793626331	3916408	0	0
T1	266206	2159	0	0
T2	51726	1600	0	0
T3	1579	0	0	0
T4	115192	832	0	0
T5	7078	832	0	0
T6	3593	0	0	0
T7	12026	840	0	0
T8	1315991	14871	0	0
T9	1323	0	0	0
T10	1672	8	0	0
T13	114272	832	0	0
T14	192372	0	0	0
T15	134514	12472	0	0
T17	423394	13091	0	0
T18	276298	1362	0	0
T21	0	12308	0	0
T22	0	5337	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T26	0	100	0	0
T27	0	1177	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T50	0	1272	0	0
T51	0	3077	0	0
T52	0	3251	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153669488	26839640	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153669488	615056	0	0
GntImpliesValid_A	153669488	615056	0	0
GrantKnown_A	153669488	26839640	0	0
IdxKnown_A	153669488	26839640	0	0
IndexIsCorrect_A	153669488	615056	0	0
LockArbDecision_A	153669488	0	0	0
NoReadyValidNoGrant_A	153669488	0	0	0
ReadyAndValidImplyGrant_A	153669488	615056	0	0
ReqAndReadyImplyGrant_A	153669488	615056	0	0
ReqImpliesValid_A	153669488	615056	0	0
ReqStaysHighUntilGranted0_M	153669488	0	0	0
RoundRobin_A	153669488	0	0	0
ValidKnown_A	153669488	26839640	0	0
gen_data_port_assertion.DataFlow_A	153669488	615056	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	26839640	0	0
T1	33624	32080	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	720	0	0
T7	887	0	0	0
T8	468357	19968	0	0
T10	208	208	0	0
T13	57136	0	0	0
T14	96186	90624	0	0
T18	0	36440	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T26	0	1408	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	26839640	0	0
T1	33624	32080	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	720	0	0
T7	887	0	0	0
T8	468357	19968	0	0
T10	208	208	0	0
T13	57136	0	0	0
T14	96186	90624	0	0
T18	0	36440	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T26	0	1408	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	26839640	0	0
T1	33624	32080	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	720	0	0
T7	887	0	0	0
T8	468357	19968	0	0
T10	208	208	0	0
T13	57136	0	0	0
T14	96186	90624	0	0
T18	0	36440	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T26	0	1408	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	26839640	0	0
T1	33624	32080	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	720	0	0
T7	887	0	0	0
T8	468357	19968	0	0
T10	208	208	0	0
T13	57136	0	0	0
T14	96186	90624	0	0
T18	0	36440	0	0
T21	0	146968	0	0
T23	0	107584	0	0
T24	0	33344	0	0
T26	0	1408	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	615056	0	0
T1	33624	1441	0	0
T2	20455	0	0	0
T4	27984	0	0	0
T5	2056	0	0	0
T6	720	0	0	0
T7	887	0	0	0
T8	468357	770	0	0
T10	208	6	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T18	0	837	0	0
T21	0	6444	0	0
T22	0	5337	0	0
T26	0	100	0	0
T27	0	1177	0	0
T50	0	1272	0	0
T51	0	3077	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T15
1	0	Covered	T7,T8,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T15
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153669488	125457286	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153669488	942450	0	0
GntImpliesValid_A	153669488	942450	0	0
GrantKnown_A	153669488	125457286	0	0
IdxKnown_A	153669488	125457286	0	0
IndexIsCorrect_A	153669488	942450	0	0
LockArbDecision_A	153669488	0	0	0
NoReadyValidNoGrant_A	153669488	0	0	0
ReadyAndValidImplyGrant_A	153669488	942450	0	0
ReqAndReadyImplyGrant_A	153669488	942450	0	0
ReqImpliesValid_A	153669488	942450	0	0
ReqStaysHighUntilGranted0_M	153669488	0	0	0
RoundRobin_A	153669488	0	0	0
ValidKnown_A	153669488	125457286	0	0
gen_data_port_assertion.DataFlow_A	153669488	942450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	125457286	0	0
T2	20455	20094	0	0
T4	27984	27984	0	0
T5	2056	2056	0	0
T6	720	0	0	0
T7	887	640	0	0
T8	468357	444414	0	0
T10	208	0	0	0
T13	57136	57136	0	0
T14	96186	0	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	237840	0	0
T25	0	2080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	125457286	0	0
T2	20455	20094	0	0
T4	27984	27984	0	0
T5	2056	2056	0	0
T6	720	0	0	0
T7	887	640	0	0
T8	468357	444414	0	0
T10	208	0	0	0
T13	57136	57136	0	0
T14	96186	0	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	237840	0	0
T25	0	2080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	125457286	0	0
T2	20455	20094	0	0
T4	27984	27984	0	0
T5	2056	2056	0	0
T6	720	0	0	0
T7	887	640	0	0
T8	468357	444414	0	0
T10	208	0	0	0
T13	57136	57136	0	0
T14	96186	0	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	237840	0	0
T25	0	2080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	125457286	0	0
T2	20455	20094	0	0
T4	27984	27984	0	0
T5	2056	2056	0	0
T6	720	0	0	0
T7	887	640	0	0
T8	468357	444414	0	0
T10	208	0	0	0
T13	57136	57136	0	0
T14	96186	0	0	0
T15	134514	134192	0	0
T17	0	421475	0	0
T18	0	237840	0	0
T25	0	2080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153669488	942450	0	0
T7	887	4	0	0
T8	468357	5023	0	0
T10	208	0	0	0
T13	57136	0	0	0
T14	96186	0	0	0
T15	134514	11376	0	0
T17	423394	3560	0	0
T18	276298	525	0	0
T21	0	5864	0	0
T23	112868	0	0	0
T24	33911	0	0	0
T36	0	278	0	0
T37	0	8529	0	0
T46	0	7119	0	0
T52	0	3251	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	486287355	486199203	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	486287355	2358902	0	0
GntImpliesValid_A	486287355	2358902	0	0
GrantKnown_A	486287355	486199203	0	0
IdxKnown_A	486287355	486199203	0	0
IndexIsCorrect_A	486287355	2358902	0	0
LockArbDecision_A	486287355	0	0	0
NoReadyValidNoGrant_A	486287355	0	0	0
ReadyAndValidImplyGrant_A	486287355	2358902	0	0
ReqAndReadyImplyGrant_A	486287355	2358902	0	0
ReqImpliesValid_A	486287355	2358902	0	0
ReqStaysHighUntilGranted0_M	486287355	0	0	0
RoundRobin_A	486287355	4	0	956
ValidKnown_A	486287355	486199203	0	0
gen_data_port_assertion.DataFlow_A	486287355	2358902	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	486199203	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	486199203	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	486199203	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	4	0	956
T53	110695	1	0	1
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	209165	0	0	1
T58	1328	0	0	1
T59	1951	0	0	1
T60	66014	0	0	1
T61	809480	0	0	1
T62	24009	0	0	1
T63	1353	0	0	1
T64	752	0	0	1
T65	763798	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	486199203	0	0
T1	232582	232482	0	0
T2	31271	31220	0	0
T3	1579	1522	0	0
T4	87208	87143	0	0
T5	5022	4940	0	0
T6	2873	2809	0	0
T7	10252	10177	0	0
T8	379277	379257	0	0
T9	1323	1249	0	0
T10	1256	1168	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287355	2358902	0	0
T1	232582	718	0	0
T2	31271	1600	0	0
T3	1579	0	0	0
T4	87208	832	0	0
T5	5022	832	0	0
T6	2873	0	0	0
T7	10252	836	0	0
T8	379277	9078	0	0
T9	1323	0	0	0
T10	1256	2	0	0
T13	0	832	0	0
T15	0	1096	0	0
T17	0	9531	0	0