Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
3654 | 
0 | 
0 | 
| T69 | 
6841 | 
241 | 
0 | 
0 | 
| T70 | 
10799 | 
1 | 
0 | 
0 | 
| T71 | 
17075 | 
233 | 
0 | 
0 | 
| T102 | 
99940 | 
7 | 
0 | 
0 | 
| T103 | 
15916 | 
9 | 
0 | 
0 | 
| T105 | 
2768 | 
82 | 
0 | 
0 | 
| T106 | 
12633 | 
161 | 
0 | 
0 | 
| T107 | 
2780 | 
103 | 
0 | 
0 | 
| T116 | 
4920 | 
9 | 
0 | 
0 | 
| T117 | 
4009 | 
6 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2063 | 
0 | 
0 | 
| T102 | 
99940 | 
106 | 
0 | 
0 | 
| T103 | 
15916 | 
26 | 
0 | 
0 | 
| T124 | 
114399 | 
759 | 
0 | 
0 | 
| T130 | 
4179 | 
7 | 
0 | 
0 | 
| T146 | 
13957 | 
28 | 
0 | 
0 | 
| T149 | 
7588 | 
60 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
40 | 
0 | 
0 | 
| T156 | 
7820 | 
13 | 
0 | 
0 | 
| T157 | 
20281 | 
60 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2132 | 
0 | 
0 | 
| T102 | 
99940 | 
149 | 
0 | 
0 | 
| T103 | 
15916 | 
19 | 
0 | 
0 | 
| T124 | 
114399 | 
759 | 
0 | 
0 | 
| T130 | 
4179 | 
6 | 
0 | 
0 | 
| T146 | 
13957 | 
38 | 
0 | 
0 | 
| T149 | 
7588 | 
11 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
62 | 
0 | 
0 | 
| T156 | 
7820 | 
22 | 
0 | 
0 | 
| T157 | 
20281 | 
83 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2809 | 
0 | 
0 | 
| T102 | 
99940 | 
249 | 
0 | 
0 | 
| T103 | 
15916 | 
32 | 
0 | 
0 | 
| T124 | 
114399 | 
824 | 
0 | 
0 | 
| T130 | 
4179 | 
22 | 
0 | 
0 | 
| T131 | 
10865 | 
18 | 
0 | 
0 | 
| T146 | 
13957 | 
46 | 
0 | 
0 | 
| T149 | 
7588 | 
31 | 
0 | 
0 | 
| T155 | 
13513 | 
57 | 
0 | 
0 | 
| T156 | 
7820 | 
39 | 
0 | 
0 | 
| T157 | 
20281 | 
54 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
11605 | 
0 | 
0 | 
| T102 | 
99940 | 
1744 | 
0 | 
0 | 
| T103 | 
15916 | 
223 | 
0 | 
0 | 
| T124 | 
114399 | 
777 | 
0 | 
0 | 
| T130 | 
4179 | 
125 | 
0 | 
0 | 
| T131 | 
10865 | 
127 | 
0 | 
0 | 
| T146 | 
13957 | 
50 | 
0 | 
0 | 
| T149 | 
7588 | 
20 | 
0 | 
0 | 
| T155 | 
13513 | 
48 | 
0 | 
0 | 
| T156 | 
7820 | 
27 | 
0 | 
0 | 
| T157 | 
20281 | 
57 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
11041 | 
0 | 
0 | 
| T102 | 
99940 | 
1624 | 
0 | 
0 | 
| T103 | 
15916 | 
267 | 
0 | 
0 | 
| T124 | 
114399 | 
801 | 
0 | 
0 | 
| T130 | 
4179 | 
5 | 
0 | 
0 | 
| T146 | 
13957 | 
84 | 
0 | 
0 | 
| T149 | 
7588 | 
39 | 
0 | 
0 | 
| T154 | 
4803 | 
128 | 
0 | 
0 | 
| T155 | 
13513 | 
44 | 
0 | 
0 | 
| T156 | 
7820 | 
19 | 
0 | 
0 | 
| T157 | 
20281 | 
40 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
10039 | 
0 | 
0 | 
| T102 | 
99940 | 
1768 | 
0 | 
0 | 
| T103 | 
15916 | 
19 | 
0 | 
0 | 
| T124 | 
114399 | 
801 | 
0 | 
0 | 
| T130 | 
4179 | 
84 | 
0 | 
0 | 
| T146 | 
13957 | 
42 | 
0 | 
0 | 
| T149 | 
7588 | 
45 | 
0 | 
0 | 
| T154 | 
4803 | 
100 | 
0 | 
0 | 
| T155 | 
13513 | 
58 | 
0 | 
0 | 
| T156 | 
7820 | 
34 | 
0 | 
0 | 
| T157 | 
20281 | 
46 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
11377 | 
0 | 
0 | 
| T102 | 
99940 | 
2345 | 
0 | 
0 | 
| T103 | 
15916 | 
282 | 
0 | 
0 | 
| T124 | 
114399 | 
792 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
39 | 
0 | 
0 | 
| T149 | 
7588 | 
1 | 
0 | 
0 | 
| T154 | 
4803 | 
142 | 
0 | 
0 | 
| T155 | 
13513 | 
42 | 
0 | 
0 | 
| T156 | 
7820 | 
3 | 
0 | 
0 | 
| T157 | 
20281 | 
47 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
12757 | 
0 | 
0 | 
| T102 | 
99940 | 
2653 | 
0 | 
0 | 
| T103 | 
15916 | 
243 | 
0 | 
0 | 
| T124 | 
114399 | 
798 | 
0 | 
0 | 
| T130 | 
4179 | 
122 | 
0 | 
0 | 
| T146 | 
13957 | 
23 | 
0 | 
0 | 
| T149 | 
7588 | 
17 | 
0 | 
0 | 
| T154 | 
4803 | 
110 | 
0 | 
0 | 
| T155 | 
13513 | 
63 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
69 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
10868 | 
0 | 
0 | 
| T102 | 
99940 | 
1675 | 
0 | 
0 | 
| T103 | 
15916 | 
147 | 
0 | 
0 | 
| T124 | 
114399 | 
828 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
64 | 
0 | 
0 | 
| T149 | 
7588 | 
10 | 
0 | 
0 | 
| T154 | 
4803 | 
122 | 
0 | 
0 | 
| T155 | 
13513 | 
68 | 
0 | 
0 | 
| T156 | 
7820 | 
21 | 
0 | 
0 | 
| T157 | 
20281 | 
44 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
12124 | 
0 | 
0 | 
| T102 | 
99940 | 
1482 | 
0 | 
0 | 
| T103 | 
15916 | 
201 | 
0 | 
0 | 
| T124 | 
114399 | 
849 | 
0 | 
0 | 
| T130 | 
4179 | 
100 | 
0 | 
0 | 
| T146 | 
13957 | 
60 | 
0 | 
0 | 
| T149 | 
7588 | 
8 | 
0 | 
0 | 
| T154 | 
4803 | 
130 | 
0 | 
0 | 
| T155 | 
13513 | 
40 | 
0 | 
0 | 
| T156 | 
7820 | 
5 | 
0 | 
0 | 
| T157 | 
20281 | 
31 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
11620 | 
0 | 
0 | 
| T102 | 
99940 | 
2136 | 
0 | 
0 | 
| T103 | 
15916 | 
268 | 
0 | 
0 | 
| T124 | 
114399 | 
841 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
57 | 
0 | 
0 | 
| T149 | 
7588 | 
6 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
36 | 
0 | 
0 | 
| T156 | 
7820 | 
22 | 
0 | 
0 | 
| T157 | 
20281 | 
61 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5497 | 
0 | 
0 | 
| T102 | 
99940 | 
733 | 
0 | 
0 | 
| T103 | 
15916 | 
77 | 
0 | 
0 | 
| T124 | 
114399 | 
778 | 
0 | 
0 | 
| T130 | 
4179 | 
51 | 
0 | 
0 | 
| T146 | 
13957 | 
58 | 
0 | 
0 | 
| T149 | 
7588 | 
7 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
16 | 
0 | 
0 | 
| T156 | 
7820 | 
14 | 
0 | 
0 | 
| T157 | 
20281 | 
61 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6085 | 
0 | 
0 | 
| T102 | 
99940 | 
1145 | 
0 | 
0 | 
| T103 | 
15916 | 
91 | 
0 | 
0 | 
| T124 | 
114399 | 
892 | 
0 | 
0 | 
| T130 | 
4179 | 
65 | 
0 | 
0 | 
| T146 | 
13957 | 
62 | 
0 | 
0 | 
| T149 | 
7588 | 
21 | 
0 | 
0 | 
| T154 | 
4803 | 
7 | 
0 | 
0 | 
| T155 | 
13513 | 
12 | 
0 | 
0 | 
| T156 | 
7820 | 
34 | 
0 | 
0 | 
| T157 | 
20281 | 
27 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6028 | 
0 | 
0 | 
| T102 | 
99940 | 
685 | 
0 | 
0 | 
| T103 | 
15916 | 
133 | 
0 | 
0 | 
| T124 | 
114399 | 
775 | 
0 | 
0 | 
| T130 | 
4179 | 
29 | 
0 | 
0 | 
| T146 | 
13957 | 
40 | 
0 | 
0 | 
| T149 | 
7588 | 
47 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
4 | 
0 | 
0 | 
| T156 | 
7820 | 
21 | 
0 | 
0 | 
| T157 | 
20281 | 
21 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5788 | 
0 | 
0 | 
| T102 | 
99940 | 
835 | 
0 | 
0 | 
| T103 | 
15916 | 
14 | 
0 | 
0 | 
| T124 | 
114399 | 
769 | 
0 | 
0 | 
| T130 | 
4179 | 
7 | 
0 | 
0 | 
| T131 | 
10865 | 
150 | 
0 | 
0 | 
| T146 | 
13957 | 
22 | 
0 | 
0 | 
| T149 | 
7588 | 
9 | 
0 | 
0 | 
| T155 | 
13513 | 
8 | 
0 | 
0 | 
| T156 | 
7820 | 
3 | 
0 | 
0 | 
| T157 | 
20281 | 
10 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5660 | 
0 | 
0 | 
| T102 | 
99940 | 
845 | 
0 | 
0 | 
| T103 | 
15916 | 
62 | 
0 | 
0 | 
| T124 | 
114399 | 
823 | 
0 | 
0 | 
| T130 | 
4179 | 
7 | 
0 | 
0 | 
| T146 | 
13957 | 
12 | 
0 | 
0 | 
| T149 | 
7588 | 
43 | 
0 | 
0 | 
| T154 | 
4803 | 
60 | 
0 | 
0 | 
| T155 | 
13513 | 
1 | 
0 | 
0 | 
| T156 | 
7820 | 
33 | 
0 | 
0 | 
| T157 | 
20281 | 
57 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5440 | 
0 | 
0 | 
| T102 | 
99940 | 
842 | 
0 | 
0 | 
| T103 | 
15916 | 
141 | 
0 | 
0 | 
| T124 | 
114399 | 
820 | 
0 | 
0 | 
| T130 | 
4179 | 
43 | 
0 | 
0 | 
| T146 | 
13957 | 
14 | 
0 | 
0 | 
| T149 | 
7588 | 
9 | 
0 | 
0 | 
| T154 | 
4803 | 
46 | 
0 | 
0 | 
| T155 | 
13513 | 
66 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
51 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5472 | 
0 | 
0 | 
| T102 | 
99940 | 
835 | 
0 | 
0 | 
| T103 | 
15916 | 
69 | 
0 | 
0 | 
| T124 | 
114399 | 
829 | 
0 | 
0 | 
| T130 | 
4179 | 
47 | 
0 | 
0 | 
| T146 | 
13957 | 
29 | 
0 | 
0 | 
| T149 | 
7588 | 
38 | 
0 | 
0 | 
| T154 | 
4803 | 
7 | 
0 | 
0 | 
| T155 | 
13513 | 
55 | 
0 | 
0 | 
| T156 | 
7820 | 
5 | 
0 | 
0 | 
| T157 | 
20281 | 
50 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6043 | 
0 | 
0 | 
| T102 | 
99940 | 
998 | 
0 | 
0 | 
| T103 | 
15916 | 
151 | 
0 | 
0 | 
| T124 | 
114399 | 
772 | 
0 | 
0 | 
| T130 | 
4179 | 
1 | 
0 | 
0 | 
| T146 | 
13957 | 
104 | 
0 | 
0 | 
| T149 | 
7588 | 
14 | 
0 | 
0 | 
| T154 | 
4803 | 
52 | 
0 | 
0 | 
| T155 | 
13513 | 
22 | 
0 | 
0 | 
| T156 | 
7820 | 
10 | 
0 | 
0 | 
| T157 | 
20281 | 
36 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6238 | 
0 | 
0 | 
| T102 | 
99940 | 
973 | 
0 | 
0 | 
| T103 | 
15916 | 
50 | 
0 | 
0 | 
| T124 | 
114399 | 
797 | 
0 | 
0 | 
| T130 | 
4179 | 
47 | 
0 | 
0 | 
| T131 | 
10865 | 
113 | 
0 | 
0 | 
| T146 | 
13957 | 
71 | 
0 | 
0 | 
| T149 | 
7588 | 
22 | 
0 | 
0 | 
| T155 | 
13513 | 
37 | 
0 | 
0 | 
| T156 | 
7820 | 
54 | 
0 | 
0 | 
| T157 | 
20281 | 
71 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5740 | 
0 | 
0 | 
| T102 | 
99940 | 
760 | 
0 | 
0 | 
| T103 | 
15916 | 
166 | 
0 | 
0 | 
| T124 | 
114399 | 
823 | 
0 | 
0 | 
| T130 | 
4179 | 
67 | 
0 | 
0 | 
| T146 | 
13957 | 
43 | 
0 | 
0 | 
| T149 | 
7588 | 
34 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
30 | 
0 | 
0 | 
| T156 | 
7820 | 
32 | 
0 | 
0 | 
| T157 | 
20281 | 
44 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5247 | 
0 | 
0 | 
| T102 | 
99940 | 
635 | 
0 | 
0 | 
| T103 | 
15916 | 
66 | 
0 | 
0 | 
| T124 | 
114399 | 
740 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
30 | 
0 | 
0 | 
| T149 | 
7588 | 
27 | 
0 | 
0 | 
| T154 | 
4803 | 
40 | 
0 | 
0 | 
| T155 | 
13513 | 
30 | 
0 | 
0 | 
| T156 | 
7820 | 
14 | 
0 | 
0 | 
| T157 | 
20281 | 
86 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5699 | 
0 | 
0 | 
| T102 | 
99940 | 
1036 | 
0 | 
0 | 
| T103 | 
15916 | 
24 | 
0 | 
0 | 
| T124 | 
114399 | 
780 | 
0 | 
0 | 
| T130 | 
4179 | 
9 | 
0 | 
0 | 
| T146 | 
13957 | 
59 | 
0 | 
0 | 
| T149 | 
7588 | 
23 | 
0 | 
0 | 
| T154 | 
4803 | 
6 | 
0 | 
0 | 
| T155 | 
13513 | 
35 | 
0 | 
0 | 
| T156 | 
7820 | 
46 | 
0 | 
0 | 
| T157 | 
20281 | 
101 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5256 | 
0 | 
0 | 
| T102 | 
99940 | 
564 | 
0 | 
0 | 
| T103 | 
15916 | 
70 | 
0 | 
0 | 
| T114 | 
18985 | 
3 | 
0 | 
0 | 
| T124 | 
114399 | 
791 | 
0 | 
0 | 
| T130 | 
4179 | 
46 | 
0 | 
0 | 
| T146 | 
13957 | 
41 | 
0 | 
0 | 
| T149 | 
7588 | 
46 | 
0 | 
0 | 
| T155 | 
13513 | 
46 | 
0 | 
0 | 
| T156 | 
7820 | 
38 | 
0 | 
0 | 
| T157 | 
20281 | 
68 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6250 | 
0 | 
0 | 
| T102 | 
99940 | 
901 | 
0 | 
0 | 
| T103 | 
15916 | 
127 | 
0 | 
0 | 
| T124 | 
114399 | 
721 | 
0 | 
0 | 
| T130 | 
4179 | 
53 | 
0 | 
0 | 
| T146 | 
13957 | 
9 | 
0 | 
0 | 
| T149 | 
7588 | 
9 | 
0 | 
0 | 
| T154 | 
4803 | 
35 | 
0 | 
0 | 
| T155 | 
13513 | 
21 | 
0 | 
0 | 
| T156 | 
7820 | 
13 | 
0 | 
0 | 
| T157 | 
20281 | 
72 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5907 | 
0 | 
0 | 
| T102 | 
99940 | 
692 | 
0 | 
0 | 
| T103 | 
15916 | 
91 | 
0 | 
0 | 
| T124 | 
114399 | 
804 | 
0 | 
0 | 
| T130 | 
4179 | 
3 | 
0 | 
0 | 
| T146 | 
13957 | 
45 | 
0 | 
0 | 
| T149 | 
7588 | 
16 | 
0 | 
0 | 
| T154 | 
4803 | 
43 | 
0 | 
0 | 
| T155 | 
13513 | 
26 | 
0 | 
0 | 
| T156 | 
7820 | 
47 | 
0 | 
0 | 
| T157 | 
20281 | 
37 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
6080 | 
0 | 
0 | 
| T102 | 
99940 | 
833 | 
0 | 
0 | 
| T103 | 
15916 | 
167 | 
0 | 
0 | 
| T124 | 
114399 | 
830 | 
0 | 
0 | 
| T130 | 
4179 | 
48 | 
0 | 
0 | 
| T146 | 
13957 | 
34 | 
0 | 
0 | 
| T149 | 
7588 | 
39 | 
0 | 
0 | 
| T154 | 
4803 | 
9 | 
0 | 
0 | 
| T155 | 
13513 | 
32 | 
0 | 
0 | 
| T156 | 
7820 | 
65 | 
0 | 
0 | 
| T157 | 
20281 | 
49 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5702 | 
0 | 
0 | 
| T102 | 
99940 | 
835 | 
0 | 
0 | 
| T103 | 
15916 | 
102 | 
0 | 
0 | 
| T124 | 
114399 | 
772 | 
0 | 
0 | 
| T131 | 
10865 | 
96 | 
0 | 
0 | 
| T146 | 
13957 | 
54 | 
0 | 
0 | 
| T149 | 
7588 | 
8 | 
0 | 
0 | 
| T154 | 
4803 | 
9 | 
0 | 
0 | 
| T155 | 
13513 | 
58 | 
0 | 
0 | 
| T156 | 
7820 | 
12 | 
0 | 
0 | 
| T157 | 
20281 | 
37 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5581 | 
0 | 
0 | 
| T102 | 
99940 | 
892 | 
0 | 
0 | 
| T103 | 
15916 | 
101 | 
0 | 
0 | 
| T124 | 
114399 | 
744 | 
0 | 
0 | 
| T130 | 
4179 | 
8 | 
0 | 
0 | 
| T146 | 
13957 | 
58 | 
0 | 
0 | 
| T149 | 
7588 | 
1 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
57 | 
0 | 
0 | 
| T156 | 
7820 | 
33 | 
0 | 
0 | 
| T157 | 
20281 | 
71 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5784 | 
0 | 
0 | 
| T102 | 
99940 | 
722 | 
0 | 
0 | 
| T103 | 
15916 | 
114 | 
0 | 
0 | 
| T124 | 
114399 | 
788 | 
0 | 
0 | 
| T130 | 
4179 | 
39 | 
0 | 
0 | 
| T146 | 
13957 | 
36 | 
0 | 
0 | 
| T149 | 
7588 | 
39 | 
0 | 
0 | 
| T154 | 
4803 | 
65 | 
0 | 
0 | 
| T155 | 
13513 | 
42 | 
0 | 
0 | 
| T156 | 
7820 | 
3 | 
0 | 
0 | 
| T157 | 
20281 | 
88 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5587 | 
0 | 
0 | 
| T102 | 
99940 | 
784 | 
0 | 
0 | 
| T103 | 
15916 | 
17 | 
0 | 
0 | 
| T124 | 
114399 | 
873 | 
0 | 
0 | 
| T131 | 
10865 | 
131 | 
0 | 
0 | 
| T146 | 
13957 | 
32 | 
0 | 
0 | 
| T149 | 
7588 | 
41 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
54 | 
0 | 
0 | 
| T156 | 
7820 | 
24 | 
0 | 
0 | 
| T157 | 
20281 | 
39 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5749 | 
0 | 
0 | 
| T102 | 
99940 | 
643 | 
0 | 
0 | 
| T103 | 
15916 | 
178 | 
0 | 
0 | 
| T124 | 
114399 | 
808 | 
0 | 
0 | 
| T130 | 
4179 | 
2 | 
0 | 
0 | 
| T146 | 
13957 | 
60 | 
0 | 
0 | 
| T149 | 
7588 | 
24 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
60 | 
0 | 
0 | 
| T156 | 
7820 | 
27 | 
0 | 
0 | 
| T157 | 
20281 | 
26 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5675 | 
0 | 
0 | 
| T102 | 
99940 | 
690 | 
0 | 
0 | 
| T103 | 
15916 | 
126 | 
0 | 
0 | 
| T124 | 
114399 | 
796 | 
0 | 
0 | 
| T130 | 
4179 | 
29 | 
0 | 
0 | 
| T146 | 
13957 | 
22 | 
0 | 
0 | 
| T149 | 
7588 | 
18 | 
0 | 
0 | 
| T154 | 
4803 | 
43 | 
0 | 
0 | 
| T155 | 
13513 | 
28 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
83 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5762 | 
0 | 
0 | 
| T102 | 
99940 | 
842 | 
0 | 
0 | 
| T103 | 
15916 | 
126 | 
0 | 
0 | 
| T124 | 
114399 | 
820 | 
0 | 
0 | 
| T130 | 
4179 | 
9 | 
0 | 
0 | 
| T146 | 
13957 | 
18 | 
0 | 
0 | 
| T149 | 
7588 | 
3 | 
0 | 
0 | 
| T154 | 
4803 | 
50 | 
0 | 
0 | 
| T155 | 
13513 | 
61 | 
0 | 
0 | 
| T156 | 
7820 | 
10 | 
0 | 
0 | 
| T157 | 
20281 | 
104 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
5133 | 
0 | 
0 | 
| T102 | 
99940 | 
838 | 
0 | 
0 | 
| T103 | 
15916 | 
90 | 
0 | 
0 | 
| T124 | 
114399 | 
777 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
5 | 
0 | 
0 | 
| T149 | 
7588 | 
24 | 
0 | 
0 | 
| T154 | 
4803 | 
5 | 
0 | 
0 | 
| T155 | 
13513 | 
71 | 
0 | 
0 | 
| T156 | 
7820 | 
4 | 
0 | 
0 | 
| T157 | 
20281 | 
83 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2453 | 
0 | 
0 | 
| T102 | 
99940 | 
194 | 
0 | 
0 | 
| T103 | 
15916 | 
35 | 
0 | 
0 | 
| T124 | 
114399 | 
793 | 
0 | 
0 | 
| T131 | 
10865 | 
9 | 
0 | 
0 | 
| T146 | 
13957 | 
29 | 
0 | 
0 | 
| T149 | 
7588 | 
23 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
33 | 
0 | 
0 | 
| T156 | 
7820 | 
17 | 
0 | 
0 | 
| T157 | 
20281 | 
64 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2373 | 
0 | 
0 | 
| T102 | 
99940 | 
205 | 
0 | 
0 | 
| T103 | 
15916 | 
49 | 
0 | 
0 | 
| T124 | 
114399 | 
762 | 
0 | 
0 | 
| T130 | 
4179 | 
10 | 
0 | 
0 | 
| T146 | 
13957 | 
63 | 
0 | 
0 | 
| T149 | 
7588 | 
8 | 
0 | 
0 | 
| T154 | 
4803 | 
4 | 
0 | 
0 | 
| T155 | 
13513 | 
9 | 
0 | 
0 | 
| T156 | 
7820 | 
8 | 
0 | 
0 | 
| T157 | 
20281 | 
79 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2474 | 
0 | 
0 | 
| T102 | 
99940 | 
147 | 
0 | 
0 | 
| T103 | 
15916 | 
25 | 
0 | 
0 | 
| T124 | 
114399 | 
833 | 
0 | 
0 | 
| T130 | 
4179 | 
5 | 
0 | 
0 | 
| T146 | 
13957 | 
75 | 
0 | 
0 | 
| T149 | 
7588 | 
7 | 
0 | 
0 | 
| T154 | 
4803 | 
7 | 
0 | 
0 | 
| T155 | 
13513 | 
55 | 
0 | 
0 | 
| T156 | 
7820 | 
7 | 
0 | 
0 | 
| T157 | 
20281 | 
111 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2266 | 
0 | 
0 | 
| T102 | 
99940 | 
196 | 
0 | 
0 | 
| T103 | 
15916 | 
32 | 
0 | 
0 | 
| T124 | 
114399 | 
786 | 
0 | 
0 | 
| T130 | 
4179 | 
9 | 
0 | 
0 | 
| T146 | 
13957 | 
30 | 
0 | 
0 | 
| T149 | 
7588 | 
15 | 
0 | 
0 | 
| T154 | 
4803 | 
8 | 
0 | 
0 | 
| T155 | 
13513 | 
21 | 
0 | 
0 | 
| T156 | 
7820 | 
11 | 
0 | 
0 | 
| T157 | 
20281 | 
69 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2968 | 
0 | 
0 | 
| T102 | 
99940 | 
270 | 
0 | 
0 | 
| T103 | 
15916 | 
57 | 
0 | 
0 | 
| T124 | 
114399 | 
823 | 
0 | 
0 | 
| T130 | 
4179 | 
22 | 
0 | 
0 | 
| T146 | 
13957 | 
19 | 
0 | 
0 | 
| T149 | 
7588 | 
20 | 
0 | 
0 | 
| T154 | 
4803 | 
11 | 
0 | 
0 | 
| T155 | 
13513 | 
43 | 
0 | 
0 | 
| T156 | 
7820 | 
17 | 
0 | 
0 | 
| T157 | 
20281 | 
53 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
4994 | 
0 | 
0 | 
| T8 | 
379277 | 
16 | 
0 | 
0 | 
| T9 | 
1323 | 
0 | 
0 | 
0 | 
| T10 | 
1256 | 
0 | 
0 | 
0 | 
| T11 | 
1777 | 
0 | 
0 | 
0 | 
| T12 | 
1953 | 
0 | 
0 | 
0 | 
| T13 | 
60011 | 
0 | 
0 | 
0 | 
| T14 | 
151304 | 
0 | 
0 | 
0 | 
| T15 | 
80056 | 
0 | 
0 | 
0 | 
| T16 | 
6716 | 
33 | 
0 | 
0 | 
| T23 | 
878122 | 
0 | 
0 | 
0 | 
| T30 | 
0 | 
55 | 
0 | 
0 | 
| T158 | 
0 | 
28 | 
0 | 
0 | 
| T159 | 
0 | 
28 | 
0 | 
0 | 
| T160 | 
0 | 
19 | 
0 | 
0 | 
| T161 | 
0 | 
19 | 
0 | 
0 | 
| T162 | 
0 | 
25 | 
0 | 
0 | 
| T163 | 
0 | 
34 | 
0 | 
0 | 
| T164 | 
0 | 
48 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2367 | 
0 | 
0 | 
| T102 | 
99940 | 
178 | 
0 | 
0 | 
| T103 | 
15916 | 
31 | 
0 | 
0 | 
| T124 | 
114399 | 
739 | 
0 | 
0 | 
| T131 | 
10865 | 
14 | 
0 | 
0 | 
| T146 | 
13957 | 
26 | 
0 | 
0 | 
| T149 | 
7588 | 
10 | 
0 | 
0 | 
| T154 | 
4803 | 
7 | 
0 | 
0 | 
| T155 | 
13513 | 
45 | 
0 | 
0 | 
| T156 | 
7820 | 
25 | 
0 | 
0 | 
| T157 | 
20281 | 
70 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2373 | 
0 | 
0 | 
| T102 | 
99940 | 
151 | 
0 | 
0 | 
| T103 | 
15916 | 
23 | 
0 | 
0 | 
| T124 | 
114399 | 
812 | 
0 | 
0 | 
| T130 | 
4179 | 
6 | 
0 | 
0 | 
| T146 | 
13957 | 
41 | 
0 | 
0 | 
| T149 | 
7588 | 
1 | 
0 | 
0 | 
| T154 | 
4803 | 
12 | 
0 | 
0 | 
| T155 | 
13513 | 
24 | 
0 | 
0 | 
| T156 | 
7820 | 
31 | 
0 | 
0 | 
| T157 | 
20281 | 
49 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2072 | 
0 | 
0 | 
| T102 | 
99940 | 
130 | 
0 | 
0 | 
| T103 | 
15916 | 
31 | 
0 | 
0 | 
| T124 | 
114399 | 
831 | 
0 | 
0 | 
| T131 | 
10865 | 
22 | 
0 | 
0 | 
| T146 | 
13957 | 
55 | 
0 | 
0 | 
| T149 | 
7588 | 
8 | 
0 | 
0 | 
| T154 | 
4803 | 
5 | 
0 | 
0 | 
| T155 | 
13513 | 
21 | 
0 | 
0 | 
| T156 | 
7820 | 
1 | 
0 | 
0 | 
| T157 | 
20281 | 
33 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2098 | 
0 | 
0 | 
| T102 | 
99940 | 
93 | 
0 | 
0 | 
| T103 | 
15916 | 
19 | 
0 | 
0 | 
| T114 | 
18985 | 
3 | 
0 | 
0 | 
| T124 | 
114399 | 
766 | 
0 | 
0 | 
| T146 | 
13957 | 
19 | 
0 | 
0 | 
| T149 | 
7588 | 
41 | 
0 | 
0 | 
| T154 | 
4803 | 
4 | 
0 | 
0 | 
| T155 | 
13513 | 
31 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
81 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2231 | 
0 | 
0 | 
| T102 | 
99940 | 
129 | 
0 | 
0 | 
| T103 | 
15916 | 
27 | 
0 | 
0 | 
| T124 | 
114399 | 
872 | 
0 | 
0 | 
| T130 | 
4179 | 
8 | 
0 | 
0 | 
| T146 | 
13957 | 
44 | 
0 | 
0 | 
| T149 | 
7588 | 
11 | 
0 | 
0 | 
| T154 | 
4803 | 
5 | 
0 | 
0 | 
| T155 | 
13513 | 
49 | 
0 | 
0 | 
| T156 | 
7820 | 
7 | 
0 | 
0 | 
| T157 | 
20281 | 
48 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2187 | 
0 | 
0 | 
| T102 | 
99940 | 
117 | 
0 | 
0 | 
| T103 | 
15916 | 
35 | 
0 | 
0 | 
| T124 | 
114399 | 
816 | 
0 | 
0 | 
| T130 | 
4179 | 
10 | 
0 | 
0 | 
| T146 | 
13957 | 
84 | 
0 | 
0 | 
| T149 | 
7588 | 
15 | 
0 | 
0 | 
| T154 | 
4803 | 
6 | 
0 | 
0 | 
| T155 | 
13513 | 
62 | 
0 | 
0 | 
| T156 | 
7820 | 
13 | 
0 | 
0 | 
| T157 | 
20281 | 
85 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2859 | 
0 | 
0 | 
| T102 | 
99940 | 
221 | 
0 | 
0 | 
| T103 | 
15916 | 
31 | 
0 | 
0 | 
| T124 | 
114399 | 
819 | 
0 | 
0 | 
| T130 | 
4179 | 
5 | 
0 | 
0 | 
| T146 | 
13957 | 
36 | 
0 | 
0 | 
| T149 | 
7588 | 
24 | 
0 | 
0 | 
| T154 | 
4803 | 
3 | 
0 | 
0 | 
| T155 | 
13513 | 
34 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
35 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2256 | 
0 | 
0 | 
| T102 | 
99940 | 
113 | 
0 | 
0 | 
| T103 | 
15916 | 
22 | 
0 | 
0 | 
| T124 | 
114399 | 
822 | 
0 | 
0 | 
| T131 | 
10865 | 
19 | 
0 | 
0 | 
| T146 | 
13957 | 
103 | 
0 | 
0 | 
| T149 | 
7588 | 
22 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
53 | 
0 | 
0 | 
| T156 | 
7820 | 
12 | 
0 | 
0 | 
| T157 | 
20281 | 
86 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
3368 | 
0 | 
0 | 
| T102 | 
99940 | 
370 | 
0 | 
0 | 
| T103 | 
15916 | 
40 | 
0 | 
0 | 
| T124 | 
114399 | 
777 | 
0 | 
0 | 
| T130 | 
4179 | 
1 | 
0 | 
0 | 
| T146 | 
13957 | 
31 | 
0 | 
0 | 
| T149 | 
7588 | 
24 | 
0 | 
0 | 
| T154 | 
4803 | 
26 | 
0 | 
0 | 
| T155 | 
13513 | 
23 | 
0 | 
0 | 
| T156 | 
7820 | 
10 | 
0 | 
0 | 
| T157 | 
20281 | 
92 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2485 | 
0 | 
0 | 
| T102 | 
99940 | 
159 | 
0 | 
0 | 
| T103 | 
15916 | 
26 | 
0 | 
0 | 
| T124 | 
114399 | 
774 | 
0 | 
0 | 
| T130 | 
4179 | 
6 | 
0 | 
0 | 
| T146 | 
13957 | 
93 | 
0 | 
0 | 
| T149 | 
7588 | 
21 | 
0 | 
0 | 
| T154 | 
4803 | 
12 | 
0 | 
0 | 
| T155 | 
13513 | 
60 | 
0 | 
0 | 
| T156 | 
7820 | 
33 | 
0 | 
0 | 
| T157 | 
20281 | 
88 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2164 | 
0 | 
0 | 
| T102 | 
99940 | 
118 | 
0 | 
0 | 
| T103 | 
15916 | 
38 | 
0 | 
0 | 
| T124 | 
114399 | 
818 | 
0 | 
0 | 
| T130 | 
4179 | 
5 | 
0 | 
0 | 
| T146 | 
13957 | 
69 | 
0 | 
0 | 
| T149 | 
7588 | 
11 | 
0 | 
0 | 
| T154 | 
4803 | 
8 | 
0 | 
0 | 
| T155 | 
13513 | 
33 | 
0 | 
0 | 
| T156 | 
7820 | 
15 | 
0 | 
0 | 
| T157 | 
20281 | 
26 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2240 | 
0 | 
0 | 
| T102 | 
99940 | 
114 | 
0 | 
0 | 
| T103 | 
15916 | 
31 | 
0 | 
0 | 
| T124 | 
114399 | 
783 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T146 | 
13957 | 
73 | 
0 | 
0 | 
| T149 | 
7588 | 
30 | 
0 | 
0 | 
| T154 | 
4803 | 
6 | 
0 | 
0 | 
| T155 | 
13513 | 
60 | 
0 | 
0 | 
| T156 | 
7820 | 
34 | 
0 | 
0 | 
| T157 | 
20281 | 
101 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2236 | 
0 | 
0 | 
| T102 | 
99940 | 
116 | 
0 | 
0 | 
| T103 | 
15916 | 
19 | 
0 | 
0 | 
| T124 | 
114399 | 
841 | 
0 | 
0 | 
| T131 | 
10865 | 
10 | 
0 | 
0 | 
| T146 | 
13957 | 
68 | 
0 | 
0 | 
| T149 | 
7588 | 
20 | 
0 | 
0 | 
| T154 | 
4803 | 
5 | 
0 | 
0 | 
| T155 | 
13513 | 
36 | 
0 | 
0 | 
| T156 | 
7820 | 
36 | 
0 | 
0 | 
| T157 | 
20281 | 
71 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2067 | 
0 | 
0 | 
| T102 | 
99940 | 
134 | 
0 | 
0 | 
| T103 | 
15916 | 
19 | 
0 | 
0 | 
| T124 | 
114399 | 
859 | 
0 | 
0 | 
| T130 | 
4179 | 
1 | 
0 | 
0 | 
| T131 | 
10865 | 
6 | 
0 | 
0 | 
| T146 | 
13957 | 
36 | 
0 | 
0 | 
| T149 | 
7588 | 
6 | 
0 | 
0 | 
| T155 | 
13513 | 
56 | 
0 | 
0 | 
| T156 | 
7820 | 
1 | 
0 | 
0 | 
| T157 | 
20281 | 
71 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
1957 | 
0 | 
0 | 
| T102 | 
99940 | 
113 | 
0 | 
0 | 
| T103 | 
15916 | 
26 | 
0 | 
0 | 
| T124 | 
114399 | 
763 | 
0 | 
0 | 
| T130 | 
4179 | 
4 | 
0 | 
0 | 
| T131 | 
10865 | 
8 | 
0 | 
0 | 
| T146 | 
13957 | 
24 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
38 | 
0 | 
0 | 
| T156 | 
7820 | 
1 | 
0 | 
0 | 
| T157 | 
20281 | 
51 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
488727432 | 
2272 | 
0 | 
0 | 
| T102 | 
99940 | 
110 | 
0 | 
0 | 
| T103 | 
15916 | 
28 | 
0 | 
0 | 
| T124 | 
114399 | 
803 | 
0 | 
0 | 
| T130 | 
4179 | 
9 | 
0 | 
0 | 
| T146 | 
13957 | 
83 | 
0 | 
0 | 
| T149 | 
7588 | 
48 | 
0 | 
0 | 
| T154 | 
4803 | 
2 | 
0 | 
0 | 
| T155 | 
13513 | 
40 | 
0 | 
0 | 
| T156 | 
7820 | 
52 | 
0 | 
0 | 
| T157 | 
20281 | 
57 | 
0 | 
0 |