Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3596687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4222020

1

T1

1

T2

875

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4307768	1			T1	69		T2	2		T3	1
values[0x0]	1754953	1			T2	442		T3	2		T4	1878
values[0x1]	1755986	1			T2	434		T3	5		T4	1847

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2549743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5268964

1

T1

18

T2

876

T3

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29853	1			T4	21		T9	14		T10	3
valid_sources[0x01]	28949	1			T1	1		T2	1		T4	13
valid_sources[0x02]	30564	1			T1	2		T4	14		T10	2
valid_sources[0x03]	30761	1			T4	15		T10	4		T11	35
valid_sources[0x04]	30391	1			T4	13		T10	6		T11	9
valid_sources[0x05]	29951	1			T4	24		T10	3		T11	37
valid_sources[0x06]	34874	1			T4	14		T7	5642		T10	2
valid_sources[0x07]	31630	1			T1	2		T4	12		T10	3
valid_sources[0x08]	31268	1			T4	10		T8	1267		T10	6
valid_sources[0x09]	30076	1			T2	27		T4	25		T5	1
valid_sources[0x0a]	29137	1			T1	1		T4	11		T5	2
valid_sources[0x0b]	28845	1			T4	20		T9	47		T10	2
valid_sources[0x0c]	29112	1			T4	22		T10	3		T11	117
valid_sources[0x0d]	28538	1			T4	18		T5	2		T10	3
valid_sources[0x0e]	30580	1			T4	14		T10	2		T11	2
valid_sources[0x0f]	32301	1			T2	2		T4	15		T5	1
valid_sources[0x10]	39360	1			T4	17		T5	1		T8	1
valid_sources[0x11]	31435	1			T4	19		T10	5		T11	97
valid_sources[0x12]	27780	1			T4	21		T5	1		T10	2
valid_sources[0x13]	34511	1			T4	17		T10	5		T11	26
valid_sources[0x14]	29420	1			T1	1		T2	7		T4	13
valid_sources[0x15]	29386	1			T4	14		T10	3		T11	60
valid_sources[0x16]	34012	1			T4	23		T9	28		T10	5
valid_sources[0x17]	33926	1			T4	21		T10	1		T11	10
valid_sources[0x18]	29482	1			T2	31		T4	15		T8	958
valid_sources[0x19]	28597	1			T4	20		T5	1		T8	24
valid_sources[0x1a]	30595	1			T2	10		T4	18		T10	8
valid_sources[0x1b]	28151	1			T4	13		T10	5		T11	19
valid_sources[0x1c]	31017	1			T4	15		T9	128		T10	1
valid_sources[0x1d]	31873	1			T2	14		T4	20		T10	4
valid_sources[0x1e]	36289	1			T4	17		T10	4		T11	6
valid_sources[0x1f]	29575	1			T4	20		T10	3		T12	1
valid_sources[0x20]	29602	1			T1	1		T2	13		T4	18
valid_sources[0x21]	27740	1			T2	10		T4	16		T9	36
valid_sources[0x22]	29495	1			T1	1		T4	21		T9	48
valid_sources[0x23]	28742	1			T1	1		T4	13		T10	4
valid_sources[0x24]	33359	1			T4	9		T10	6		T12	6
valid_sources[0x25]	31741	1			T4	26		T10	6		T11	33
valid_sources[0x26]	30135	1			T4	18		T8	1352		T10	6
valid_sources[0x27]	30044	1			T4	20		T10	3		T11	95
valid_sources[0x28]	29216	1			T4	9		T10	6		T11	54
valid_sources[0x29]	30037	1			T4	13		T5	1		T10	3
valid_sources[0x2a]	27453	1			T4	12		T10	3		T11	19
valid_sources[0x2b]	56250	1			T4	14		T5	1		T10	4
valid_sources[0x2c]	28346	1			T1	1		T4	18		T10	4
valid_sources[0x2d]	33049	1			T1	1		T4	12		T10	1
valid_sources[0x2e]	29390	1			T2	17		T4	23		T10	2
valid_sources[0x2f]	33318	1			T2	10		T4	15		T10	4
valid_sources[0x30]	28581	1			T4	17		T10	4		T11	20
valid_sources[0x31]	30283	1			T4	18		T10	4		T12	4
valid_sources[0x32]	29161	1			T4	14		T10	5		T11	8
valid_sources[0x33]	32139	1			T4	12		T5	1		T9	1
valid_sources[0x34]	32010	1			T4	20		T9	1		T10	4
valid_sources[0x35]	29853	1			T2	36		T4	15		T10	4
valid_sources[0x36]	28834	1			T4	18		T10	6		T11	16
valid_sources[0x37]	27048	1			T2	47		T4	16		T10	4
valid_sources[0x38]	29765	1			T2	19		T4	18		T5	2
valid_sources[0x39]	29948	1			T4	17		T9	40		T10	3
valid_sources[0x3a]	32038	1			T1	3		T4	20		T5	1
valid_sources[0x3b]	28819	1			T1	2		T4	18		T10	6
valid_sources[0x3c]	34345	1			T2	16		T4	14		T10	7
valid_sources[0x3d]	28109	1			T2	21		T4	17		T10	5
valid_sources[0x3e]	28044	1			T2	3		T4	33		T10	1
valid_sources[0x3f]	30329	1			T4	27		T10	2		T11	52
valid_sources[0x40]	30059	1			T4	22		T10	3		T11	53
valid_sources[0x41]	28572	1			T4	16		T10	6		T12	10
valid_sources[0x42]	28038	1			T2	30		T4	18		T9	60
valid_sources[0x43]	30750	1			T3	1		T4	19		T8	1
valid_sources[0x44]	30026	1			T4	25		T10	3		T11	4
valid_sources[0x45]	34915	1			T4	9		T10	4		T41	2
valid_sources[0x46]	30595	1			T4	14		T10	8		T11	37
valid_sources[0x47]	36453	1			T2	2		T4	18		T6	2922
valid_sources[0x48]	29838	1			T4	15		T10	5		T11	13
valid_sources[0x49]	31673	1			T4	16		T10	1		T11	4
valid_sources[0x4a]	30433	1			T1	1		T2	4		T4	17
valid_sources[0x4b]	30429	1			T2	7		T4	10		T10	3
valid_sources[0x4c]	31107	1			T4	14		T10	3		T11	22
valid_sources[0x4d]	30912	1			T2	4		T4	20		T5	1
valid_sources[0x4e]	30944	1			T3	1		T4	14		T10	4
valid_sources[0x4f]	30253	1			T4	13		T10	4		T12	9
valid_sources[0x50]	28568	1			T4	22		T10	1		T11	22
valid_sources[0x51]	30177	1			T4	19		T10	6		T11	22
valid_sources[0x52]	31555	1			T4	18		T9	56		T10	2
valid_sources[0x53]	34186	1			T3	3		T4	16		T10	3
valid_sources[0x54]	31907	1			T4	11		T10	1		T11	9
valid_sources[0x55]	31380	1			T1	1		T2	7		T4	12
valid_sources[0x56]	29507	1			T4	10		T8	416		T10	6
valid_sources[0x57]	29183	1			T2	28		T4	22		T10	3
valid_sources[0x58]	28534	1			T2	5		T4	13		T9	33
valid_sources[0x59]	29152	1			T4	19		T10	3		T11	9
valid_sources[0x5a]	29243	1			T4	25		T10	8		T11	15
valid_sources[0x5b]	30678	1			T2	1		T4	26		T9	3
valid_sources[0x5c]	27898	1			T1	1		T4	15		T10	4
valid_sources[0x5d]	29617	1			T4	17		T10	4		T11	63
valid_sources[0x5e]	32307	1			T1	1		T4	14		T10	4
valid_sources[0x5f]	30870	1			T4	18		T10	4		T11	27
valid_sources[0x60]	29221	1			T4	13		T10	9		T11	60
valid_sources[0x61]	29241	1			T1	1		T4	14		T11	12
valid_sources[0x62]	29570	1			T4	12		T10	4		T11	7
valid_sources[0x63]	30027	1			T4	11		T10	3		T11	31
valid_sources[0x64]	28836	1			T4	24		T10	3		T11	3
valid_sources[0x65]	32320	1			T4	9		T10	2		T11	2
valid_sources[0x66]	32920	1			T4	13		T10	3		T11	53
valid_sources[0x67]	31503	1			T4	19		T5	2		T9	62
valid_sources[0x68]	31605	1			T4	19		T10	2		T12	3
valid_sources[0x69]	28586	1			T4	15		T10	4		T11	12
valid_sources[0x6a]	29527	1			T1	7		T4	25		T10	4
valid_sources[0x6b]	29139	1			T4	23		T5	1		T10	5
valid_sources[0x6c]	28532	1			T4	20		T10	4		T11	20
valid_sources[0x6d]	28412	1			T1	1		T3	1		T4	26
valid_sources[0x6e]	29095	1			T4	23		T8	416		T10	5
valid_sources[0x6f]	33793	1			T4	13		T9	97		T10	2
valid_sources[0x70]	32588	1			T4	20		T10	4		T11	42
valid_sources[0x71]	28426	1			T4	15		T10	6		T11	1
valid_sources[0x72]	29896	1			T1	1		T4	11		T10	6
valid_sources[0x73]	31020	1			T4	16		T10	3		T11	83
valid_sources[0x74]	29930	1			T4	29		T10	3		T11	84
valid_sources[0x75]	31429	1			T2	2		T4	19		T10	4
valid_sources[0x76]	30665	1			T4	20		T8	2004		T10	2
valid_sources[0x77]	30440	1			T1	2		T4	19		T9	51
valid_sources[0x78]	26837	1			T2	13		T4	22		T9	46
valid_sources[0x79]	29443	1			T4	17		T10	3		T12	8
valid_sources[0x7a]	28570	1			T4	23		T10	2		T11	19
valid_sources[0x7b]	28491	1			T4	17		T10	3		T11	108
valid_sources[0x7c]	30040	1			T4	25		T10	2		T11	91
valid_sources[0x7d]	28051	1			T4	22		T10	4		T11	28
valid_sources[0x7e]	28393	1			T4	16		T10	2		T11	29
valid_sources[0x7f]	28853	1			T1	2		T4	16		T8	2
valid_sources[0x80]	32265	1			T1	4		T4	29		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1045028

1

T1

1

T3

1

T4

389

values[0x0]

all_enables

biggest_size

1599656

1

T2

442

T3

2

T4

1869

values[0x1]

all_enables

biggest_size

1577336

1

T2

433

T4

1833

T6

458