Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3614520

1

T1

68

T2

3

T3

5

full_word

4223036

1

T1

1

T2

875

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7837236	1			T1	69		T2	878		T3	8
auto[TlIntgErrCmd]	116	1			T79	7		T80	6		T81	4
auto[TlIntgErrData]	95	1			T79	4		T80	6		T81	4
auto[TlIntgErrBoth]	109	1			T79	9		T80	8		T81	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4310609

1

T1

69

T2

2

T3

1

auto[1]

3526947

1

T2

876

T3

7

T4

3725

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3265206	1			T1	68		T2	2		T4	407
auto[TlIntgErrNone]	partial	auto[1]	349020	1			T2	1		T3	5		T4	23
auto[TlIntgErrNone]	full_word	auto[0]	1045263	1			T1	1		T3	1		T4	389
auto[TlIntgErrNone]	full_word	auto[1]	3177747	1			T2	875		T3	2		T4	3702
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T79	3		T80	4		T81	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T79	4		T80	2		T81	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T158	1		T159	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T160	1		T158	1		T161	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T79	2		T80	5		T81	3
auto[TlIntgErrData]	partial	auto[1]	38	1			T79	1		T80	1		T81	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T79	1		T96	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T93	1		T155	1		T162	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T79	4		T80	4		T81	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T79	4		T80	4		T93	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T96	1		T163	2		T161	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T79	1		T93	2		T158	1