Line Coverage for Module : 
spid_csb_sync
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 11 | 11 | 100.00 | 
| ALWAYS | 32 | 4 | 4 | 100.00 | 
| ALWAYS | 44 | 3 | 3 | 100.00 | 
| ALWAYS | 63 | 3 | 3 | 100.00 | 
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 32 | 
1 | 
1 | 
| 33 | 
1 | 
1 | 
| 35 | 
1 | 
1 | 
| 36 | 
1 | 
1 | 
 | 
 | 
 | 
     MISSING_ELSE | 
| 44 | 
1 | 
1 | 
| 45 | 
1 | 
1 | 
| 47 | 
1 | 
1 | 
| 63 | 
1 | 
1 | 
| 64 | 
1 | 
1 | 
| 66 | 
1 | 
1 | 
| 70 | 
1 | 
1 | 
Cond Coverage for Module : 
spid_csb_sync
 | Total | Covered | Percent | 
| Conditions | 2 | 2 | 100.00 | 
| Logical | 2 | 2 | 100.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
| -1- | Status | Tests |                       
| 0 | Covered | T1,T2,T3 | 
| 1 | Covered | T2,T4,T6 | 
Branch Coverage for Module : 
spid_csb_sync
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
7 | 
7 | 
100.00 | 
| IF | 
32 | 
3 | 
3 | 
100.00 | 
| IF | 
44 | 
2 | 
2 | 
100.00 | 
| IF | 
63 | 
2 | 
2 | 
100.00 | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)
Branches:
| -1- | -2- | Status | Tests | 
| 1 | 
- | 
Covered | 
T1,T2,T3 | 
| 0 | 
1 | 
Covered | 
T2,T4,T6 | 
| 0 | 
0 | 
Covered | 
T2,T4,T6 | 
	LineNo.	Expression
-1-:	44	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T4 | 
	LineNo.	Expression
-1-:	63	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T3 | 
 
Line Coverage for Instance : tb.dut.u_spid_csb_sync
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 11 | 11 | 100.00 | 
| ALWAYS | 32 | 4 | 4 | 100.00 | 
| ALWAYS | 44 | 3 | 3 | 100.00 | 
| ALWAYS | 63 | 3 | 3 | 100.00 | 
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 32 | 
1 | 
1 | 
| 33 | 
1 | 
1 | 
| 35 | 
1 | 
1 | 
| 36 | 
1 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
| 44 | 
1 | 
1 | 
| 45 | 
1 | 
1 | 
| 47 | 
1 | 
1 | 
| 63 | 
1 | 
1 | 
| 64 | 
1 | 
1 | 
| 66 | 
1 | 
1 | 
| 70 | 
1 | 
1 | 
Cond Coverage for Instance : tb.dut.u_spid_csb_sync
 | Total | Covered | Percent | 
| Conditions | 2 | 2 | 100.00 | 
| Logical | 2 | 2 | 100.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
| -1- | Status | Tests |                       
| 0 | Covered | T1,T2,T3 | 
| 1 | Covered | T2,T4,T6 | 
Branch Coverage for Instance : tb.dut.u_spid_csb_sync
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
7 | 
6 | 
85.71  | 
| IF | 
32 | 
3 | 
2 | 
66.67  | 
| IF | 
44 | 
2 | 
2 | 
100.00 | 
| IF | 
63 | 
2 | 
2 | 
100.00 | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)
Branches:
| -1- | -2- | Status | Tests | 
| 1 | 
- | 
Covered | 
T1,T2,T3 | 
| 0 | 
1 | 
Covered | 
T2,T4,T6 | 
| 0 | 
0 | 
Not Covered | 
 | 
	LineNo.	Expression
-1-:	44	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T4 | 
	LineNo.	Expression
-1-:	63	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T3 | 
 
Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 11 | 11 | 100.00 | 
| ALWAYS | 32 | 4 | 4 | 100.00 | 
| ALWAYS | 44 | 3 | 3 | 100.00 | 
| ALWAYS | 63 | 3 | 3 | 100.00 | 
| CONT_ASSIGN | 70 | 1 | 1 | 100.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 32 | 
1 | 
1 | 
| 33 | 
1 | 
1 | 
| 35 | 
1 | 
1 | 
| 36 | 
1 | 
1 | 
 | 
 | 
 | 
     MISSING_ELSE | 
| 44 | 
1 | 
1 | 
| 45 | 
1 | 
1 | 
| 47 | 
1 | 
1 | 
| 63 | 
1 | 
1 | 
| 64 | 
1 | 
1 | 
| 66 | 
1 | 
1 | 
| 70 | 
1 | 
1 | 
Cond Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
 | Total | Covered | Percent | 
| Conditions | 2 | 2 | 100.00 | 
| Logical | 2 | 2 | 100.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       70
 EXPRESSION (sys_toggle != sys_toggle_last)
            ---------------1---------------
| -1- | Status | Tests |                       
| 0 | Covered | T1,T2,T3 | 
| 1 | Covered | T8,T15,T23 | 
Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
7 | 
7 | 
100.00 | 
| IF | 
32 | 
3 | 
3 | 
100.00 | 
| IF | 
44 | 
2 | 
2 | 
100.00 | 
| IF | 
63 | 
2 | 
2 | 
100.00 | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_csb_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	32	if ((!rst_ni))
-2-:	35	if (sck_pulse_en_i)
Branches:
| -1- | -2- | Status | Tests | 
| 1 | 
- | 
Covered | 
T1,T2,T3 | 
| 0 | 
1 | 
Covered | 
T8,T15,T23 | 
| 0 | 
0 | 
Covered | 
T2,T4,T6 | 
	LineNo.	Expression
-1-:	44	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T4 | 
	LineNo.	Expression
-1-:	63	if ((!rst_ni))
Branches:
| -1- | Status | Tests | 
| 1 | 
Covered | 
T1,T2,T3 | 
| 0 | 
Covered | 
T1,T2,T3 |