Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	2814740	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	2814740	0	0
T2	10838	1663	0	0
T3	1175	0	0	0
T4	23880	7284	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	1663	0	0
T8	219164	9147	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	0	0	0
T12	0	832	0	0
T15	0	4160	0	0
T41	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	3097171	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	3097171	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	4992	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	0	0	0
T12	0	832	0	0
T15	0	8832	0	0
T41	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	187025	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	187025	0	0
T8	219164	257	0	0
T9	29370	0	0	0
T10	386279	0	0	0
T11	480714	508	0	0
T12	14885	0	0	0
T13	890837	783	0	0
T14	8261	0	0	0
T15	211936	160	0	0
T16	24724	0	0	0
T17	0	443	0	0
T23	0	840	0	0
T28	0	820	0	0
T29	0	802	0	0
T39	0	32	0	0
T40	0	1	0	0
T41	3781	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	441586	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	441586	0	0
T8	219164	257	0	0
T9	29370	0	0	0
T10	386279	0	0	0
T11	480714	1521	0	0
T12	14885	0	0	0
T13	890837	783	0	0
T14	8261	0	0	0
T15	211936	480	0	0
T16	24724	0	0	0
T17	0	443	0	0
T23	0	3775	0	0
T28	0	820	0	0
T29	0	802	0	0
T39	0	32	0	0
T40	0	1	0	0
T41	3781	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	6140311	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	6140311	0	0
T1	2146	69	0	0
T2	10838	46	0	0
T3	1175	8	0	0
T4	23880	879	0	0
T5	1258	41	0	0
T6	95178	3466	0	0
T7	126336	5262	0	0
T8	219164	3095	0	0
T9	29370	644	0	0
T10	386279	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	469967919	12826480	0	0
DepthKnown_A	469967919	469842112	0	0
RvalidKnown_A	469967919	469842112	0	0
WreadyKnown_A	469967919	469842112	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	12826480	0	0
T1	2146	307	0	0
T2	10838	46	0	0
T3	1175	8	0	0
T4	23880	873	0	0
T5	1258	41	0	0
T6	95178	3465	0	0
T7	126336	5262	0	0
T8	219164	3092	0	0
T9	29370	644	0	0
T10	386279	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	469967919	469842112	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0