Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T23
1	0	Covered	T11,T13,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T23
1	0	Unreachable
1	1	Covered	T11,T13,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T23
1	0	Covered	T8,T15,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T8,T15,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T11,T13
1	0	Covered	T2,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	760032898	612635570	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	760032898	3748551	0	0
GntImpliesValid_A	760032898	3748551	0	0
GrantKnown_A	760032898	612635570	0	0
IdxKnown_A	760032898	612635570	0	0
IndexIsCorrect_A	760032898	3748551	0	0
LockArbDecision_A	760032898	0	0	0
NoReadyValidNoGrant_A	760032898	0	0	0
ReadyAndValidImplyGrant_A	760032898	3748551	0	0
ReqAndReadyImplyGrant_A	760032898	3748551	0	0
ReqImpliesValid_A	760032898	3748551	0	0
ReqStaysHighUntilGranted0_M	760032898	0	0	0
RoundRobin_A	760032898	4	0	956
ValidKnown_A	760032898	612635570	0	0
gen_data_port_assertion.DataFlow_A	760032898	3748551	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	612635570	0	0
T1	2146	2085	0	0
T2	14966	14876	0	0
T3	1175	1118	0	0
T4	81528	81193	0	0
T5	1258	1191	0	0
T6	124432	123883	0	0
T7	143926	143850	0	0
T8	529382	528781	0	0
T9	37818	37767	0	0
T10	514859	513687	0	0
T11	121264	59104	0	0
T12	49202	24596	0	0
T13	245748	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	612635570	0	0
T1	2146	2085	0	0
T2	14966	14876	0	0
T3	1175	1118	0	0
T4	81528	81193	0	0
T5	1258	1191	0	0
T6	124432	123883	0	0
T7	143926	143850	0	0
T8	529382	528781	0	0
T9	37818	37767	0	0
T10	514859	513687	0	0
T11	121264	59104	0	0
T12	49202	24596	0	0
T13	245748	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	612635570	0	0
T1	2146	2085	0	0
T2	14966	14876	0	0
T3	1175	1118	0	0
T4	81528	81193	0	0
T5	1258	1191	0	0
T6	124432	123883	0	0
T7	143926	143850	0	0
T8	529382	528781	0	0
T9	37818	37767	0	0
T10	514859	513687	0	0
T11	121264	59104	0	0
T12	49202	24596	0	0
T13	245748	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	4	0	956
T20	265374	1	0	1
T21	206443	0	0	1
T45	51464	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	25511	0	0	1
T54	1714	0	0	1
T55	1102	0	0	1
T56	58043	0	0	1
T57	1047	0	0	1
T58	9742	0	0	1
T59	212720	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	612635570	0	0
T1	2146	2085	0	0
T2	14966	14876	0	0
T3	1175	1118	0	0
T4	81528	81193	0	0
T5	1258	1191	0	0
T6	124432	123883	0	0
T7	143926	143850	0	0
T8	529382	528781	0	0
T9	37818	37767	0	0
T10	514859	513687	0	0
T11	121264	59104	0	0
T12	49202	24596	0	0
T13	245748	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	760032898	3748551	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	529382	8982	0	0
T9	37818	832	0	0
T10	514859	832	0	0
T11	601978	3693	0	0
T12	49202	832	0	0
T13	245748	5026	0	0
T15	697284	648	0	0
T16	21344	0	0	0
T17	275816	3619	0	0
T19	0	11998	0	0
T20	0	12455	0	0
T23	449746	4450	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4763	0	0
T29	0	5155	0	0
T30	0	1719	0	0
T31	0	6724	0	0
T39	0	130	0	0
T41	0	832	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T23
1	0	Covered	T11,T13,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T23
1	0	Unreachable
1	1	Covered	T11,T13,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T13,T23
0	0	1	Unreachable
0	0	0	Covered	T11,T13,T23

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145987758	27014448	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145987758	624459	0	0
GntImpliesValid_A	145987758	624459	0	0
GrantKnown_A	145987758	27014448	0	0
IdxKnown_A	145987758	27014448	0	0
IndexIsCorrect_A	145987758	624459	0	0
LockArbDecision_A	145987758	0	0	0
NoReadyValidNoGrant_A	145987758	0	0	0
ReadyAndValidImplyGrant_A	145987758	624459	0	0
ReqAndReadyImplyGrant_A	145987758	624459	0	0
ReqImpliesValid_A	145987758	624459	0	0
ReqStaysHighUntilGranted0_M	145987758	0	0	0
RoundRobin_A	145987758	0	0	0
ValidKnown_A	145987758	27014448	0	0
gen_data_port_assertion.DataFlow_A	145987758	624459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	27014448	0	0
T11	60632	59104	0	0
T12	24601	0	0	0
T13	122874	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	27014448	0	0
T11	60632	59104	0	0
T12	24601	0	0	0
T13	122874	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	27014448	0	0
T11	60632	59104	0	0
T12	24601	0	0	0
T13	122874	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	27014448	0	0
T11	60632	59104	0	0
T12	24601	0	0	0
T13	122874	115984	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	74672	0	0
T23	224873	71576	0	0
T24	2080	0	0	0
T25	360	360	0	0
T26	72	72	0	0
T27	0	360	0	0
T28	0	130456	0	0
T29	0	157784	0	0
T30	0	27824	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	624459	0	0
T11	60632	2610	0	0
T12	24601	0	0	0
T13	122874	5026	0	0
T15	348642	0	0	0
T16	10672	0	0	0
T17	137908	2209	0	0
T19	0	6638	0	0
T20	0	6145	0	0
T23	224873	2898	0	0
T24	2080	0	0	0
T25	360	0	0	0
T26	72	0	0	0
T28	0	4755	0	0
T29	0	5155	0	0
T30	0	1329	0	0
T31	0	6724	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T23

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T23
1	0	Covered	T8,T15,T23

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T8,T15,T23

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T15,T23
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T23
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T23
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	145987758	117650375	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	145987758	893642	0	0
GntImpliesValid_A	145987758	893642	0	0
GrantKnown_A	145987758	117650375	0	0
IdxKnown_A	145987758	117650375	0	0
IndexIsCorrect_A	145987758	893642	0	0
LockArbDecision_A	145987758	0	0	0
NoReadyValidNoGrant_A	145987758	0	0	0
ReadyAndValidImplyGrant_A	145987758	893642	0	0
ReqAndReadyImplyGrant_A	145987758	893642	0	0
ReqImpliesValid_A	145987758	893642	0	0
ReqStaysHighUntilGranted0_M	145987758	0	0	0
RoundRobin_A	145987758	0	0	0
ValidKnown_A	145987758	117650375	0	0
gen_data_port_assertion.DataFlow_A	145987758	893642	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	117650375	0	0
T2	4128	4128	0	0
T4	57648	57405	0	0
T6	29254	28784	0	0
T7	17590	17590	0	0
T8	310218	309622	0	0
T9	8448	8448	0	0
T10	128580	127492	0	0
T11	60632	0	0	0
T12	24601	24596	0	0
T13	122874	0	0	0
T15	0	347810	0	0
T16	0	10672	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	117650375	0	0
T2	4128	4128	0	0
T4	57648	57405	0	0
T6	29254	28784	0	0
T7	17590	17590	0	0
T8	310218	309622	0	0
T9	8448	8448	0	0
T10	128580	127492	0	0
T11	60632	0	0	0
T12	24601	24596	0	0
T13	122874	0	0	0
T15	0	347810	0	0
T16	0	10672	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	117650375	0	0
T2	4128	4128	0	0
T4	57648	57405	0	0
T6	29254	28784	0	0
T7	17590	17590	0	0
T8	310218	309622	0	0
T9	8448	8448	0	0
T10	128580	127492	0	0
T11	60632	0	0	0
T12	24601	24596	0	0
T13	122874	0	0	0
T15	0	347810	0	0
T16	0	10672	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	117650375	0	0
T2	4128	4128	0	0
T4	57648	57405	0	0
T6	29254	28784	0	0
T7	17590	17590	0	0
T8	310218	309622	0	0
T9	8448	8448	0	0
T10	128580	127492	0	0
T11	60632	0	0	0
T12	24601	24596	0	0
T13	122874	0	0	0
T15	0	347810	0	0
T16	0	10672	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145987758	893642	0	0
T8	310218	3718	0	0
T9	8448	0	0	0
T10	128580	0	0	0
T11	60632	0	0	0
T12	24601	0	0	0
T13	122874	0	0	0
T15	348642	648	0	0
T16	10672	0	0	0
T17	137908	1410	0	0
T19	0	5360	0	0
T20	0	6310	0	0
T23	224873	1552	0	0
T28	0	8	0	0
T30	0	390	0	0
T39	0	130	0	0
T40	0	10	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T11,T13
1	0	Covered	T2,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	468057382	467970747	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	468057382	2230450	0	0
GntImpliesValid_A	468057382	2230450	0	0
GrantKnown_A	468057382	467970747	0	0
IdxKnown_A	468057382	467970747	0	0
IndexIsCorrect_A	468057382	2230450	0	0
LockArbDecision_A	468057382	0	0	0
NoReadyValidNoGrant_A	468057382	0	0	0
ReadyAndValidImplyGrant_A	468057382	2230450	0	0
ReqAndReadyImplyGrant_A	468057382	2230450	0	0
ReqImpliesValid_A	468057382	2230450	0	0
ReqStaysHighUntilGranted0_M	468057382	0	0	0
RoundRobin_A	468057382	4	0	956
ValidKnown_A	468057382	467970747	0	0
gen_data_port_assertion.DataFlow_A	468057382	2230450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	467970747	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	467970747	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	467970747	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	4	0	956
T20	265374	1	0	1
T21	206443	0	0	1
T45	51464	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	25511	0	0	1
T54	1714	0	0	1
T55	1102	0	0	1
T56	58043	0	0	1
T57	1047	0	0	1
T58	9742	0	0	1
T59	212720	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	467970747	0	0
T1	2146	2085	0	0
T2	10838	10748	0	0
T3	1175	1118	0	0
T4	23880	23788	0	0
T5	1258	1191	0	0
T6	95178	95099	0	0
T7	126336	126260	0	0
T8	219164	219159	0	0
T9	29370	29319	0	0
T10	386279	386195	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468057382	2230450	0	0
T2	10838	832	0	0
T3	1175	0	0	0
T4	23880	3648	0	0
T5	1258	0	0	0
T6	95178	832	0	0
T7	126336	832	0	0
T8	219164	5264	0	0
T9	29370	832	0	0
T10	386279	832	0	0
T11	480714	1083	0	0
T12	0	832	0	0
T41	0	832	0	0