Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
3157 |
0 |
0 |
T61 |
2622 |
71 |
0 |
0 |
T62 |
3919 |
15 |
0 |
0 |
T63 |
5532 |
138 |
0 |
0 |
T79 |
54357 |
4 |
0 |
0 |
T80 |
51810 |
4 |
0 |
0 |
T81 |
10903 |
2 |
0 |
0 |
T82 |
2437 |
2 |
0 |
0 |
T83 |
8599 |
4 |
0 |
0 |
T86 |
9126 |
148 |
0 |
0 |
T94 |
4481 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1258 |
0 |
0 |
T71 |
4519 |
6 |
0 |
0 |
T72 |
1804 |
8 |
0 |
0 |
T95 |
9521 |
14 |
0 |
0 |
T99 |
7824 |
6 |
0 |
0 |
T104 |
4345 |
5 |
0 |
0 |
T132 |
6219 |
10 |
0 |
0 |
T133 |
7695 |
14 |
0 |
0 |
T134 |
19843 |
40 |
0 |
0 |
T135 |
9915 |
16 |
0 |
0 |
T136 |
33383 |
34 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1349 |
0 |
0 |
T71 |
4519 |
18 |
0 |
0 |
T95 |
9521 |
16 |
0 |
0 |
T99 |
7824 |
4 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
9 |
0 |
0 |
T132 |
6219 |
19 |
0 |
0 |
T133 |
7695 |
33 |
0 |
0 |
T134 |
19843 |
43 |
0 |
0 |
T135 |
9915 |
18 |
0 |
0 |
T136 |
33383 |
49 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1569 |
0 |
0 |
T71 |
4519 |
6 |
0 |
0 |
T95 |
9521 |
9 |
0 |
0 |
T99 |
7824 |
13 |
0 |
0 |
T103 |
3762 |
13 |
0 |
0 |
T104 |
4345 |
14 |
0 |
0 |
T132 |
6219 |
6 |
0 |
0 |
T133 |
7695 |
37 |
0 |
0 |
T134 |
19843 |
61 |
0 |
0 |
T135 |
9915 |
10 |
0 |
0 |
T136 |
33383 |
73 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
3747 |
0 |
0 |
T71 |
4519 |
20 |
0 |
0 |
T72 |
1804 |
7 |
0 |
0 |
T95 |
9521 |
13 |
0 |
0 |
T99 |
7824 |
281 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T132 |
6219 |
22 |
0 |
0 |
T133 |
7695 |
42 |
0 |
0 |
T134 |
19843 |
75 |
0 |
0 |
T135 |
9915 |
4 |
0 |
0 |
T136 |
33383 |
689 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4003 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
15 |
0 |
0 |
T99 |
7824 |
222 |
0 |
0 |
T132 |
6219 |
21 |
0 |
0 |
T133 |
7695 |
20 |
0 |
0 |
T134 |
19843 |
56 |
0 |
0 |
T135 |
9915 |
145 |
0 |
0 |
T136 |
33383 |
444 |
0 |
0 |
T137 |
4683 |
2 |
0 |
0 |
T138 |
19738 |
104 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4784 |
0 |
0 |
T71 |
4519 |
1 |
0 |
0 |
T95 |
9521 |
17 |
0 |
0 |
T99 |
7824 |
120 |
0 |
0 |
T103 |
3762 |
126 |
0 |
0 |
T104 |
4345 |
98 |
0 |
0 |
T132 |
6219 |
16 |
0 |
0 |
T133 |
7695 |
12 |
0 |
0 |
T134 |
19843 |
54 |
0 |
0 |
T135 |
9915 |
40 |
0 |
0 |
T136 |
33383 |
833 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4675 |
0 |
0 |
T71 |
4519 |
15 |
0 |
0 |
T72 |
1804 |
4 |
0 |
0 |
T95 |
9521 |
146 |
0 |
0 |
T99 |
7824 |
1 |
0 |
0 |
T103 |
3762 |
4 |
0 |
0 |
T132 |
6219 |
3 |
0 |
0 |
T133 |
7695 |
8 |
0 |
0 |
T134 |
19843 |
59 |
0 |
0 |
T135 |
9915 |
71 |
0 |
0 |
T136 |
33383 |
751 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
3602 |
0 |
0 |
T71 |
4519 |
17 |
0 |
0 |
T95 |
9521 |
129 |
0 |
0 |
T99 |
7824 |
154 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
123 |
0 |
0 |
T133 |
7695 |
14 |
0 |
0 |
T134 |
19843 |
92 |
0 |
0 |
T135 |
9915 |
80 |
0 |
0 |
T136 |
33383 |
338 |
0 |
0 |
T137 |
4683 |
6 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4355 |
0 |
0 |
T71 |
4519 |
16 |
0 |
0 |
T72 |
1804 |
5 |
0 |
0 |
T95 |
9521 |
251 |
0 |
0 |
T99 |
7824 |
9 |
0 |
0 |
T103 |
3762 |
124 |
0 |
0 |
T132 |
6219 |
23 |
0 |
0 |
T133 |
7695 |
25 |
0 |
0 |
T134 |
19843 |
35 |
0 |
0 |
T135 |
9915 |
122 |
0 |
0 |
T136 |
33383 |
824 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4166 |
0 |
0 |
T71 |
4519 |
7 |
0 |
0 |
T72 |
1804 |
1 |
0 |
0 |
T95 |
9521 |
12 |
0 |
0 |
T99 |
7824 |
131 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T132 |
6219 |
13 |
0 |
0 |
T133 |
7695 |
12 |
0 |
0 |
T134 |
19843 |
93 |
0 |
0 |
T135 |
9915 |
13 |
0 |
0 |
T136 |
33383 |
921 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
4123 |
0 |
0 |
T71 |
4519 |
18 |
0 |
0 |
T72 |
1804 |
7 |
0 |
0 |
T95 |
9521 |
212 |
0 |
0 |
T99 |
7824 |
274 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T132 |
6219 |
5 |
0 |
0 |
T133 |
7695 |
32 |
0 |
0 |
T134 |
19843 |
80 |
0 |
0 |
T135 |
9915 |
51 |
0 |
0 |
T136 |
33383 |
381 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2430 |
0 |
0 |
T71 |
4519 |
7 |
0 |
0 |
T95 |
9521 |
53 |
0 |
0 |
T99 |
7824 |
2 |
0 |
0 |
T103 |
3762 |
64 |
0 |
0 |
T104 |
4345 |
43 |
0 |
0 |
T132 |
6219 |
18 |
0 |
0 |
T133 |
7695 |
45 |
0 |
0 |
T134 |
19843 |
58 |
0 |
0 |
T135 |
9915 |
19 |
0 |
0 |
T136 |
33383 |
248 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2063 |
0 |
0 |
T71 |
4519 |
8 |
0 |
0 |
T72 |
1804 |
4 |
0 |
0 |
T95 |
9521 |
57 |
0 |
0 |
T99 |
7824 |
5 |
0 |
0 |
T103 |
3762 |
8 |
0 |
0 |
T104 |
4345 |
51 |
0 |
0 |
T132 |
6219 |
7 |
0 |
0 |
T134 |
19843 |
44 |
0 |
0 |
T135 |
9915 |
18 |
0 |
0 |
T136 |
33383 |
304 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2493 |
0 |
0 |
T71 |
4519 |
6 |
0 |
0 |
T95 |
9521 |
49 |
0 |
0 |
T99 |
7824 |
106 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T104 |
4345 |
2 |
0 |
0 |
T132 |
6219 |
1 |
0 |
0 |
T133 |
7695 |
44 |
0 |
0 |
T134 |
19843 |
95 |
0 |
0 |
T135 |
9915 |
60 |
0 |
0 |
T136 |
33383 |
121 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2356 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
11 |
0 |
0 |
T99 |
7824 |
3 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
50 |
0 |
0 |
T132 |
6219 |
20 |
0 |
0 |
T133 |
7695 |
53 |
0 |
0 |
T134 |
19843 |
91 |
0 |
0 |
T135 |
9915 |
29 |
0 |
0 |
T136 |
33383 |
327 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2543 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T72 |
1804 |
3 |
0 |
0 |
T95 |
9521 |
59 |
0 |
0 |
T99 |
7824 |
64 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T132 |
6219 |
37 |
0 |
0 |
T133 |
7695 |
36 |
0 |
0 |
T134 |
19843 |
38 |
0 |
0 |
T135 |
9915 |
30 |
0 |
0 |
T136 |
33383 |
278 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2559 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T72 |
1804 |
3 |
0 |
0 |
T95 |
9521 |
63 |
0 |
0 |
T99 |
7824 |
8 |
0 |
0 |
T103 |
3762 |
51 |
0 |
0 |
T132 |
6219 |
4 |
0 |
0 |
T133 |
7695 |
26 |
0 |
0 |
T134 |
19843 |
64 |
0 |
0 |
T135 |
9915 |
23 |
0 |
0 |
T136 |
33383 |
204 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2540 |
0 |
0 |
T71 |
4519 |
13 |
0 |
0 |
T72 |
1804 |
7 |
0 |
0 |
T95 |
9521 |
46 |
0 |
0 |
T99 |
7824 |
36 |
0 |
0 |
T103 |
3762 |
27 |
0 |
0 |
T104 |
4345 |
1 |
0 |
0 |
T133 |
7695 |
28 |
0 |
0 |
T134 |
19843 |
60 |
0 |
0 |
T135 |
9915 |
27 |
0 |
0 |
T136 |
33383 |
327 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2048 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T72 |
1804 |
3 |
0 |
0 |
T95 |
9521 |
48 |
0 |
0 |
T99 |
7824 |
99 |
0 |
0 |
T103 |
3762 |
38 |
0 |
0 |
T132 |
6219 |
9 |
0 |
0 |
T133 |
7695 |
16 |
0 |
0 |
T134 |
19843 |
65 |
0 |
0 |
T135 |
9915 |
31 |
0 |
0 |
T136 |
33383 |
126 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2413 |
0 |
0 |
T71 |
4519 |
20 |
0 |
0 |
T72 |
1804 |
1 |
0 |
0 |
T95 |
9521 |
71 |
0 |
0 |
T99 |
7824 |
9 |
0 |
0 |
T104 |
4345 |
40 |
0 |
0 |
T132 |
6219 |
19 |
0 |
0 |
T133 |
7695 |
7 |
0 |
0 |
T134 |
19843 |
49 |
0 |
0 |
T135 |
9915 |
12 |
0 |
0 |
T136 |
33383 |
233 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2481 |
0 |
0 |
T71 |
4519 |
10 |
0 |
0 |
T72 |
1804 |
2 |
0 |
0 |
T95 |
9521 |
75 |
0 |
0 |
T99 |
7824 |
30 |
0 |
0 |
T103 |
3762 |
46 |
0 |
0 |
T132 |
6219 |
21 |
0 |
0 |
T133 |
7695 |
61 |
0 |
0 |
T134 |
19843 |
90 |
0 |
0 |
T135 |
9915 |
31 |
0 |
0 |
T136 |
33383 |
260 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2666 |
0 |
0 |
T71 |
4519 |
15 |
0 |
0 |
T72 |
1804 |
4 |
0 |
0 |
T95 |
9521 |
99 |
0 |
0 |
T99 |
7824 |
53 |
0 |
0 |
T103 |
3762 |
47 |
0 |
0 |
T104 |
4345 |
24 |
0 |
0 |
T133 |
7695 |
10 |
0 |
0 |
T134 |
19843 |
63 |
0 |
0 |
T135 |
9915 |
26 |
0 |
0 |
T136 |
33383 |
263 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2455 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
75 |
0 |
0 |
T99 |
7824 |
90 |
0 |
0 |
T103 |
3762 |
4 |
0 |
0 |
T104 |
4345 |
42 |
0 |
0 |
T132 |
6219 |
3 |
0 |
0 |
T133 |
7695 |
30 |
0 |
0 |
T134 |
19843 |
56 |
0 |
0 |
T135 |
9915 |
49 |
0 |
0 |
T136 |
33383 |
315 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2358 |
0 |
0 |
T71 |
4519 |
4 |
0 |
0 |
T95 |
9521 |
14 |
0 |
0 |
T99 |
7824 |
48 |
0 |
0 |
T103 |
3762 |
38 |
0 |
0 |
T104 |
4345 |
54 |
0 |
0 |
T132 |
6219 |
8 |
0 |
0 |
T133 |
7695 |
7 |
0 |
0 |
T134 |
19843 |
90 |
0 |
0 |
T135 |
9915 |
54 |
0 |
0 |
T136 |
33383 |
264 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2695 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
9 |
0 |
0 |
T99 |
7824 |
66 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
41 |
0 |
0 |
T132 |
6219 |
16 |
0 |
0 |
T133 |
7695 |
29 |
0 |
0 |
T134 |
19843 |
77 |
0 |
0 |
T135 |
9915 |
77 |
0 |
0 |
T136 |
33383 |
341 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2329 |
0 |
0 |
T71 |
4519 |
4 |
0 |
0 |
T72 |
1804 |
6 |
0 |
0 |
T95 |
9521 |
50 |
0 |
0 |
T99 |
7824 |
35 |
0 |
0 |
T103 |
3762 |
59 |
0 |
0 |
T132 |
6219 |
3 |
0 |
0 |
T133 |
7695 |
22 |
0 |
0 |
T134 |
19843 |
68 |
0 |
0 |
T135 |
9915 |
34 |
0 |
0 |
T136 |
33383 |
368 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2593 |
0 |
0 |
T71 |
4519 |
14 |
0 |
0 |
T95 |
9521 |
59 |
0 |
0 |
T99 |
7824 |
59 |
0 |
0 |
T103 |
3762 |
44 |
0 |
0 |
T104 |
4345 |
59 |
0 |
0 |
T132 |
6219 |
10 |
0 |
0 |
T133 |
7695 |
8 |
0 |
0 |
T134 |
19843 |
41 |
0 |
0 |
T135 |
9915 |
24 |
0 |
0 |
T136 |
33383 |
234 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2098 |
0 |
0 |
T71 |
4519 |
15 |
0 |
0 |
T72 |
1804 |
1 |
0 |
0 |
T95 |
9521 |
18 |
0 |
0 |
T99 |
7824 |
35 |
0 |
0 |
T103 |
3762 |
36 |
0 |
0 |
T132 |
6219 |
23 |
0 |
0 |
T133 |
7695 |
32 |
0 |
0 |
T134 |
19843 |
51 |
0 |
0 |
T135 |
9915 |
31 |
0 |
0 |
T136 |
33383 |
60 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2583 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T95 |
9521 |
60 |
0 |
0 |
T99 |
7824 |
46 |
0 |
0 |
T103 |
3762 |
55 |
0 |
0 |
T104 |
4345 |
1 |
0 |
0 |
T133 |
7695 |
2 |
0 |
0 |
T134 |
19843 |
52 |
0 |
0 |
T135 |
9915 |
27 |
0 |
0 |
T136 |
33383 |
210 |
0 |
0 |
T137 |
4683 |
57 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2196 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T95 |
9521 |
57 |
0 |
0 |
T99 |
7824 |
54 |
0 |
0 |
T103 |
3762 |
5 |
0 |
0 |
T104 |
4345 |
41 |
0 |
0 |
T132 |
6219 |
19 |
0 |
0 |
T133 |
7695 |
48 |
0 |
0 |
T134 |
19843 |
62 |
0 |
0 |
T135 |
9915 |
25 |
0 |
0 |
T136 |
33383 |
177 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2210 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T72 |
1804 |
3 |
0 |
0 |
T95 |
9521 |
46 |
0 |
0 |
T99 |
7824 |
62 |
0 |
0 |
T103 |
3762 |
37 |
0 |
0 |
T104 |
4345 |
4 |
0 |
0 |
T133 |
7695 |
8 |
0 |
0 |
T134 |
19843 |
54 |
0 |
0 |
T135 |
9915 |
7 |
0 |
0 |
T136 |
33383 |
317 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2124 |
0 |
0 |
T71 |
4519 |
8 |
0 |
0 |
T72 |
1804 |
2 |
0 |
0 |
T95 |
9521 |
5 |
0 |
0 |
T99 |
7824 |
92 |
0 |
0 |
T103 |
3762 |
8 |
0 |
0 |
T132 |
6219 |
3 |
0 |
0 |
T133 |
7695 |
15 |
0 |
0 |
T134 |
19843 |
89 |
0 |
0 |
T135 |
9915 |
25 |
0 |
0 |
T136 |
33383 |
232 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2535 |
0 |
0 |
T71 |
4519 |
11 |
0 |
0 |
T72 |
1804 |
2 |
0 |
0 |
T95 |
9521 |
71 |
0 |
0 |
T99 |
7824 |
44 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T132 |
6219 |
10 |
0 |
0 |
T133 |
7695 |
30 |
0 |
0 |
T134 |
19843 |
60 |
0 |
0 |
T135 |
9915 |
27 |
0 |
0 |
T136 |
33383 |
346 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2319 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
92 |
0 |
0 |
T99 |
7824 |
39 |
0 |
0 |
T104 |
4345 |
8 |
0 |
0 |
T132 |
6219 |
21 |
0 |
0 |
T133 |
7695 |
20 |
0 |
0 |
T134 |
19843 |
27 |
0 |
0 |
T135 |
9915 |
32 |
0 |
0 |
T136 |
33383 |
361 |
0 |
0 |
T137 |
4683 |
31 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2544 |
0 |
0 |
T71 |
4519 |
10 |
0 |
0 |
T95 |
9521 |
57 |
0 |
0 |
T99 |
7824 |
86 |
0 |
0 |
T103 |
3762 |
55 |
0 |
0 |
T104 |
4345 |
49 |
0 |
0 |
T132 |
6219 |
15 |
0 |
0 |
T133 |
7695 |
33 |
0 |
0 |
T134 |
19843 |
102 |
0 |
0 |
T135 |
9915 |
18 |
0 |
0 |
T136 |
33383 |
242 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1401 |
0 |
0 |
T71 |
4519 |
17 |
0 |
0 |
T72 |
1804 |
6 |
0 |
0 |
T95 |
9521 |
12 |
0 |
0 |
T99 |
7824 |
15 |
0 |
0 |
T104 |
4345 |
1 |
0 |
0 |
T132 |
6219 |
16 |
0 |
0 |
T133 |
7695 |
28 |
0 |
0 |
T134 |
19843 |
45 |
0 |
0 |
T135 |
9915 |
6 |
0 |
0 |
T136 |
33383 |
41 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1477 |
0 |
0 |
T71 |
4519 |
1 |
0 |
0 |
T95 |
9521 |
29 |
0 |
0 |
T99 |
7824 |
8 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
8 |
0 |
0 |
T132 |
6219 |
7 |
0 |
0 |
T133 |
7695 |
33 |
0 |
0 |
T134 |
19843 |
50 |
0 |
0 |
T135 |
9915 |
12 |
0 |
0 |
T136 |
33383 |
57 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1262 |
0 |
0 |
T71 |
4519 |
17 |
0 |
0 |
T95 |
9521 |
9 |
0 |
0 |
T99 |
7824 |
13 |
0 |
0 |
T103 |
3762 |
5 |
0 |
0 |
T104 |
4345 |
10 |
0 |
0 |
T132 |
6219 |
8 |
0 |
0 |
T133 |
7695 |
12 |
0 |
0 |
T134 |
19843 |
27 |
0 |
0 |
T135 |
9915 |
8 |
0 |
0 |
T136 |
33383 |
40 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1269 |
0 |
0 |
T71 |
4519 |
5 |
0 |
0 |
T95 |
9521 |
14 |
0 |
0 |
T99 |
7824 |
6 |
0 |
0 |
T103 |
3762 |
7 |
0 |
0 |
T104 |
4345 |
8 |
0 |
0 |
T133 |
7695 |
12 |
0 |
0 |
T134 |
19843 |
37 |
0 |
0 |
T135 |
9915 |
12 |
0 |
0 |
T136 |
33383 |
80 |
0 |
0 |
T137 |
4683 |
11 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1538 |
0 |
0 |
T71 |
4519 |
23 |
0 |
0 |
T72 |
1804 |
3 |
0 |
0 |
T95 |
9521 |
23 |
0 |
0 |
T99 |
7824 |
1 |
0 |
0 |
T103 |
3762 |
28 |
0 |
0 |
T132 |
6219 |
5 |
0 |
0 |
T133 |
7695 |
14 |
0 |
0 |
T134 |
19843 |
71 |
0 |
0 |
T135 |
9915 |
13 |
0 |
0 |
T136 |
33383 |
94 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
2939 |
0 |
0 |
T21 |
206443 |
33 |
0 |
0 |
T32 |
0 |
46 |
0 |
0 |
T33 |
0 |
25 |
0 |
0 |
T46 |
228835 |
0 |
0 |
0 |
T58 |
9742 |
0 |
0 |
0 |
T59 |
212720 |
0 |
0 |
0 |
T69 |
737201 |
0 |
0 |
0 |
T78 |
38517 |
0 |
0 |
0 |
T125 |
63195 |
0 |
0 |
0 |
T139 |
0 |
14 |
0 |
0 |
T140 |
0 |
23 |
0 |
0 |
T141 |
0 |
17 |
0 |
0 |
T142 |
0 |
49 |
0 |
0 |
T143 |
0 |
5 |
0 |
0 |
T144 |
0 |
7 |
0 |
0 |
T145 |
0 |
52 |
0 |
0 |
T146 |
35129 |
0 |
0 |
0 |
T147 |
1257 |
0 |
0 |
0 |
T148 |
26265 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1425 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T95 |
9521 |
15 |
0 |
0 |
T99 |
7824 |
9 |
0 |
0 |
T103 |
3762 |
6 |
0 |
0 |
T104 |
4345 |
11 |
0 |
0 |
T132 |
6219 |
6 |
0 |
0 |
T133 |
7695 |
22 |
0 |
0 |
T134 |
19843 |
57 |
0 |
0 |
T135 |
9915 |
11 |
0 |
0 |
T136 |
33383 |
45 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1495 |
0 |
0 |
T71 |
4519 |
24 |
0 |
0 |
T95 |
9521 |
17 |
0 |
0 |
T99 |
7824 |
19 |
0 |
0 |
T103 |
3762 |
1 |
0 |
0 |
T104 |
4345 |
7 |
0 |
0 |
T132 |
6219 |
13 |
0 |
0 |
T133 |
7695 |
24 |
0 |
0 |
T134 |
19843 |
30 |
0 |
0 |
T135 |
9915 |
18 |
0 |
0 |
T136 |
33383 |
68 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1234 |
0 |
0 |
T71 |
4519 |
14 |
0 |
0 |
T95 |
9521 |
9 |
0 |
0 |
T99 |
7824 |
8 |
0 |
0 |
T103 |
3762 |
2 |
0 |
0 |
T104 |
4345 |
6 |
0 |
0 |
T132 |
6219 |
8 |
0 |
0 |
T134 |
19843 |
51 |
0 |
0 |
T135 |
9915 |
11 |
0 |
0 |
T136 |
33383 |
42 |
0 |
0 |
T137 |
4683 |
2 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1261 |
0 |
0 |
T71 |
4519 |
12 |
0 |
0 |
T95 |
9521 |
8 |
0 |
0 |
T99 |
7824 |
12 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T132 |
6219 |
12 |
0 |
0 |
T133 |
7695 |
8 |
0 |
0 |
T134 |
19843 |
38 |
0 |
0 |
T135 |
9915 |
4 |
0 |
0 |
T136 |
33383 |
41 |
0 |
0 |
T138 |
19738 |
59 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1336 |
0 |
0 |
T71 |
4519 |
9 |
0 |
0 |
T95 |
9521 |
16 |
0 |
0 |
T99 |
7824 |
10 |
0 |
0 |
T103 |
3762 |
6 |
0 |
0 |
T104 |
4345 |
3 |
0 |
0 |
T132 |
6219 |
26 |
0 |
0 |
T133 |
7695 |
46 |
0 |
0 |
T134 |
19843 |
50 |
0 |
0 |
T135 |
9915 |
13 |
0 |
0 |
T136 |
33383 |
25 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1382 |
0 |
0 |
T71 |
4519 |
5 |
0 |
0 |
T95 |
9521 |
12 |
0 |
0 |
T99 |
7824 |
7 |
0 |
0 |
T103 |
3762 |
5 |
0 |
0 |
T132 |
6219 |
8 |
0 |
0 |
T133 |
7695 |
26 |
0 |
0 |
T134 |
19843 |
62 |
0 |
0 |
T135 |
9915 |
6 |
0 |
0 |
T136 |
33383 |
30 |
0 |
0 |
T138 |
19738 |
77 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1457 |
0 |
0 |
T71 |
4519 |
5 |
0 |
0 |
T95 |
9521 |
5 |
0 |
0 |
T99 |
7824 |
20 |
0 |
0 |
T103 |
3762 |
9 |
0 |
0 |
T104 |
4345 |
14 |
0 |
0 |
T132 |
6219 |
36 |
0 |
0 |
T133 |
7695 |
6 |
0 |
0 |
T134 |
19843 |
52 |
0 |
0 |
T135 |
9915 |
27 |
0 |
0 |
T136 |
33383 |
83 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1311 |
0 |
0 |
T71 |
4519 |
6 |
0 |
0 |
T72 |
1804 |
2 |
0 |
0 |
T95 |
9521 |
7 |
0 |
0 |
T99 |
7824 |
9 |
0 |
0 |
T104 |
4345 |
9 |
0 |
0 |
T132 |
6219 |
29 |
0 |
0 |
T133 |
7695 |
5 |
0 |
0 |
T134 |
19843 |
47 |
0 |
0 |
T135 |
9915 |
15 |
0 |
0 |
T136 |
33383 |
36 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1481 |
0 |
0 |
T71 |
4519 |
7 |
0 |
0 |
T95 |
9521 |
21 |
0 |
0 |
T99 |
7824 |
22 |
0 |
0 |
T103 |
3762 |
4 |
0 |
0 |
T104 |
4345 |
14 |
0 |
0 |
T132 |
6219 |
2 |
0 |
0 |
T133 |
7695 |
8 |
0 |
0 |
T134 |
19843 |
55 |
0 |
0 |
T135 |
9915 |
19 |
0 |
0 |
T136 |
33383 |
99 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1361 |
0 |
0 |
T71 |
4519 |
14 |
0 |
0 |
T95 |
9521 |
10 |
0 |
0 |
T99 |
7824 |
6 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T104 |
4345 |
7 |
0 |
0 |
T132 |
6219 |
31 |
0 |
0 |
T133 |
7695 |
44 |
0 |
0 |
T134 |
19843 |
56 |
0 |
0 |
T136 |
33383 |
48 |
0 |
0 |
T137 |
4683 |
4 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1394 |
0 |
0 |
T71 |
4519 |
13 |
0 |
0 |
T72 |
1804 |
1 |
0 |
0 |
T95 |
9521 |
9 |
0 |
0 |
T99 |
7824 |
6 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T132 |
6219 |
24 |
0 |
0 |
T133 |
7695 |
39 |
0 |
0 |
T134 |
19843 |
53 |
0 |
0 |
T136 |
33383 |
27 |
0 |
0 |
T137 |
4683 |
7 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1167 |
0 |
0 |
T71 |
4519 |
8 |
0 |
0 |
T72 |
1804 |
7 |
0 |
0 |
T95 |
9521 |
12 |
0 |
0 |
T99 |
7824 |
6 |
0 |
0 |
T103 |
3762 |
7 |
0 |
0 |
T132 |
6219 |
12 |
0 |
0 |
T133 |
7695 |
16 |
0 |
0 |
T134 |
19843 |
94 |
0 |
0 |
T135 |
9915 |
8 |
0 |
0 |
T136 |
33383 |
27 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1312 |
0 |
0 |
T71 |
4519 |
13 |
0 |
0 |
T95 |
9521 |
21 |
0 |
0 |
T99 |
7824 |
7 |
0 |
0 |
T103 |
3762 |
1 |
0 |
0 |
T104 |
4345 |
8 |
0 |
0 |
T132 |
6219 |
24 |
0 |
0 |
T134 |
19843 |
79 |
0 |
0 |
T135 |
9915 |
14 |
0 |
0 |
T136 |
33383 |
35 |
0 |
0 |
T137 |
4683 |
6 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1298 |
0 |
0 |
T71 |
4519 |
14 |
0 |
0 |
T95 |
9521 |
8 |
0 |
0 |
T99 |
7824 |
7 |
0 |
0 |
T103 |
3762 |
3 |
0 |
0 |
T104 |
4345 |
2 |
0 |
0 |
T132 |
6219 |
19 |
0 |
0 |
T133 |
7695 |
2 |
0 |
0 |
T134 |
19843 |
81 |
0 |
0 |
T135 |
9915 |
10 |
0 |
0 |
T136 |
33383 |
27 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1334 |
0 |
0 |
T71 |
4519 |
3 |
0 |
0 |
T95 |
9521 |
6 |
0 |
0 |
T99 |
7824 |
5 |
0 |
0 |
T103 |
3762 |
4 |
0 |
0 |
T104 |
4345 |
7 |
0 |
0 |
T132 |
6219 |
19 |
0 |
0 |
T133 |
7695 |
24 |
0 |
0 |
T134 |
19843 |
42 |
0 |
0 |
T135 |
9915 |
7 |
0 |
0 |
T136 |
33383 |
22 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
469967919 |
1277 |
0 |
0 |
T71 |
4519 |
8 |
0 |
0 |
T95 |
9521 |
15 |
0 |
0 |
T99 |
7824 |
10 |
0 |
0 |
T103 |
3762 |
6 |
0 |
0 |
T104 |
4345 |
2 |
0 |
0 |
T132 |
6219 |
10 |
0 |
0 |
T133 |
7695 |
21 |
0 |
0 |
T134 |
19843 |
73 |
0 |
0 |
T135 |
9915 |
8 |
0 |
0 |
T136 |
33383 |
39 |
0 |
0 |