Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3403342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4163593

1

T1

2514

T2

956

T3

1440

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4104565	1			T1	8660		T2	153		T3	1155
values[0x0]	1730427	1			T1	1262		T2	426		T3	468
values[0x1]	1731943	1			T1	1258		T2	451		T3	424

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2416452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5150483

1

T1

5240

T2

972

T3

1562

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29262	1			T1	49		T2	5		T5	57
valid_sources[0x01]	30567	1			T1	57		T2	3		T5	67
valid_sources[0x02]	28024	1			T1	40		T2	3		T5	66
valid_sources[0x03]	31745	1			T1	43		T2	10		T5	48
valid_sources[0x04]	27048	1			T1	50		T2	3		T5	68
valid_sources[0x05]	36165	1			T1	31		T2	5		T5	60
valid_sources[0x06]	30041	1			T1	42		T2	5		T5	58
valid_sources[0x07]	28473	1			T1	48		T2	1		T5	62
valid_sources[0x08]	25672	1			T1	48		T2	2		T5	59
valid_sources[0x09]	27434	1			T1	51		T2	1		T5	54
valid_sources[0x0a]	24337	1			T1	36		T2	7		T5	73
valid_sources[0x0b]	30910	1			T1	44		T2	1		T5	45
valid_sources[0x0c]	29702	1			T1	36		T2	4		T5	56
valid_sources[0x0d]	31662	1			T1	49		T2	2		T5	70
valid_sources[0x0e]	28126	1			T1	25		T2	7		T5	77
valid_sources[0x0f]	26831	1			T1	46		T2	1		T5	67
valid_sources[0x10]	28115	1			T1	46		T2	5		T5	64
valid_sources[0x11]	33494	1			T1	59		T5	57		T6	125
valid_sources[0x12]	31507	1			T1	44		T2	3		T5	64
valid_sources[0x13]	31413	1			T1	48		T2	4		T5	53
valid_sources[0x14]	31226	1			T1	35		T2	1		T5	63
valid_sources[0x15]	29065	1			T1	45		T2	11		T5	55
valid_sources[0x16]	28618	1			T1	46		T2	2		T5	63
valid_sources[0x17]	51653	1			T1	61		T2	1		T5	58
valid_sources[0x18]	27841	1			T1	32		T2	6		T5	71
valid_sources[0x19]	28289	1			T1	46		T2	8		T5	75
valid_sources[0x1a]	34024	1			T1	36		T2	5		T5	70
valid_sources[0x1b]	28202	1			T1	39		T2	6		T4	14
valid_sources[0x1c]	27270	1			T1	48		T2	3		T5	57
valid_sources[0x1d]	30794	1			T1	38		T2	5		T5	58
valid_sources[0x1e]	26395	1			T1	48		T2	5		T5	61
valid_sources[0x1f]	30422	1			T1	33		T2	3		T4	4
valid_sources[0x20]	34863	1			T1	26		T2	5		T5	64
valid_sources[0x21]	26561	1			T1	46		T2	6		T5	65
valid_sources[0x22]	26585	1			T1	65		T2	2		T5	67
valid_sources[0x23]	26260	1			T1	37		T2	5		T5	72
valid_sources[0x24]	25100	1			T1	48		T2	4		T5	73
valid_sources[0x25]	30547	1			T1	42		T2	2		T5	62
valid_sources[0x26]	28504	1			T1	41		T2	1		T5	61
valid_sources[0x27]	27294	1			T1	35		T2	2		T5	53
valid_sources[0x28]	54138	1			T1	50		T2	9		T5	58
valid_sources[0x29]	55624	1			T1	50		T2	4		T5	69
valid_sources[0x2a]	27679	1			T1	39		T2	6		T5	53
valid_sources[0x2b]	26175	1			T1	56		T2	1		T5	71
valid_sources[0x2c]	31907	1			T1	43		T2	6		T5	60
valid_sources[0x2d]	26870	1			T1	53		T2	7		T5	51
valid_sources[0x2e]	27829	1			T1	46		T2	7		T5	67
valid_sources[0x2f]	27167	1			T1	37		T2	5		T5	58
valid_sources[0x30]	27627	1			T1	36		T2	9		T5	63
valid_sources[0x31]	35469	1			T1	49		T2	2		T5	57
valid_sources[0x32]	26948	1			T1	51		T2	4		T5	53
valid_sources[0x33]	28536	1			T1	41		T2	7		T5	58
valid_sources[0x34]	27410	1			T1	34		T2	3		T5	63
valid_sources[0x35]	27282	1			T1	35		T2	4		T5	56
valid_sources[0x36]	29863	1			T1	38		T2	3		T5	46
valid_sources[0x37]	30157	1			T1	38		T2	8		T5	52
valid_sources[0x38]	27522	1			T1	38		T2	6		T5	71
valid_sources[0x39]	38064	1			T1	43		T2	4		T5	64
valid_sources[0x3a]	28796	1			T1	52		T2	1		T5	55
valid_sources[0x3b]	25981	1			T1	61		T2	4		T5	67
valid_sources[0x3c]	28290	1			T1	44		T2	3		T5	70
valid_sources[0x3d]	27598	1			T1	48		T2	6		T5	60
valid_sources[0x3e]	29368	1			T1	41		T2	4		T5	60
valid_sources[0x3f]	29673	1			T1	45		T2	1		T5	52
valid_sources[0x40]	59390	1			T1	36		T2	3		T5	70
valid_sources[0x41]	26356	1			T1	40		T2	2		T5	66
valid_sources[0x42]	27155	1			T1	43		T2	2		T5	77
valid_sources[0x43]	30855	1			T1	48		T2	2		T5	62
valid_sources[0x44]	26809	1			T1	35		T2	4		T5	57
valid_sources[0x45]	26994	1			T1	36		T2	1		T5	57
valid_sources[0x46]	26591	1			T1	48		T2	10		T5	81
valid_sources[0x47]	30316	1			T1	46		T2	3		T5	51
valid_sources[0x48]	29776	1			T1	31		T2	4		T5	69
valid_sources[0x49]	28895	1			T1	46		T2	9		T5	64
valid_sources[0x4a]	29906	1			T1	46		T2	4		T5	70
valid_sources[0x4b]	26433	1			T1	31		T2	5		T5	59
valid_sources[0x4c]	29784	1			T1	39		T2	4		T3	1222
valid_sources[0x4d]	29588	1			T1	57		T2	6		T5	66
valid_sources[0x4e]	31119	1			T1	46		T2	8		T4	7
valid_sources[0x4f]	27534	1			T1	53		T2	5		T5	62
valid_sources[0x50]	26834	1			T1	42		T2	3		T5	59
valid_sources[0x51]	32479	1			T1	47		T2	6		T5	64
valid_sources[0x52]	30479	1			T1	35		T2	3		T5	61
valid_sources[0x53]	29360	1			T1	48		T2	6		T5	53
valid_sources[0x54]	31050	1			T1	52		T2	6		T5	72
valid_sources[0x55]	30805	1			T1	37		T2	7		T5	67
valid_sources[0x56]	30394	1			T1	57		T2	3		T5	59
valid_sources[0x57]	27589	1			T1	47		T2	2		T5	59
valid_sources[0x58]	26701	1			T1	38		T2	7		T5	57
valid_sources[0x59]	26587	1			T1	55		T4	1		T5	45
valid_sources[0x5a]	27406	1			T1	60		T2	3		T5	64
valid_sources[0x5b]	28143	1			T1	54		T2	4		T5	46
valid_sources[0x5c]	32797	1			T1	43		T2	5		T3	452
valid_sources[0x5d]	26661	1			T1	42		T2	3		T5	56
valid_sources[0x5e]	30407	1			T1	41		T2	3		T5	51
valid_sources[0x5f]	31997	1			T1	47		T2	2		T5	60
valid_sources[0x60]	30327	1			T1	55		T2	2		T5	65
valid_sources[0x61]	30361	1			T1	35		T2	2		T5	63
valid_sources[0x62]	27881	1			T1	37		T2	6		T5	53
valid_sources[0x63]	32176	1			T1	60		T2	1		T5	55
valid_sources[0x64]	27691	1			T1	37		T2	1		T4	2
valid_sources[0x65]	27371	1			T1	29		T2	6		T5	55
valid_sources[0x66]	27671	1			T1	45		T2	4		T5	69
valid_sources[0x67]	28207	1			T1	45		T2	3		T5	49
valid_sources[0x68]	27044	1			T1	43		T2	9		T5	62
valid_sources[0x69]	30073	1			T1	45		T2	6		T5	65
valid_sources[0x6a]	30087	1			T1	36		T2	5		T5	54
valid_sources[0x6b]	29869	1			T1	43		T2	3		T5	69
valid_sources[0x6c]	29571	1			T1	48		T2	3		T5	70
valid_sources[0x6d]	36060	1			T1	59		T2	4		T5	58
valid_sources[0x6e]	31708	1			T1	44		T2	4		T5	79
valid_sources[0x6f]	31896	1			T1	35		T2	4		T5	67
valid_sources[0x70]	32131	1			T1	33		T2	6		T5	49
valid_sources[0x71]	27394	1			T1	32		T2	6		T5	52
valid_sources[0x72]	31537	1			T1	59		T2	4		T5	56
valid_sources[0x73]	29187	1			T1	50		T2	4		T5	61
valid_sources[0x74]	27376	1			T1	42		T2	2		T4	2
valid_sources[0x75]	29237	1			T1	61		T2	5		T5	76
valid_sources[0x76]	31142	1			T1	52		T2	6		T5	75
valid_sources[0x77]	26779	1			T1	35		T2	4		T5	74
valid_sources[0x78]	28852	1			T1	31		T2	4		T5	63
valid_sources[0x79]	30424	1			T1	56		T2	3		T5	59
valid_sources[0x7a]	27611	1			T1	67		T2	2		T5	61
valid_sources[0x7b]	27338	1			T1	41		T2	5		T5	43
valid_sources[0x7c]	26368	1			T1	55		T2	2		T5	77
valid_sources[0x7d]	27844	1			T1	61		T2	5		T5	50
valid_sources[0x7e]	29888	1			T1	30		T2	6		T5	46
valid_sources[0x7f]	27980	1			T1	44		T2	6		T5	50
valid_sources[0x80]	31380	1			T1	48		T2	4		T5	62

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018033

1

T1

577

T2

82

T3

551

values[0x0]

all_enables

biggest_size

1584707

1

T1

991

T2

424

T3

467

values[0x1]

all_enables

biggest_size

1560853

1

T1

946

T2

450

T3

422