Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3425901

1

T1

8666

T2

74

T3

607

full_word

4164859

1

T1

2514

T2

956

T3

1440

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7590340	1			T1	11180		T2	1030		T3	2047
auto[TlIntgErrCmd]	134	1			T67	2		T101	13		T102	9
auto[TlIntgErrData]	114	1			T67	11		T101	4		T102	9
auto[TlIntgErrBoth]	172	1			T67	7		T101	13		T102	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4109428

1

T1

8660

T2

153

T3

1155

auto[1]

3481332

1

T1

2520

T2

877

T3

892

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3090893	1			T1	8083		T2	71		T3	604
auto[TlIntgErrNone]	partial	auto[1]	334627	1			T1	583		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1018364	1			T1	577		T2	82		T3	551
auto[TlIntgErrNone]	full_word	auto[1]	3146456	1			T1	1937		T2	874		T3	889
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T67	2		T101	6		T102	2
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T101	5		T102	6		T176	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T101	1		T177	2		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T101	1		T102	1		T114	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T67	2		T101	1		T102	7
auto[TlIntgErrData]	partial	auto[1]	51	1			T67	6		T101	3		T102	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T67	2		T179	1		T180	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T67	1		T181	1		T177	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T101	7		T102	2		T176	2
auto[TlIntgErrBoth]	partial	auto[1]	103	1			T67	7		T101	4		T102	8
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T101	1		T102	1		T114	3
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T101	1		T102	1		T182	1