Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	606002821	3314126	0	0
gen_wmask[1].MaskCheckPortA_A	606002821	3314126	0	0
gen_wmask[2].MaskCheckPortA_A	606002821	3314126	0	0
gen_wmask[3].MaskCheckPortA_A	606002821	3314126	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606002821	3314126	0	0
T1	738666	2780	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	681612	21278	0	0
T6	390046	6554	0	0
T7	60615	832	0	0
T8	493944	4832	0	0
T9	526629	4460	0	0
T10	315641	832	0	0
T11	0	16277	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606002821	3314126	0	0
T1	738666	2780	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	681612	21278	0	0
T6	390046	6554	0	0
T7	60615	832	0	0
T8	493944	4832	0	0
T9	526629	4460	0	0
T10	315641	832	0	0
T11	0	16277	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606002821	3314126	0	0
T1	738666	2780	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	681612	21278	0	0
T6	390046	6554	0	0
T7	60615	832	0	0
T8	493944	4832	0	0
T9	526629	4460	0	0
T10	315641	832	0	0
T11	0	16277	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606002821	3314126	0	0
T1	738666	2780	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	681612	21278	0	0
T6	390046	6554	0	0
T7	60615	832	0	0
T8	493944	4832	0	0
T9	526629	4460	0	0
T10	315641	832	0	0
T11	0	16277	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	456084574	2091403	0	0
gen_wmask[1].MaskCheckPortA_A	456084574	2091403	0	0
gen_wmask[2].MaskCheckPortA_A	456084574	2091403	0	0
gen_wmask[3].MaskCheckPortA_A	456084574	2091403	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2091403	0	0
T1	658250	998	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	11648	0	0
T6	132253	4684	0	0
T7	47909	832	0	0
T8	291497	2000	0	0
T9	276359	3328	0	0
T10	118715	832	0	0
T11	0	10503	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2091403	0	0
T1	658250	998	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	11648	0	0
T6	132253	4684	0	0
T7	47909	832	0	0
T8	291497	2000	0	0
T9	276359	3328	0	0
T10	118715	832	0	0
T11	0	10503	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2091403	0	0
T1	658250	998	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	11648	0	0
T6	132253	4684	0	0
T7	47909	832	0	0
T8	291497	2000	0	0
T9	276359	3328	0	0
T10	118715	832	0	0
T11	0	10503	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2091403	0	0
T1	658250	998	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	11648	0	0
T6	132253	4684	0	0
T7	47909	832	0	0
T8	291497	2000	0	0
T9	276359	3328	0	0
T10	118715	832	0	0
T11	0	10503	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	149918247	1222723	0	0
gen_wmask[1].MaskCheckPortA_A	149918247	1222723	0	0
gen_wmask[2].MaskCheckPortA_A	149918247	1222723	0	0
gen_wmask[3].MaskCheckPortA_A	149918247	1222723	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	1222723	0	0
T1	80416	1782	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	9630	0	0
T6	257793	1870	0	0
T7	12706	0	0	0
T8	202447	2832	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	0	5774	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	1222723	0	0
T1	80416	1782	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	9630	0	0
T6	257793	1870	0	0
T7	12706	0	0	0
T8	202447	2832	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	0	5774	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	1222723	0	0
T1	80416	1782	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	9630	0	0
T6	257793	1870	0	0
T7	12706	0	0	0
T8	202447	2832	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	0	5774	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	1222723	0	0
T1	80416	1782	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	9630	0	0
T6	257793	1870	0	0
T7	12706	0	0	0
T8	202447	2832	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	0	5774	0	0
T12	0	10367	0	0
T23	0	2	0	0
T28	0	11755	0	0
T31	0	401	0	0