Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	2903279	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	2903279	0	0
T2	5247	1663	0	0
T3	47008	1668	0	0
T4	3759	0	0	0
T5	123490	15803	0	0
T6	132253	6659	0	0
T7	47909	832	0	0
T8	291497	832	0	0
T9	276359	4996	0	0
T10	118715	1663	0	0
T11	372750	13307	0	0
T12	0	16630	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	3096885	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	3096885	0	0
T2	5247	832	0	0
T3	47008	837	0	0
T4	3759	0	0	0
T5	123490	11648	0	0
T6	132253	7116	0	0
T7	47909	2553	0	0
T8	291497	832	0	0
T9	276359	6840	0	0
T10	118715	832	0	0
T11	372750	9152	0	0
T12	0	8320	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	189021	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	189021	0	0
T1	658250	461	0	0
T2	5247	0	0	0
T3	47008	0	0	0
T4	3759	0	0	0
T5	123490	1001	0	0
T6	132253	480	0	0
T7	47909	0	0	0
T8	291497	731	0	0
T9	276359	192	0	0
T10	118715	0	0	0
T11	0	1141	0	0
T12	0	1642	0	0
T28	0	1777	0	0
T31	0	105	0	0
T37	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	406730	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	406730	0	0
T1	658250	461	0	0
T2	5247	0	0	0
T3	47008	0	0	0
T4	3759	0	0	0
T5	123490	1001	0	0
T6	132253	2097	0	0
T7	47909	0	0	0
T8	291497	731	0	0
T9	276359	628	0	0
T10	118715	0	0	0
T11	0	1139	0	0
T12	0	1642	0	0
T28	0	7940	0	0
T31	0	105	0	0
T37	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	5901172	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	5901172	0	0
T1	658250	10757	0	0
T2	5247	199	0	0
T3	47008	1215	0	0
T4	3759	41	0	0
T5	123490	2850	0	0
T6	132253	25965	0	0
T7	47909	1929	0	0
T8	291497	7753	0	0
T9	276359	880	0	0
T10	118715	47165	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	458632914	12204861	0	0
DepthKnown_A	458632914	458500281	0	0
RvalidKnown_A	458632914	458500281	0	0
WreadyKnown_A	458632914	458500281	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	12204861	0	0
T1	658250	10719	0	0
T2	5247	198	0	0
T3	47008	5280	0	0
T4	3759	194	0	0
T5	123490	2850	0	0
T6	132253	82862	0	0
T7	47909	6058	0	0
T8	291497	7614	0	0
T9	276359	2575	0	0
T10	118715	204889	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458632914	458500281	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0