Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	755921068	604506331	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	755921068	3697901	0	0
GntImpliesValid_A	755921068	3697901	0	0
GrantKnown_A	755921068	604506331	0	0
IdxKnown_A	755921068	604506331	0	0
IndexIsCorrect_A	755921068	3697901	0	0
LockArbDecision_A	755921068	0	0	0
NoReadyValidNoGrant_A	755921068	0	0	0
ReadyAndValidImplyGrant_A	755921068	3697901	0	0
ReqAndReadyImplyGrant_A	755921068	3697901	0	0
ReqImpliesValid_A	755921068	3697901	0	0
ReqStaysHighUntilGranted0_M	755921068	0	0	0
RoundRobin_A	755921068	5	0	955
ValidKnown_A	755921068	604506331	0	0
gen_data_port_assertion.DataFlow_A	755921068	3697901	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	604506331	0	0
T1	738666	734396	0	0
T2	10149	7608	0	0
T3	221388	134118	0	0
T4	5769	4642	0	0
T5	1239734	680061	0	0
T6	647839	384436	0	0
T7	73321	60527	0	0
T8	696391	484777	0	0
T9	776899	525877	0	0
T10	512567	315162	0	0
T11	694657	686606	0	0
T12	0	863597	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	604506331	0	0
T1	738666	734396	0	0
T2	10149	7608	0	0
T3	221388	134118	0	0
T4	5769	4642	0	0
T5	1239734	680061	0	0
T6	647839	384436	0	0
T7	73321	60527	0	0
T8	696391	484777	0	0
T9	776899	525877	0	0
T10	512567	315162	0	0
T11	694657	686606	0	0
T12	0	863597	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	604506331	0	0
T1	738666	734396	0	0
T2	10149	7608	0	0
T3	221388	134118	0	0
T4	5769	4642	0	0
T5	1239734	680061	0	0
T6	647839	384436	0	0
T7	73321	60527	0	0
T8	696391	484777	0	0
T9	776899	525877	0	0
T10	512567	315162	0	0
T11	694657	686606	0	0
T12	0	863597	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	5	0	955
T48	213604	1	0	1
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	1394	0	0	1
T53	318450	0	0	1
T54	15330	0	0	1
T55	1189	0	0	1
T56	964	0	0	1
T57	1829	0	0	1
T58	617916	0	0	1
T59	2102	0	0	1
T60	49105	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	604506331	0	0
T1	738666	734396	0	0
T2	10149	7608	0	0
T3	221388	134118	0	0
T4	5769	4642	0	0
T5	1239734	680061	0	0
T6	647839	384436	0	0
T7	73321	60527	0	0
T8	696391	484777	0	0
T9	776899	525877	0	0
T10	512567	315162	0	0
T11	694657	686606	0	0
T12	0	863597	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755921068	3697901	0	0
T1	738666	4328	0	0
T2	7698	832	0	0
T3	134198	832	0	0
T4	4764	0	0	0
T5	1239734	22332	0	0
T6	647839	7610	0	0
T7	73321	832	0	0
T8	696391	6860	0	0
T9	776899	4665	0	0
T10	512567	832	0	0
T11	694657	18911	0	0
T12	876955	12514	0	0
T14	0	268	0	0
T23	0	2	0	0
T27	0	2	0	0
T28	0	13330	0	0
T31	23733	585	0	0
T33	72	0	0	0
T37	0	29	0	0
T40	0	10245	0	0
T47	0	64	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149918247	30019816	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	149918247	628287	0	0
GntImpliesValid_A	149918247	628287	0	0
GrantKnown_A	149918247	30019816	0	0
IdxKnown_A	149918247	30019816	0	0
IndexIsCorrect_A	149918247	628287	0	0
LockArbDecision_A	149918247	0	0	0
NoReadyValidNoGrant_A	149918247	0	0	0
ReadyAndValidImplyGrant_A	149918247	628287	0	0
ReqAndReadyImplyGrant_A	149918247	628287	0	0
ReqImpliesValid_A	149918247	628287	0	0
ReqStaysHighUntilGranted0_M	149918247	0	0	0
RoundRobin_A	149918247	0	0	0
ValidKnown_A	149918247	30019816	0	0
gen_data_port_assertion.DataFlow_A	149918247	628287	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	30019816	0	0
T1	80416	76240	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	936	0	0
T5	558122	0	0	0
T6	257793	61376	0	0
T7	12706	0	0	0
T8	202447	159984	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	291808	0	0
T12	0	170456	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	30019816	0	0
T1	80416	76240	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	936	0	0
T5	558122	0	0	0
T6	257793	61376	0	0
T7	12706	0	0	0
T8	202447	159984	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	291808	0	0
T12	0	170456	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	30019816	0	0
T1	80416	76240	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	936	0	0
T5	558122	0	0	0
T6	257793	61376	0	0
T7	12706	0	0	0
T8	202447	159984	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	291808	0	0
T12	0	170456	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	30019816	0	0
T1	80416	76240	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	936	0	0
T5	558122	0	0	0
T6	257793	61376	0	0
T7	12706	0	0	0
T8	202447	159984	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	291808	0	0
T12	0	170456	0	0
T24	0	936	0	0
T27	0	80	0	0
T31	0	23544	0	0
T33	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	628287	0	0
T1	80416	2869	0	0
T2	2451	0	0	0
T3	87190	0	0	0
T4	1005	0	0	0
T5	558122	0	0	0
T6	257793	2290	0	0
T7	12706	0	0	0
T8	202447	4127	0	0
T9	250270	0	0	0
T10	196926	0	0	0
T11	0	5259	0	0
T12	0	6596	0	0
T27	0	2	0	0
T28	0	5720	0	0
T31	0	585	0	0
T37	0	29	0	0
T47	0	64	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149918247	118488422	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	149918247	799682	0	0
GntImpliesValid_A	149918247	799682	0	0
GrantKnown_A	149918247	118488422	0	0
IdxKnown_A	149918247	118488422	0	0
IndexIsCorrect_A	149918247	799682	0	0
LockArbDecision_A	149918247	0	0	0
NoReadyValidNoGrant_A	149918247	0	0	0
ReadyAndValidImplyGrant_A	149918247	799682	0	0
ReqAndReadyImplyGrant_A	149918247	799682	0	0
ReqImpliesValid_A	149918247	799682	0	0
ReqStaysHighUntilGranted0_M	149918247	0	0	0
RoundRobin_A	149918247	0	0	0
ValidKnown_A	149918247	118488422	0	0
gen_data_port_assertion.DataFlow_A	149918247	799682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	118488422	0	0
T2	2451	2416	0	0
T3	87190	87190	0	0
T4	1005	0	0	0
T5	558122	556581	0	0
T6	257793	190816	0	0
T7	12706	12706	0	0
T8	202447	33387	0	0
T9	250270	249586	0	0
T10	196926	196456	0	0
T11	694657	394798	0	0
T12	0	693141	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	118488422	0	0
T2	2451	2416	0	0
T3	87190	87190	0	0
T4	1005	0	0	0
T5	558122	556581	0	0
T6	257793	190816	0	0
T7	12706	12706	0	0
T8	202447	33387	0	0
T9	250270	249586	0	0
T10	196926	196456	0	0
T11	694657	394798	0	0
T12	0	693141	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	118488422	0	0
T2	2451	2416	0	0
T3	87190	87190	0	0
T4	1005	0	0	0
T5	558122	556581	0	0
T6	257793	190816	0	0
T7	12706	12706	0	0
T8	202447	33387	0	0
T9	250270	249586	0	0
T10	196926	196456	0	0
T11	694657	394798	0	0
T12	0	693141	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	118488422	0	0
T2	2451	2416	0	0
T3	87190	87190	0	0
T4	1005	0	0	0
T5	558122	556581	0	0
T6	257793	190816	0	0
T7	12706	12706	0	0
T8	202447	33387	0	0
T9	250270	249586	0	0
T10	196926	196456	0	0
T11	694657	394798	0	0
T12	0	693141	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149918247	799682	0	0
T5	558122	9630	0	0
T6	257793	142	0	0
T7	12706	0	0	0
T8	202447	1	0	0
T9	250270	1132	0	0
T10	196926	0	0	0
T11	694657	1995	0	0
T12	876955	5918	0	0
T14	0	268	0	0
T23	0	2	0	0
T28	0	7610	0	0
T31	23733	0	0	0
T33	72	0	0	0
T40	0	10245	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456084574	455998093	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	456084574	2269932	0	0
GntImpliesValid_A	456084574	2269932	0	0
GrantKnown_A	456084574	455998093	0	0
IdxKnown_A	456084574	455998093	0	0
IndexIsCorrect_A	456084574	2269932	0	0
LockArbDecision_A	456084574	0	0	0
NoReadyValidNoGrant_A	456084574	0	0	0
ReadyAndValidImplyGrant_A	456084574	2269932	0	0
ReqAndReadyImplyGrant_A	456084574	2269932	0	0
ReqImpliesValid_A	456084574	2269932	0	0
ReqStaysHighUntilGranted0_M	456084574	0	0	0
RoundRobin_A	456084574	5	0	955
ValidKnown_A	456084574	455998093	0	0
gen_data_port_assertion.DataFlow_A	456084574	2269932	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	455998093	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	455998093	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	455998093	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	5	0	955
T48	213604	1	0	1
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	1394	0	0	1
T53	318450	0	0	1
T54	15330	0	0	1
T55	1189	0	0	1
T56	964	0	0	1
T57	1829	0	0	1
T58	617916	0	0	1
T59	2102	0	0	1
T60	49105	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	455998093	0	0
T1	658250	658156	0	0
T2	5247	5192	0	0
T3	47008	46928	0	0
T4	3759	3706	0	0
T5	123490	123480	0	0
T6	132253	132244	0	0
T7	47909	47821	0	0
T8	291497	291406	0	0
T9	276359	276291	0	0
T10	118715	118706	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456084574	2269932	0	0
T1	658250	1459	0	0
T2	5247	832	0	0
T3	47008	832	0	0
T4	3759	0	0	0
T5	123490	12702	0	0
T6	132253	5178	0	0
T7	47909	832	0	0
T8	291497	2732	0	0
T9	276359	3533	0	0
T10	118715	832	0	0
T11	0	11657	0	0