Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3611496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4293577

1

T1

435

T2

895

T3

1220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4385000	1			T1	1		T2	7		T3	682
values[0x0]	1757718	1			T1	275		T2	431		T3	437
values[0x1]	1762355	1			T1	272		T2	462		T3	454

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2567024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5338049

1

T1

463

T2

896

T3

1281

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28898	1			T2	9		T4	4		T7	57
valid_sources[0x01]	31417	1			T2	3		T3	52		T7	178
valid_sources[0x02]	30113	1			T2	9		T3	44		T4	2
valid_sources[0x03]	29679	1			T2	28		T4	12		T7	104
valid_sources[0x04]	37968	1			T4	10		T8	1		T9	68
valid_sources[0x05]	27463	1			T2	2		T3	6		T4	2
valid_sources[0x06]	28780	1			T1	8		T3	9		T5	7
valid_sources[0x07]	28791	1			T1	8		T2	5		T4	1
valid_sources[0x08]	29981	1			T1	15		T2	11		T5	16
valid_sources[0x09]	25768	1			T1	3		T3	1		T5	20
valid_sources[0x0a]	30199	1			T2	6		T4	7		T7	1
valid_sources[0x0b]	31231	1			T1	6		T2	2		T3	10
valid_sources[0x0c]	27541	1			T3	38		T7	135		T8	1
valid_sources[0x0d]	29072	1			T1	3		T4	25		T5	9
valid_sources[0x0e]	32705	1			T2	7		T4	4		T8	1
valid_sources[0x0f]	30421	1			T1	3		T2	17		T3	4
valid_sources[0x10]	28889	1			T3	15		T4	5		T7	157
valid_sources[0x11]	30570	1			T1	1		T4	3		T5	22
valid_sources[0x12]	31015	1			T2	3		T4	8		T5	2
valid_sources[0x13]	28833	1			T1	2		T4	14		T5	2
valid_sources[0x14]	27941	1			T1	1		T2	5		T5	2
valid_sources[0x15]	28462	1			T2	4		T4	21		T5	3
valid_sources[0x16]	28973	1			T1	1		T3	6		T4	2
valid_sources[0x17]	29567	1			T2	6		T4	11		T5	7
valid_sources[0x18]	32999	1			T1	8		T3	8		T4	15
valid_sources[0x19]	32871	1			T1	9		T9	92		T10	74
valid_sources[0x1a]	28053	1			T1	12		T4	5		T7	1108
valid_sources[0x1b]	30170	1			T1	14		T3	4		T4	5
valid_sources[0x1c]	30412	1			T2	2		T3	1		T4	11
valid_sources[0x1d]	30280	1			T2	14		T3	5		T4	16
valid_sources[0x1e]	29307	1			T1	3		T3	8		T4	7
valid_sources[0x1f]	29627	1			T3	24		T4	22		T5	12
valid_sources[0x20]	33827	1			T3	13		T4	12		T5	14
valid_sources[0x21]	28888	1			T1	3		T5	6		T7	11
valid_sources[0x22]	27803	1			T3	3		T4	7		T5	3
valid_sources[0x23]	32585	1			T2	10		T5	4		T7	21
valid_sources[0x24]	32200	1			T4	1		T7	6		T9	80
valid_sources[0x25]	31913	1			T1	13		T2	4		T3	9
valid_sources[0x26]	30377	1			T2	3		T3	9		T4	4
valid_sources[0x27]	30087	1			T1	1		T3	11		T4	2
valid_sources[0x28]	28289	1			T1	4		T2	1		T3	10
valid_sources[0x29]	27994	1			T4	4		T5	4		T7	5
valid_sources[0x2a]	28632	1			T1	2		T2	7		T3	22
valid_sources[0x2b]	29561	1			T2	1		T3	4		T4	3
valid_sources[0x2c]	36251	1			T1	3		T3	3		T4	15
valid_sources[0x2d]	30459	1			T1	6		T2	5		T3	6
valid_sources[0x2e]	29186	1			T1	5		T5	5		T9	81
valid_sources[0x2f]	27669	1			T2	2		T4	13		T5	13
valid_sources[0x30]	32326	1			T4	14		T5	1		T7	24
valid_sources[0x31]	99506	1			T7	3		T8	1		T9	77
valid_sources[0x32]	29336	1			T5	20		T7	2		T9	56
valid_sources[0x33]	29021	1			T2	5		T3	8		T5	4
valid_sources[0x34]	27967	1			T1	1		T3	20		T4	3
valid_sources[0x35]	31636	1			T3	7		T4	1		T8	1
valid_sources[0x36]	28480	1			T3	15		T4	4		T5	5
valid_sources[0x37]	30735	1			T4	2		T7	179		T9	68
valid_sources[0x38]	34539	1			T5	1		T7	90		T9	60
valid_sources[0x39]	27147	1			T1	6		T2	6		T3	1
valid_sources[0x3a]	29324	1			T1	4		T2	2		T4	15
valid_sources[0x3b]	28016	1			T1	2		T2	5		T3	4
valid_sources[0x3c]	55772	1			T2	8		T3	2		T5	1
valid_sources[0x3d]	33934	1			T1	3		T3	1		T9	58
valid_sources[0x3e]	31963	1			T1	12		T2	1		T3	9
valid_sources[0x3f]	28837	1			T1	3		T4	1		T7	6
valid_sources[0x40]	30602	1			T5	15		T7	627		T9	69
valid_sources[0x41]	32561	1			T3	2		T4	14		T5	6
valid_sources[0x42]	28283	1			T2	7		T4	17		T7	106
valid_sources[0x43]	29981	1			T2	5		T4	1		T5	9
valid_sources[0x44]	34797	1			T4	18		T7	1		T9	76
valid_sources[0x45]	29242	1			T1	2		T2	4		T4	3
valid_sources[0x46]	28366	1			T1	3		T4	8		T8	3
valid_sources[0x47]	29194	1			T2	7		T3	24		T4	1
valid_sources[0x48]	31529	1			T3	2		T5	5		T7	87
valid_sources[0x49]	28534	1			T3	15		T4	5		T5	12
valid_sources[0x4a]	26702	1			T1	12		T2	1		T5	5
valid_sources[0x4b]	28564	1			T4	14		T5	5		T7	5
valid_sources[0x4c]	29464	1			T2	6		T4	3		T7	4
valid_sources[0x4d]	31060	1			T2	4		T5	4		T8	1
valid_sources[0x4e]	29273	1			T2	7		T4	6		T7	4
valid_sources[0x4f]	28205	1			T4	1		T5	6		T7	83
valid_sources[0x50]	27054	1			T2	6		T4	2		T5	8
valid_sources[0x51]	29579	1			T1	3		T2	5		T4	19
valid_sources[0x52]	28750	1			T1	7		T2	3		T3	1
valid_sources[0x53]	28352	1			T5	2		T7	5		T8	1
valid_sources[0x54]	26421	1			T1	13		T2	26		T4	18
valid_sources[0x55]	30269	1			T1	1		T2	2		T3	19
valid_sources[0x56]	29048	1			T4	8		T5	7		T7	39
valid_sources[0x57]	31657	1			T3	25		T5	2		T7	585
valid_sources[0x58]	28394	1			T2	1		T5	2		T7	2
valid_sources[0x59]	30009	1			T4	17		T5	1		T7	5
valid_sources[0x5a]	27166	1			T1	3		T3	59		T5	4
valid_sources[0x5b]	89656	1			T1	5		T2	2		T7	580
valid_sources[0x5c]	28536	1			T4	10		T7	2		T9	80
valid_sources[0x5d]	33291	1			T4	4		T5	1		T9	59
valid_sources[0x5e]	30900	1			T1	1		T4	22		T5	22
valid_sources[0x5f]	29889	1			T2	2		T7	18		T9	89
valid_sources[0x60]	28546	1			T3	16		T4	16		T5	3
valid_sources[0x61]	31611	1			T2	4		T4	13		T7	76
valid_sources[0x62]	27559	1			T2	4		T3	8		T5	1
valid_sources[0x63]	30989	1			T3	53		T4	3		T5	6
valid_sources[0x64]	26980	1			T2	2		T3	23		T6	1
valid_sources[0x65]	30161	1			T1	5		T3	32		T4	2
valid_sources[0x66]	37223	1			T1	14		T2	1		T3	23
valid_sources[0x67]	26025	1			T2	2		T4	20		T5	1
valid_sources[0x68]	28970	1			T2	16		T4	4		T7	171
valid_sources[0x69]	32110	1			T1	2		T2	2		T4	13
valid_sources[0x6a]	28799	1			T2	3		T3	19		T4	13
valid_sources[0x6b]	31103	1			T1	1		T4	21		T5	7
valid_sources[0x6c]	28646	1			T2	5		T4	20		T5	12
valid_sources[0x6d]	31429	1			T4	19		T5	6		T7	92
valid_sources[0x6e]	29902	1			T2	5		T4	10		T5	5
valid_sources[0x6f]	30668	1			T2	2		T5	1		T7	10
valid_sources[0x70]	32753	1			T2	4		T4	6		T5	6
valid_sources[0x71]	28345	1			T3	41		T4	8		T5	10
valid_sources[0x72]	30350	1			T2	18		T4	4		T9	68
valid_sources[0x73]	27715	1			T1	4		T2	10		T4	1
valid_sources[0x74]	28125	1			T1	1		T2	14		T3	24
valid_sources[0x75]	31492	1			T1	2		T3	2		T5	10
valid_sources[0x76]	30823	1			T2	1		T3	5		T4	2
valid_sources[0x77]	28927	1			T3	14		T4	2		T5	9
valid_sources[0x78]	28174	1			T4	15		T7	4		T9	71
valid_sources[0x79]	34208	1			T1	3		T4	5		T7	413
valid_sources[0x7a]	31682	1			T1	6		T2	3		T4	15
valid_sources[0x7b]	27795	1			T3	2		T4	5		T5	15
valid_sources[0x7c]	31170	1			T1	4		T2	2		T3	8
valid_sources[0x7d]	30702	1			T2	2		T4	15		T8	1
valid_sources[0x7e]	31872	1			T3	4		T4	27		T5	2
valid_sources[0x7f]	33345	1			T2	6		T3	9		T4	4
valid_sources[0x80]	29787	1			T5	1		T7	1		T9	67

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1100823

1

T1

1

T2

4

T3

339

values[0x0]

all_enables

biggest_size

1606542

1

T1

217

T2

429

T3

433

values[0x1]

all_enables

biggest_size

1586212

1

T1

217

T2

462

T3

448