Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3634973

1

T1

113

T2

5

T3

353

full_word

4294939

1

T1

435

T2

895

T3

1220

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7929482	1			T1	548		T2	900		T3	1573
auto[TlIntgErrCmd]	146	1			T52	12		T87	4		T86	7
auto[TlIntgErrData]	134	1			T52	10		T87	3		T86	8
auto[TlIntgErrBoth]	150	1			T52	8		T87	3		T86	15

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4390376

1

T1

1

T2

7

T3

682

auto[1]

3539536

1

T1

547

T2

893

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3288959	1			T2	3		T3	343		T4	367
auto[TlIntgErrNone]	partial	auto[1]	345619	1			T1	113		T2	2		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	1101228	1			T1	1		T2	4		T3	339
auto[TlIntgErrNone]	full_word	auto[1]	3193676	1			T1	434		T2	891		T3	881
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T52	4		T87	1		T86	2
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T52	7		T87	2		T86	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T87	1		T155	1		T153	1
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T52	1		T86	1		T156	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T52	6		T87	1		T86	5
auto[TlIntgErrData]	partial	auto[1]	59	1			T52	3		T87	1		T86	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T99	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	11	1			T52	1		T87	1		T86	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T52	2		T87	2		T86	7
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T52	5		T87	1		T86	7
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T52	1		T86	1		T98	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T153	1		T154	1		-	-