Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	2936635	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	2936635	0	0
T2	119002	1663	0	0
T3	18467	1666	0	0
T4	21925	1663	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9981	0	0
T8	1652	0	0	0
T9	693573	12484	0	0
T10	373619	17465	0	0
T11	162680	6653	0	0
T12	0	12496	0	0
T13	0	8319	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	3221667	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	3221667	0	0
T2	119002	832	0	0
T3	18467	835	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	7488	0	0
T8	1652	0	0	0
T9	693573	17284	0	0
T10	373619	11648	0	0
T11	162680	4160	0	0
T12	0	23051	0	0
T13	0	13719	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	195214	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	195214	0	0
T7	486067	1051	0	0
T8	1652	0	0	0
T9	693573	292	0	0
T10	373619	466	0	0
T11	162680	959	0	0
T12	327511	705	0	0
T13	190422	498	0	0
T14	0	2055	0	0
T22	0	263	0	0
T29	194965	229	0	0
T30	0	735	0	0
T37	1402	0	0	0
T38	25864	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	430971	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	430971	0	0
T7	486067	1050	0	0
T8	1652	0	0	0
T9	693573	940	0	0
T10	373619	465	0	0
T11	162680	959	0	0
T12	327511	3187	0	0
T13	190422	1363	0	0
T14	0	2055	0	0
T22	0	263	0	0
T29	194965	229	0	0
T30	0	2216	0	0
T37	1402	0	0	0
T38	25864	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	6238253	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	6238253	0	0
T1	472295	548	0	0
T2	119002	68	0	0
T3	18467	741	0	0
T4	21925	815	0	0
T5	10133	222	0	0
T6	1832	17	0	0
T7	486067	8068	0	0
T8	1652	73	0	0
T9	693573	10680	0	0
T10	373619	2395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	479340252	12181538	0	0
DepthKnown_A	479340252	479206008	0	0
RvalidKnown_A	479340252	479206008	0	0
WreadyKnown_A	479340252	479206008	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	12181538	0	0
T1	472295	2296	0	0
T2	119002	68	0	0
T3	18467	3283	0	0
T4	21925	815	0	0
T5	10133	222	0	0
T6	1832	17	0	0
T7	486067	7997	0	0
T8	1652	73	0	0
T9	693573	33021	0	0
T10	373619	2387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479340252	479206008	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0