Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T7,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T7,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T7,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	779677221	626718303	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	779677221	3777983	0	0
GntImpliesValid_A	779677221	3777983	0	0
GrantKnown_A	779677221	626718303	0	0
IdxKnown_A	779677221	626718303	0	0
IndexIsCorrect_A	779677221	3777983	0	0
LockArbDecision_A	779677221	0	0	0
NoReadyValidNoGrant_A	779677221	0	0	0
ReadyAndValidImplyGrant_A	779677221	3777983	0	0
ReqAndReadyImplyGrant_A	779677221	3777983	0	0
ReqImpliesValid_A	779677221	3777983	0	0
ReqStaysHighUntilGranted0_M	779677221	0	0	0
RoundRobin_A	779677221	7	0	956
ValidKnown_A	779677221	626718303	0	0
gen_data_port_assertion.DataFlow_A	779677221	3777983	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	626718303	0	0
T1	541852	537163	0	0
T2	349018	233380	0	0
T3	47955	33149	0	0
T4	94933	58332	0	0
T5	21621	15786	0	0
T6	2552	2125	0	0
T7	2086835	1281074	0	0
T8	1652	1562	0	0
T9	2410671	1549484	0	0
T10	589081	543745	0	0
T11	646922	315456	0	0
T12	458993	456429	0	0
T13	0	473128	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	626718303	0	0
T1	541852	537163	0	0
T2	349018	233380	0	0
T3	47955	33149	0	0
T4	94933	58332	0	0
T5	21621	15786	0	0
T6	2552	2125	0	0
T7	2086835	1281074	0	0
T8	1652	1562	0	0
T9	2410671	1549484	0	0
T10	589081	543745	0	0
T11	646922	315456	0	0
T12	458993	456429	0	0
T13	0	473128	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	626718303	0	0
T1	541852	537163	0	0
T2	349018	233380	0	0
T3	47955	33149	0	0
T4	94933	58332	0	0
T5	21621	15786	0	0
T6	2552	2125	0	0
T7	2086835	1281074	0	0
T8	1652	1562	0	0
T9	2410671	1549484	0	0
T10	589081	543745	0	0
T11	646922	315456	0	0
T12	458993	456429	0	0
T13	0	473128	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	7	0	956
T11	162680	1	0	1
T12	327511	0	0	1
T13	190422	0	0	1
T14	448536	0	0	1
T29	194965	0	0	1
T30	200021	0	0	1
T37	1402	0	0	1
T38	25864	0	0	1
T40	11141	0	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	138252	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	626718303	0	0
T1	541852	537163	0	0
T2	349018	233380	0	0
T3	47955	33149	0	0
T4	94933	58332	0	0
T5	21621	15786	0	0
T6	2552	2125	0	0
T7	2086835	1281074	0	0
T8	1652	1562	0	0
T9	2410671	1549484	0	0
T10	589081	543745	0	0
T11	646922	315456	0	0
T12	458993	456429	0	0
T13	0	473128	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	779677221	3777983	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	2086835	24423	0	0
T8	1652	0	0	0
T9	2410671	10064	0	0
T10	589081	17252	0	0
T11	809602	11677	0	0
T12	917986	14064	0	0
T13	954086	10165	0	0
T14	0	18981	0	0
T22	0	3112	0	0
T25	0	9357	0	0
T27	0	1814	0	0
T29	77178	1489	0	0
T30	999246	4959	0	0
T38	4208	0	0	0
T40	21586	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Unreachable
1	1	Covered	T7,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151467147	28291455	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	151467147	667956	0	0
GntImpliesValid_A	151467147	667956	0	0
GrantKnown_A	151467147	28291455	0	0
IdxKnown_A	151467147	28291455	0	0
IndexIsCorrect_A	151467147	667956	0	0
LockArbDecision_A	151467147	0	0	0
NoReadyValidNoGrant_A	151467147	0	0	0
ReadyAndValidImplyGrant_A	151467147	667956	0	0
ReqAndReadyImplyGrant_A	151467147	667956	0	0
ReqImpliesValid_A	151467147	667956	0	0
ReqStaysHighUntilGranted0_M	151467147	0	0	0
RoundRobin_A	151467147	0	0	0
ValidKnown_A	151467147	28291455	0	0
gen_data_port_assertion.DataFlow_A	151467147	667956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	28291455	0	0
T1	69557	64968	0	0
T2	115008	0	0	0
T3	14744	0	0	0
T4	36504	0	0	0
T5	5744	0	0	0
T6	360	360	0	0
T7	800384	116632	0	0
T9	858549	0	0	0
T10	107731	69840	0	0
T11	323461	125328	0	0
T13	0	150032	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	28291455	0	0
T1	69557	64968	0	0
T2	115008	0	0	0
T3	14744	0	0	0
T4	36504	0	0	0
T5	5744	0	0	0
T6	360	360	0	0
T7	800384	116632	0	0
T9	858549	0	0	0
T10	107731	69840	0	0
T11	323461	125328	0	0
T13	0	150032	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	28291455	0	0
T1	69557	64968	0	0
T2	115008	0	0	0
T3	14744	0	0	0
T4	36504	0	0	0
T5	5744	0	0	0
T6	360	360	0	0
T7	800384	116632	0	0
T9	858549	0	0	0
T10	107731	69840	0	0
T11	323461	125328	0	0
T13	0	150032	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	28291455	0	0
T1	69557	64968	0	0
T2	115008	0	0	0
T3	14744	0	0	0
T4	36504	0	0	0
T5	5744	0	0	0
T6	360	360	0	0
T7	800384	116632	0	0
T9	858549	0	0	0
T10	107731	69840	0	0
T11	323461	125328	0	0
T13	0	150032	0	0
T14	0	171160	0	0
T22	0	25664	0	0
T29	0	37648	0	0
T30	0	61080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	667956	0	0
T7	800384	2405	0	0
T9	858549	0	0	0
T10	107731	819	0	0
T11	323461	5157	0	0
T12	458993	0	0	0
T13	477043	2120	0	0
T14	0	7347	0	0
T22	0	259	0	0
T25	0	5635	0	0
T27	0	1814	0	0
T29	38589	1489	0	0
T30	499623	2358	0	0
T38	2104	0	0	0
T40	10793	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T7,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T7,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	151467147	121771417	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	151467147	801187	0	0
GntImpliesValid_A	151467147	801187	0	0
GrantKnown_A	151467147	121771417	0	0
IdxKnown_A	151467147	121771417	0	0
IndexIsCorrect_A	151467147	801187	0	0
LockArbDecision_A	151467147	0	0	0
NoReadyValidNoGrant_A	151467147	0	0	0
ReadyAndValidImplyGrant_A	151467147	801187	0	0
ReqAndReadyImplyGrant_A	151467147	801187	0	0
ReqImpliesValid_A	151467147	801187	0	0
ReqStaysHighUntilGranted0_M	151467147	0	0	0
RoundRobin_A	151467147	0	0	0
ValidKnown_A	151467147	121771417	0	0
gen_data_port_assertion.DataFlow_A	151467147	801187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	121771417	0	0
T2	115008	114466	0	0
T3	14744	14744	0	0
T4	36504	36504	0	0
T5	5744	5744	0	0
T6	360	0	0	0
T7	800384	678460	0	0
T9	858549	855918	0	0
T10	107731	100367	0	0
T11	323461	190128	0	0
T12	458993	456429	0	0
T13	0	323096	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	121771417	0	0
T2	115008	114466	0	0
T3	14744	14744	0	0
T4	36504	36504	0	0
T5	5744	5744	0	0
T6	360	0	0	0
T7	800384	678460	0	0
T9	858549	855918	0	0
T10	107731	100367	0	0
T11	323461	190128	0	0
T12	458993	456429	0	0
T13	0	323096	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	121771417	0	0
T2	115008	114466	0	0
T3	14744	14744	0	0
T4	36504	36504	0	0
T5	5744	5744	0	0
T6	360	0	0	0
T7	800384	678460	0	0
T9	858549	855918	0	0
T10	107731	100367	0	0
T11	323461	190128	0	0
T12	458993	456429	0	0
T13	0	323096	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	121771417	0	0
T2	115008	114466	0	0
T3	14744	14744	0	0
T4	36504	36504	0	0
T5	5744	5744	0	0
T6	360	0	0	0
T7	800384	678460	0	0
T9	858549	855918	0	0
T10	107731	100367	0	0
T11	323461	190128	0	0
T12	458993	456429	0	0
T13	0	323096	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151467147	801187	0	0
T7	800384	12812	0	0
T9	858549	1439	0	0
T10	107731	4057	0	0
T11	323461	15	0	0
T12	458993	5011	0	0
T13	477043	388	0	0
T14	0	11634	0	0
T22	0	2853	0	0
T25	0	3722	0	0
T29	38589	0	0	0
T30	499623	2601	0	0
T38	2104	0	0	0
T40	10793	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	476742927	476655431	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	476742927	2308840	0	0
GntImpliesValid_A	476742927	2308840	0	0
GrantKnown_A	476742927	476655431	0	0
IdxKnown_A	476742927	476655431	0	0
IndexIsCorrect_A	476742927	2308840	0	0
LockArbDecision_A	476742927	0	0	0
NoReadyValidNoGrant_A	476742927	0	0	0
ReadyAndValidImplyGrant_A	476742927	2308840	0	0
ReqAndReadyImplyGrant_A	476742927	2308840	0	0
ReqImpliesValid_A	476742927	2308840	0	0
ReqStaysHighUntilGranted0_M	476742927	0	0	0
RoundRobin_A	476742927	7	0	956
ValidKnown_A	476742927	476655431	0	0
gen_data_port_assertion.DataFlow_A	476742927	2308840	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	476655431	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	476655431	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	476655431	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	7	0	956
T11	162680	1	0	1
T12	327511	0	0	1
T13	190422	0	0	1
T14	448536	0	0	1
T29	194965	0	0	1
T30	200021	0	0	1
T37	1402	0	0	1
T38	25864	0	0	1
T40	11141	0	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	138252	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	476655431	0	0
T1	472295	472195	0	0
T2	119002	118914	0	0
T3	18467	18405	0	0
T4	21925	21828	0	0
T5	10133	10042	0	0
T6	1832	1765	0	0
T7	486067	485982	0	0
T8	1652	1562	0	0
T9	693573	693566	0	0
T10	373619	373538	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476742927	2308840	0	0
T2	119002	832	0	0
T3	18467	832	0	0
T4	21925	832	0	0
T5	10133	832	0	0
T6	1832	0	0	0
T7	486067	9206	0	0
T8	1652	0	0	0
T9	693573	8625	0	0
T10	373619	12376	0	0
T11	162680	6505	0	0
T12	0	9053	0	0
T13	0	7657	0	0