Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3658 | 
0 | 
0 | 
| T50 | 
17223 | 
197 | 
0 | 
0 | 
| T51 | 
4352 | 
181 | 
0 | 
0 | 
| T52 | 
104737 | 
5 | 
0 | 
0 | 
| T85 | 
4133 | 
177 | 
0 | 
0 | 
| T86 | 
98789 | 
6 | 
0 | 
0 | 
| T87 | 
10227 | 
3 | 
0 | 
0 | 
| T91 | 
3030 | 
49 | 
0 | 
0 | 
| T93 | 
8242 | 
3 | 
0 | 
0 | 
| T97 | 
5089 | 
1 | 
0 | 
0 | 
| T98 | 
96953 | 
6 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2890 | 
0 | 
0 | 
| T52 | 
104737 | 
95 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
112 | 
0 | 
0 | 
| T98 | 
96953 | 
55 | 
0 | 
0 | 
| T104 | 
9285 | 
9 | 
0 | 
0 | 
| T140 | 
11567 | 
22 | 
0 | 
0 | 
| T141 | 
7372 | 
8 | 
0 | 
0 | 
| T142 | 
14151 | 
51 | 
0 | 
0 | 
| T143 | 
20621 | 
75 | 
0 | 
0 | 
| T144 | 
21410 | 
105 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2645 | 
0 | 
0 | 
| T52 | 
104737 | 
111 | 
0 | 
0 | 
| T71 | 
2270 | 
6 | 
0 | 
0 | 
| T86 | 
98789 | 
110 | 
0 | 
0 | 
| T98 | 
96953 | 
51 | 
0 | 
0 | 
| T99 | 
100674 | 
118 | 
0 | 
0 | 
| T140 | 
11567 | 
11 | 
0 | 
0 | 
| T141 | 
7372 | 
11 | 
0 | 
0 | 
| T142 | 
14151 | 
11 | 
0 | 
0 | 
| T143 | 
20621 | 
82 | 
0 | 
0 | 
| T144 | 
21410 | 
46 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3952 | 
0 | 
0 | 
| T52 | 
104737 | 
174 | 
0 | 
0 | 
| T86 | 
98789 | 
244 | 
0 | 
0 | 
| T98 | 
96953 | 
112 | 
0 | 
0 | 
| T99 | 
100674 | 
169 | 
0 | 
0 | 
| T104 | 
9285 | 
16 | 
0 | 
0 | 
| T140 | 
11567 | 
25 | 
0 | 
0 | 
| T141 | 
7372 | 
4 | 
0 | 
0 | 
| T142 | 
14151 | 
47 | 
0 | 
0 | 
| T143 | 
20621 | 
64 | 
0 | 
0 | 
| T144 | 
21410 | 
70 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
20060 | 
0 | 
0 | 
| T52 | 
104737 | 
2321 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
1960 | 
0 | 
0 | 
| T98 | 
96953 | 
1082 | 
0 | 
0 | 
| T104 | 
9285 | 
95 | 
0 | 
0 | 
| T140 | 
11567 | 
11 | 
0 | 
0 | 
| T141 | 
7372 | 
3 | 
0 | 
0 | 
| T142 | 
14151 | 
95 | 
0 | 
0 | 
| T143 | 
20621 | 
48 | 
0 | 
0 | 
| T144 | 
21410 | 
58 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
19197 | 
0 | 
0 | 
| T52 | 
104737 | 
1421 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
2388 | 
0 | 
0 | 
| T98 | 
96953 | 
1003 | 
0 | 
0 | 
| T99 | 
100674 | 
1531 | 
0 | 
0 | 
| T140 | 
11567 | 
25 | 
0 | 
0 | 
| T141 | 
7372 | 
139 | 
0 | 
0 | 
| T142 | 
14151 | 
31 | 
0 | 
0 | 
| T143 | 
20621 | 
35 | 
0 | 
0 | 
| T144 | 
21410 | 
79 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
21193 | 
0 | 
0 | 
| T52 | 
104737 | 
1907 | 
0 | 
0 | 
| T71 | 
2270 | 
6 | 
0 | 
0 | 
| T86 | 
98789 | 
1453 | 
0 | 
0 | 
| T98 | 
96953 | 
919 | 
0 | 
0 | 
| T104 | 
9285 | 
145 | 
0 | 
0 | 
| T140 | 
11567 | 
14 | 
0 | 
0 | 
| T141 | 
7372 | 
290 | 
0 | 
0 | 
| T142 | 
14151 | 
31 | 
0 | 
0 | 
| T143 | 
20621 | 
110 | 
0 | 
0 | 
| T144 | 
21410 | 
83 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
20402 | 
0 | 
0 | 
| T52 | 
104737 | 
1635 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
1774 | 
0 | 
0 | 
| T98 | 
96953 | 
983 | 
0 | 
0 | 
| T104 | 
9285 | 
53 | 
0 | 
0 | 
| T140 | 
11567 | 
23 | 
0 | 
0 | 
| T141 | 
7372 | 
14 | 
0 | 
0 | 
| T142 | 
14151 | 
26 | 
0 | 
0 | 
| T143 | 
20621 | 
63 | 
0 | 
0 | 
| T144 | 
21410 | 
34 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
19975 | 
0 | 
0 | 
| T52 | 
104737 | 
1601 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
1445 | 
0 | 
0 | 
| T98 | 
96953 | 
1052 | 
0 | 
0 | 
| T104 | 
9285 | 
4 | 
0 | 
0 | 
| T140 | 
11567 | 
9 | 
0 | 
0 | 
| T141 | 
7372 | 
1 | 
0 | 
0 | 
| T142 | 
14151 | 
28 | 
0 | 
0 | 
| T143 | 
20621 | 
52 | 
0 | 
0 | 
| T144 | 
21410 | 
38 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
20426 | 
0 | 
0 | 
| T52 | 
104737 | 
2083 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
1529 | 
0 | 
0 | 
| T98 | 
96953 | 
1216 | 
0 | 
0 | 
| T104 | 
9285 | 
73 | 
0 | 
0 | 
| T140 | 
11567 | 
46 | 
0 | 
0 | 
| T141 | 
7372 | 
130 | 
0 | 
0 | 
| T142 | 
14151 | 
41 | 
0 | 
0 | 
| T143 | 
20621 | 
51 | 
0 | 
0 | 
| T144 | 
21410 | 
49 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
18508 | 
0 | 
0 | 
| T52 | 
104737 | 
1832 | 
0 | 
0 | 
| T86 | 
98789 | 
1803 | 
0 | 
0 | 
| T98 | 
96953 | 
719 | 
0 | 
0 | 
| T99 | 
100674 | 
1656 | 
0 | 
0 | 
| T104 | 
9285 | 
6 | 
0 | 
0 | 
| T140 | 
11567 | 
8 | 
0 | 
0 | 
| T141 | 
7372 | 
258 | 
0 | 
0 | 
| T142 | 
14151 | 
48 | 
0 | 
0 | 
| T143 | 
20621 | 
105 | 
0 | 
0 | 
| T144 | 
21410 | 
61 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
22057 | 
0 | 
0 | 
| T52 | 
104737 | 
2402 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
2491 | 
0 | 
0 | 
| T98 | 
96953 | 
979 | 
0 | 
0 | 
| T104 | 
9285 | 
64 | 
0 | 
0 | 
| T140 | 
11567 | 
30 | 
0 | 
0 | 
| T141 | 
7372 | 
135 | 
0 | 
0 | 
| T142 | 
14151 | 
46 | 
0 | 
0 | 
| T143 | 
20621 | 
64 | 
0 | 
0 | 
| T144 | 
21410 | 
72 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9599 | 
0 | 
0 | 
| T52 | 
104737 | 
612 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
852 | 
0 | 
0 | 
| T98 | 
96953 | 
530 | 
0 | 
0 | 
| T104 | 
9285 | 
22 | 
0 | 
0 | 
| T140 | 
11567 | 
35 | 
0 | 
0 | 
| T141 | 
7372 | 
111 | 
0 | 
0 | 
| T142 | 
14151 | 
43 | 
0 | 
0 | 
| T143 | 
20621 | 
87 | 
0 | 
0 | 
| T144 | 
21410 | 
68 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9987 | 
0 | 
0 | 
| T52 | 
104737 | 
904 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
776 | 
0 | 
0 | 
| T98 | 
96953 | 
499 | 
0 | 
0 | 
| T104 | 
9285 | 
42 | 
0 | 
0 | 
| T140 | 
11567 | 
21 | 
0 | 
0 | 
| T141 | 
7372 | 
48 | 
0 | 
0 | 
| T142 | 
14151 | 
64 | 
0 | 
0 | 
| T143 | 
20621 | 
80 | 
0 | 
0 | 
| T144 | 
21410 | 
76 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9840 | 
0 | 
0 | 
| T52 | 
104737 | 
541 | 
0 | 
0 | 
| T71 | 
2270 | 
8 | 
0 | 
0 | 
| T86 | 
98789 | 
936 | 
0 | 
0 | 
| T98 | 
96953 | 
444 | 
0 | 
0 | 
| T104 | 
9285 | 
99 | 
0 | 
0 | 
| T140 | 
11567 | 
24 | 
0 | 
0 | 
| T141 | 
7372 | 
70 | 
0 | 
0 | 
| T142 | 
14151 | 
62 | 
0 | 
0 | 
| T143 | 
20621 | 
35 | 
0 | 
0 | 
| T144 | 
21410 | 
35 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9948 | 
0 | 
0 | 
| T52 | 
104737 | 
698 | 
0 | 
0 | 
| T86 | 
98789 | 
971 | 
0 | 
0 | 
| T98 | 
96953 | 
515 | 
0 | 
0 | 
| T99 | 
100674 | 
866 | 
0 | 
0 | 
| T104 | 
9285 | 
24 | 
0 | 
0 | 
| T140 | 
11567 | 
12 | 
0 | 
0 | 
| T141 | 
7372 | 
3 | 
0 | 
0 | 
| T142 | 
14151 | 
59 | 
0 | 
0 | 
| T143 | 
20621 | 
79 | 
0 | 
0 | 
| T144 | 
21410 | 
72 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
8974 | 
0 | 
0 | 
| T52 | 
104737 | 
640 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
704 | 
0 | 
0 | 
| T98 | 
96953 | 
419 | 
0 | 
0 | 
| T104 | 
9285 | 
30 | 
0 | 
0 | 
| T140 | 
11567 | 
21 | 
0 | 
0 | 
| T141 | 
7372 | 
107 | 
0 | 
0 | 
| T142 | 
14151 | 
26 | 
0 | 
0 | 
| T143 | 
20621 | 
50 | 
0 | 
0 | 
| T144 | 
21410 | 
70 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9561 | 
0 | 
0 | 
| T52 | 
104737 | 
786 | 
0 | 
0 | 
| T86 | 
98789 | 
508 | 
0 | 
0 | 
| T98 | 
96953 | 
380 | 
0 | 
0 | 
| T99 | 
100674 | 
917 | 
0 | 
0 | 
| T104 | 
9285 | 
30 | 
0 | 
0 | 
| T140 | 
11567 | 
12 | 
0 | 
0 | 
| T141 | 
7372 | 
93 | 
0 | 
0 | 
| T142 | 
14151 | 
85 | 
0 | 
0 | 
| T143 | 
20621 | 
21 | 
0 | 
0 | 
| T144 | 
21410 | 
28 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9849 | 
0 | 
0 | 
| T52 | 
104737 | 
741 | 
0 | 
0 | 
| T71 | 
2270 | 
7 | 
0 | 
0 | 
| T86 | 
98789 | 
787 | 
0 | 
0 | 
| T98 | 
96953 | 
510 | 
0 | 
0 | 
| T99 | 
100674 | 
937 | 
0 | 
0 | 
| T104 | 
9285 | 
51 | 
0 | 
0 | 
| T141 | 
7372 | 
113 | 
0 | 
0 | 
| T142 | 
14151 | 
34 | 
0 | 
0 | 
| T143 | 
20621 | 
23 | 
0 | 
0 | 
| T144 | 
21410 | 
43 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
10010 | 
0 | 
0 | 
| T52 | 
104737 | 
871 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
1004 | 
0 | 
0 | 
| T98 | 
96953 | 
414 | 
0 | 
0 | 
| T104 | 
9285 | 
17 | 
0 | 
0 | 
| T140 | 
11567 | 
37 | 
0 | 
0 | 
| T141 | 
7372 | 
42 | 
0 | 
0 | 
| T142 | 
14151 | 
14 | 
0 | 
0 | 
| T143 | 
20621 | 
80 | 
0 | 
0 | 
| T144 | 
21410 | 
42 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9182 | 
0 | 
0 | 
| T52 | 
104737 | 
692 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
672 | 
0 | 
0 | 
| T98 | 
96953 | 
349 | 
0 | 
0 | 
| T104 | 
9285 | 
28 | 
0 | 
0 | 
| T140 | 
11567 | 
33 | 
0 | 
0 | 
| T141 | 
7372 | 
108 | 
0 | 
0 | 
| T142 | 
14151 | 
43 | 
0 | 
0 | 
| T143 | 
20621 | 
128 | 
0 | 
0 | 
| T144 | 
21410 | 
56 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9593 | 
0 | 
0 | 
| T52 | 
104737 | 
824 | 
0 | 
0 | 
| T86 | 
98789 | 
461 | 
0 | 
0 | 
| T98 | 
96953 | 
410 | 
0 | 
0 | 
| T99 | 
100674 | 
787 | 
0 | 
0 | 
| T104 | 
9285 | 
62 | 
0 | 
0 | 
| T140 | 
11567 | 
36 | 
0 | 
0 | 
| T141 | 
7372 | 
7 | 
0 | 
0 | 
| T142 | 
14151 | 
7 | 
0 | 
0 | 
| T143 | 
20621 | 
59 | 
0 | 
0 | 
| T144 | 
21410 | 
69 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9346 | 
0 | 
0 | 
| T52 | 
104737 | 
761 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
900 | 
0 | 
0 | 
| T98 | 
96953 | 
519 | 
0 | 
0 | 
| T104 | 
9285 | 
61 | 
0 | 
0 | 
| T140 | 
11567 | 
7 | 
0 | 
0 | 
| T141 | 
7372 | 
71 | 
0 | 
0 | 
| T142 | 
14151 | 
47 | 
0 | 
0 | 
| T143 | 
20621 | 
67 | 
0 | 
0 | 
| T144 | 
21410 | 
47 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9971 | 
0 | 
0 | 
| T52 | 
104737 | 
904 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
905 | 
0 | 
0 | 
| T98 | 
96953 | 
557 | 
0 | 
0 | 
| T104 | 
9285 | 
54 | 
0 | 
0 | 
| T140 | 
11567 | 
18 | 
0 | 
0 | 
| T141 | 
7372 | 
11 | 
0 | 
0 | 
| T142 | 
14151 | 
55 | 
0 | 
0 | 
| T143 | 
20621 | 
75 | 
0 | 
0 | 
| T144 | 
21410 | 
47 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
10076 | 
0 | 
0 | 
| T52 | 
104737 | 
700 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
907 | 
0 | 
0 | 
| T98 | 
96953 | 
420 | 
0 | 
0 | 
| T104 | 
9285 | 
12 | 
0 | 
0 | 
| T140 | 
11567 | 
33 | 
0 | 
0 | 
| T141 | 
7372 | 
56 | 
0 | 
0 | 
| T142 | 
14151 | 
30 | 
0 | 
0 | 
| T143 | 
20621 | 
112 | 
0 | 
0 | 
| T144 | 
21410 | 
48 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
8764 | 
0 | 
0 | 
| T52 | 
104737 | 
501 | 
0 | 
0 | 
| T71 | 
2270 | 
5 | 
0 | 
0 | 
| T86 | 
98789 | 
762 | 
0 | 
0 | 
| T98 | 
96953 | 
445 | 
0 | 
0 | 
| T104 | 
9285 | 
24 | 
0 | 
0 | 
| T140 | 
11567 | 
9 | 
0 | 
0 | 
| T141 | 
7372 | 
49 | 
0 | 
0 | 
| T142 | 
14151 | 
35 | 
0 | 
0 | 
| T143 | 
20621 | 
36 | 
0 | 
0 | 
| T144 | 
21410 | 
114 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9114 | 
0 | 
0 | 
| T52 | 
104737 | 
705 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
715 | 
0 | 
0 | 
| T98 | 
96953 | 
393 | 
0 | 
0 | 
| T104 | 
9285 | 
86 | 
0 | 
0 | 
| T140 | 
11567 | 
30 | 
0 | 
0 | 
| T141 | 
7372 | 
42 | 
0 | 
0 | 
| T142 | 
14151 | 
8 | 
0 | 
0 | 
| T143 | 
20621 | 
71 | 
0 | 
0 | 
| T144 | 
21410 | 
94 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9863 | 
0 | 
0 | 
| T52 | 
104737 | 
886 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
968 | 
0 | 
0 | 
| T98 | 
96953 | 
458 | 
0 | 
0 | 
| T104 | 
9285 | 
41 | 
0 | 
0 | 
| T140 | 
11567 | 
31 | 
0 | 
0 | 
| T141 | 
7372 | 
105 | 
0 | 
0 | 
| T142 | 
14151 | 
22 | 
0 | 
0 | 
| T143 | 
20621 | 
64 | 
0 | 
0 | 
| T144 | 
21410 | 
109 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9505 | 
0 | 
0 | 
| T52 | 
104737 | 
701 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
705 | 
0 | 
0 | 
| T98 | 
96953 | 
393 | 
0 | 
0 | 
| T104 | 
9285 | 
40 | 
0 | 
0 | 
| T140 | 
11567 | 
10 | 
0 | 
0 | 
| T141 | 
7372 | 
6 | 
0 | 
0 | 
| T142 | 
14151 | 
46 | 
0 | 
0 | 
| T143 | 
20621 | 
113 | 
0 | 
0 | 
| T144 | 
21410 | 
116 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
10026 | 
0 | 
0 | 
| T52 | 
104737 | 
1058 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
890 | 
0 | 
0 | 
| T98 | 
96953 | 
473 | 
0 | 
0 | 
| T104 | 
9285 | 
31 | 
0 | 
0 | 
| T140 | 
11567 | 
59 | 
0 | 
0 | 
| T141 | 
7372 | 
95 | 
0 | 
0 | 
| T142 | 
14151 | 
51 | 
0 | 
0 | 
| T143 | 
20621 | 
96 | 
0 | 
0 | 
| T144 | 
21410 | 
36 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9143 | 
0 | 
0 | 
| T52 | 
104737 | 
784 | 
0 | 
0 | 
| T86 | 
98789 | 
621 | 
0 | 
0 | 
| T98 | 
96953 | 
432 | 
0 | 
0 | 
| T99 | 
100674 | 
984 | 
0 | 
0 | 
| T104 | 
9285 | 
33 | 
0 | 
0 | 
| T140 | 
11567 | 
23 | 
0 | 
0 | 
| T141 | 
7372 | 
12 | 
0 | 
0 | 
| T142 | 
14151 | 
40 | 
0 | 
0 | 
| T143 | 
20621 | 
73 | 
0 | 
0 | 
| T144 | 
21410 | 
41 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9939 | 
0 | 
0 | 
| T52 | 
104737 | 
861 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
845 | 
0 | 
0 | 
| T98 | 
96953 | 
469 | 
0 | 
0 | 
| T104 | 
9285 | 
87 | 
0 | 
0 | 
| T140 | 
11567 | 
13 | 
0 | 
0 | 
| T141 | 
7372 | 
44 | 
0 | 
0 | 
| T142 | 
14151 | 
74 | 
0 | 
0 | 
| T143 | 
20621 | 
100 | 
0 | 
0 | 
| T144 | 
21410 | 
54 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
10117 | 
0 | 
0 | 
| T52 | 
104737 | 
1018 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
911 | 
0 | 
0 | 
| T98 | 
96953 | 
331 | 
0 | 
0 | 
| T104 | 
9285 | 
28 | 
0 | 
0 | 
| T140 | 
11567 | 
24 | 
0 | 
0 | 
| T141 | 
7372 | 
10 | 
0 | 
0 | 
| T142 | 
14151 | 
76 | 
0 | 
0 | 
| T143 | 
20621 | 
60 | 
0 | 
0 | 
| T144 | 
21410 | 
79 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
8753 | 
0 | 
0 | 
| T52 | 
104737 | 
744 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
899 | 
0 | 
0 | 
| T98 | 
96953 | 
487 | 
0 | 
0 | 
| T104 | 
9285 | 
16 | 
0 | 
0 | 
| T140 | 
11567 | 
8 | 
0 | 
0 | 
| T141 | 
7372 | 
7 | 
0 | 
0 | 
| T142 | 
14151 | 
38 | 
0 | 
0 | 
| T143 | 
20621 | 
86 | 
0 | 
0 | 
| T144 | 
21410 | 
75 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9101 | 
0 | 
0 | 
| T52 | 
104737 | 
771 | 
0 | 
0 | 
| T71 | 
2270 | 
6 | 
0 | 
0 | 
| T86 | 
98789 | 
497 | 
0 | 
0 | 
| T98 | 
96953 | 
363 | 
0 | 
0 | 
| T104 | 
9285 | 
64 | 
0 | 
0 | 
| T140 | 
11567 | 
10 | 
0 | 
0 | 
| T141 | 
7372 | 
14 | 
0 | 
0 | 
| T142 | 
14151 | 
40 | 
0 | 
0 | 
| T143 | 
20621 | 
53 | 
0 | 
0 | 
| T144 | 
21410 | 
62 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
9493 | 
0 | 
0 | 
| T52 | 
104737 | 
629 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
867 | 
0 | 
0 | 
| T98 | 
96953 | 
490 | 
0 | 
0 | 
| T104 | 
9285 | 
58 | 
0 | 
0 | 
| T140 | 
11567 | 
9 | 
0 | 
0 | 
| T141 | 
7372 | 
53 | 
0 | 
0 | 
| T142 | 
14151 | 
43 | 
0 | 
0 | 
| T143 | 
20621 | 
51 | 
0 | 
0 | 
| T144 | 
21410 | 
37 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3472 | 
0 | 
0 | 
| T52 | 
104737 | 
132 | 
0 | 
0 | 
| T86 | 
98789 | 
188 | 
0 | 
0 | 
| T98 | 
96953 | 
101 | 
0 | 
0 | 
| T99 | 
100674 | 
199 | 
0 | 
0 | 
| T104 | 
9285 | 
1 | 
0 | 
0 | 
| T140 | 
11567 | 
30 | 
0 | 
0 | 
| T141 | 
7372 | 
14 | 
0 | 
0 | 
| T142 | 
14151 | 
47 | 
0 | 
0 | 
| T143 | 
20621 | 
58 | 
0 | 
0 | 
| T144 | 
21410 | 
85 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3332 | 
0 | 
0 | 
| T52 | 
104737 | 
162 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
187 | 
0 | 
0 | 
| T98 | 
96953 | 
99 | 
0 | 
0 | 
| T104 | 
9285 | 
8 | 
0 | 
0 | 
| T140 | 
11567 | 
20 | 
0 | 
0 | 
| T141 | 
7372 | 
9 | 
0 | 
0 | 
| T142 | 
14151 | 
38 | 
0 | 
0 | 
| T143 | 
20621 | 
43 | 
0 | 
0 | 
| T144 | 
21410 | 
47 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3469 | 
0 | 
0 | 
| T52 | 
104737 | 
175 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
181 | 
0 | 
0 | 
| T98 | 
96953 | 
95 | 
0 | 
0 | 
| T104 | 
9285 | 
10 | 
0 | 
0 | 
| T140 | 
11567 | 
11 | 
0 | 
0 | 
| T141 | 
7372 | 
23 | 
0 | 
0 | 
| T142 | 
14151 | 
32 | 
0 | 
0 | 
| T143 | 
20621 | 
39 | 
0 | 
0 | 
| T144 | 
21410 | 
125 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3433 | 
0 | 
0 | 
| T50 | 
17223 | 
4 | 
0 | 
0 | 
| T52 | 
104737 | 
166 | 
0 | 
0 | 
| T86 | 
98789 | 
193 | 
0 | 
0 | 
| T98 | 
96953 | 
116 | 
0 | 
0 | 
| T104 | 
9285 | 
18 | 
0 | 
0 | 
| T140 | 
11567 | 
31 | 
0 | 
0 | 
| T141 | 
7372 | 
12 | 
0 | 
0 | 
| T142 | 
14151 | 
40 | 
0 | 
0 | 
| T143 | 
20621 | 
32 | 
0 | 
0 | 
| T144 | 
21410 | 
52 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
4537 | 
0 | 
0 | 
| T52 | 
104737 | 
283 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
292 | 
0 | 
0 | 
| T98 | 
96953 | 
201 | 
0 | 
0 | 
| T104 | 
9285 | 
4 | 
0 | 
0 | 
| T140 | 
11567 | 
35 | 
0 | 
0 | 
| T141 | 
7372 | 
16 | 
0 | 
0 | 
| T142 | 
14151 | 
72 | 
0 | 
0 | 
| T143 | 
20621 | 
123 | 
0 | 
0 | 
| T144 | 
21410 | 
65 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
7361 | 
0 | 
0 | 
| T16 | 
123816 | 
22 | 
0 | 
0 | 
| T19 | 
0 | 
11 | 
0 | 
0 | 
| T21 | 
0 | 
20 | 
0 | 
0 | 
| T31 | 
0 | 
18 | 
0 | 
0 | 
| T36 | 
0 | 
23 | 
0 | 
0 | 
| T45 | 
0 | 
10 | 
0 | 
0 | 
| T46 | 
0 | 
12 | 
0 | 
0 | 
| T84 | 
122249 | 
0 | 
0 | 
0 | 
| T118 | 
998 | 
0 | 
0 | 
0 | 
| T119 | 
143086 | 
0 | 
0 | 
0 | 
| T120 | 
300248 | 
0 | 
0 | 
0 | 
| T121 | 
229192 | 
0 | 
0 | 
0 | 
| T122 | 
520344 | 
0 | 
0 | 
0 | 
| T123 | 
1647 | 
0 | 
0 | 
0 | 
| T124 | 
14748 | 
0 | 
0 | 
0 | 
| T125 | 
69912 | 
0 | 
0 | 
0 | 
| T145 | 
0 | 
18 | 
0 | 
0 | 
| T146 | 
0 | 
127 | 
0 | 
0 | 
| T147 | 
0 | 
44 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3269 | 
0 | 
0 | 
| T52 | 
104737 | 
139 | 
0 | 
0 | 
| T71 | 
2270 | 
6 | 
0 | 
0 | 
| T86 | 
98789 | 
175 | 
0 | 
0 | 
| T98 | 
96953 | 
74 | 
0 | 
0 | 
| T104 | 
9285 | 
2 | 
0 | 
0 | 
| T140 | 
11567 | 
19 | 
0 | 
0 | 
| T141 | 
7372 | 
20 | 
0 | 
0 | 
| T142 | 
14151 | 
32 | 
0 | 
0 | 
| T143 | 
20621 | 
44 | 
0 | 
0 | 
| T144 | 
21410 | 
85 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3118 | 
0 | 
0 | 
| T52 | 
104737 | 
135 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
203 | 
0 | 
0 | 
| T98 | 
96953 | 
84 | 
0 | 
0 | 
| T104 | 
9285 | 
5 | 
0 | 
0 | 
| T140 | 
11567 | 
16 | 
0 | 
0 | 
| T141 | 
7372 | 
8 | 
0 | 
0 | 
| T142 | 
14151 | 
27 | 
0 | 
0 | 
| T143 | 
20621 | 
41 | 
0 | 
0 | 
| T144 | 
21410 | 
69 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2889 | 
0 | 
0 | 
| T52 | 
104737 | 
120 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
133 | 
0 | 
0 | 
| T98 | 
96953 | 
51 | 
0 | 
0 | 
| T104 | 
9285 | 
9 | 
0 | 
0 | 
| T140 | 
11567 | 
41 | 
0 | 
0 | 
| T141 | 
7372 | 
11 | 
0 | 
0 | 
| T142 | 
14151 | 
52 | 
0 | 
0 | 
| T143 | 
20621 | 
47 | 
0 | 
0 | 
| T144 | 
21410 | 
71 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2858 | 
0 | 
0 | 
| T52 | 
104737 | 
140 | 
0 | 
0 | 
| T71 | 
2270 | 
2 | 
0 | 
0 | 
| T86 | 
98789 | 
151 | 
0 | 
0 | 
| T98 | 
96953 | 
73 | 
0 | 
0 | 
| T104 | 
9285 | 
1 | 
0 | 
0 | 
| T140 | 
11567 | 
55 | 
0 | 
0 | 
| T141 | 
7372 | 
12 | 
0 | 
0 | 
| T142 | 
14151 | 
36 | 
0 | 
0 | 
| T143 | 
20621 | 
66 | 
0 | 
0 | 
| T144 | 
21410 | 
90 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2709 | 
0 | 
0 | 
| T52 | 
104737 | 
98 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
106 | 
0 | 
0 | 
| T98 | 
96953 | 
60 | 
0 | 
0 | 
| T104 | 
9285 | 
5 | 
0 | 
0 | 
| T140 | 
11567 | 
23 | 
0 | 
0 | 
| T141 | 
7372 | 
10 | 
0 | 
0 | 
| T142 | 
14151 | 
70 | 
0 | 
0 | 
| T143 | 
20621 | 
47 | 
0 | 
0 | 
| T144 | 
21410 | 
18 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2769 | 
0 | 
0 | 
| T52 | 
104737 | 
95 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
120 | 
0 | 
0 | 
| T98 | 
96953 | 
51 | 
0 | 
0 | 
| T104 | 
9285 | 
6 | 
0 | 
0 | 
| T140 | 
11567 | 
8 | 
0 | 
0 | 
| T141 | 
7372 | 
11 | 
0 | 
0 | 
| T142 | 
14151 | 
32 | 
0 | 
0 | 
| T143 | 
20621 | 
48 | 
0 | 
0 | 
| T144 | 
21410 | 
95 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
4195 | 
0 | 
0 | 
| T52 | 
104737 | 
168 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
246 | 
0 | 
0 | 
| T98 | 
96953 | 
132 | 
0 | 
0 | 
| T104 | 
9285 | 
23 | 
0 | 
0 | 
| T140 | 
11567 | 
6 | 
0 | 
0 | 
| T141 | 
7372 | 
21 | 
0 | 
0 | 
| T142 | 
14151 | 
29 | 
0 | 
0 | 
| T143 | 
20621 | 
62 | 
0 | 
0 | 
| T144 | 
21410 | 
53 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2875 | 
0 | 
0 | 
| T52 | 
104737 | 
118 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
125 | 
0 | 
0 | 
| T98 | 
96953 | 
61 | 
0 | 
0 | 
| T104 | 
9285 | 
2 | 
0 | 
0 | 
| T140 | 
11567 | 
22 | 
0 | 
0 | 
| T141 | 
7372 | 
9 | 
0 | 
0 | 
| T142 | 
14151 | 
35 | 
0 | 
0 | 
| T143 | 
20621 | 
31 | 
0 | 
0 | 
| T144 | 
21410 | 
93 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
5221 | 
0 | 
0 | 
| T52 | 
104737 | 
371 | 
0 | 
0 | 
| T71 | 
2270 | 
7 | 
0 | 
0 | 
| T86 | 
98789 | 
281 | 
0 | 
0 | 
| T98 | 
96953 | 
181 | 
0 | 
0 | 
| T104 | 
9285 | 
5 | 
0 | 
0 | 
| T140 | 
11567 | 
31 | 
0 | 
0 | 
| T141 | 
7372 | 
24 | 
0 | 
0 | 
| T142 | 
14151 | 
33 | 
0 | 
0 | 
| T143 | 
20621 | 
44 | 
0 | 
0 | 
| T144 | 
21410 | 
67 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
3380 | 
0 | 
0 | 
| T52 | 
104737 | 
155 | 
0 | 
0 | 
| T71 | 
2270 | 
1 | 
0 | 
0 | 
| T86 | 
98789 | 
174 | 
0 | 
0 | 
| T98 | 
96953 | 
60 | 
0 | 
0 | 
| T104 | 
9285 | 
14 | 
0 | 
0 | 
| T140 | 
11567 | 
23 | 
0 | 
0 | 
| T141 | 
7372 | 
16 | 
0 | 
0 | 
| T142 | 
14151 | 
47 | 
0 | 
0 | 
| T143 | 
20621 | 
47 | 
0 | 
0 | 
| T144 | 
21410 | 
79 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2862 | 
0 | 
0 | 
| T52 | 
104737 | 
146 | 
0 | 
0 | 
| T71 | 
2270 | 
5 | 
0 | 
0 | 
| T86 | 
98789 | 
122 | 
0 | 
0 | 
| T98 | 
96953 | 
90 | 
0 | 
0 | 
| T104 | 
9285 | 
4 | 
0 | 
0 | 
| T140 | 
11567 | 
24 | 
0 | 
0 | 
| T141 | 
7372 | 
9 | 
0 | 
0 | 
| T142 | 
14151 | 
58 | 
0 | 
0 | 
| T143 | 
20621 | 
56 | 
0 | 
0 | 
| T144 | 
21410 | 
40 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2844 | 
0 | 
0 | 
| T52 | 
104737 | 
93 | 
0 | 
0 | 
| T71 | 
2270 | 
5 | 
0 | 
0 | 
| T86 | 
98789 | 
123 | 
0 | 
0 | 
| T98 | 
96953 | 
87 | 
0 | 
0 | 
| T104 | 
9285 | 
1 | 
0 | 
0 | 
| T140 | 
11567 | 
17 | 
0 | 
0 | 
| T141 | 
7372 | 
3 | 
0 | 
0 | 
| T142 | 
14151 | 
11 | 
0 | 
0 | 
| T143 | 
20621 | 
71 | 
0 | 
0 | 
| T144 | 
21410 | 
85 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2746 | 
0 | 
0 | 
| T52 | 
104737 | 
122 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
136 | 
0 | 
0 | 
| T98 | 
96953 | 
72 | 
0 | 
0 | 
| T99 | 
100674 | 
116 | 
0 | 
0 | 
| T140 | 
11567 | 
33 | 
0 | 
0 | 
| T141 | 
7372 | 
12 | 
0 | 
0 | 
| T142 | 
14151 | 
30 | 
0 | 
0 | 
| T143 | 
20621 | 
66 | 
0 | 
0 | 
| T144 | 
21410 | 
61 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2691 | 
0 | 
0 | 
| T52 | 
104737 | 
105 | 
0 | 
0 | 
| T71 | 
2270 | 
4 | 
0 | 
0 | 
| T86 | 
98789 | 
102 | 
0 | 
0 | 
| T98 | 
96953 | 
85 | 
0 | 
0 | 
| T104 | 
9285 | 
5 | 
0 | 
0 | 
| T140 | 
11567 | 
34 | 
0 | 
0 | 
| T141 | 
7372 | 
4 | 
0 | 
0 | 
| T142 | 
14151 | 
14 | 
0 | 
0 | 
| T143 | 
20621 | 
59 | 
0 | 
0 | 
| T144 | 
21410 | 
57 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2938 | 
0 | 
0 | 
| T52 | 
104737 | 
109 | 
0 | 
0 | 
| T71 | 
2270 | 
9 | 
0 | 
0 | 
| T86 | 
98789 | 
125 | 
0 | 
0 | 
| T98 | 
96953 | 
71 | 
0 | 
0 | 
| T104 | 
9285 | 
10 | 
0 | 
0 | 
| T140 | 
11567 | 
18 | 
0 | 
0 | 
| T141 | 
7372 | 
12 | 
0 | 
0 | 
| T142 | 
14151 | 
9 | 
0 | 
0 | 
| T143 | 
20621 | 
49 | 
0 | 
0 | 
| T144 | 
21410 | 
66 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
479340252 | 
2746 | 
0 | 
0 | 
| T52 | 
104737 | 
112 | 
0 | 
0 | 
| T71 | 
2270 | 
3 | 
0 | 
0 | 
| T86 | 
98789 | 
100 | 
0 | 
0 | 
| T98 | 
96953 | 
59 | 
0 | 
0 | 
| T99 | 
100674 | 
103 | 
0 | 
0 | 
| T104 | 
9285 | 
10 | 
0 | 
0 | 
| T140 | 
11567 | 
15 | 
0 | 
0 | 
| T142 | 
14151 | 
27 | 
0 | 
0 | 
| T143 | 
20621 | 
45 | 
0 | 
0 | 
| T144 | 
21410 | 
87 | 
0 | 
0 |