Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3817416	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4380734

1

T1

2994

T2

5704

T3

3782

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4537929	1			T1	524		T2	4129		T3	5660
values[0x0]	1828848	1			T1	1338		T2	1778		T3	458
values[0x1]	1831373	1			T1	1312		T2	1745		T3	464

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2704892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5493258

1

T1

3029

T2

6094

T3

4336

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29930	1			T1	17		T3	27		T4	4
valid_sources[0x01]	32498	1			T1	7		T2	1		T3	21
valid_sources[0x02]	40878	1			T1	8		T3	32		T4	4
valid_sources[0x03]	38862	1			T1	26		T3	24		T4	2
valid_sources[0x04]	29957	1			T1	44		T2	1		T3	35
valid_sources[0x05]	31721	1			T3	20		T4	1		T5	3
valid_sources[0x06]	41943	1			T3	36		T4	5		T5	1
valid_sources[0x07]	29065	1			T3	23		T4	2		T5	8
valid_sources[0x08]	30931	1			T1	94		T3	31		T4	7
valid_sources[0x09]	29655	1			T3	35		T4	1		T5	4
valid_sources[0x0a]	30393	1			T1	17		T3	19		T4	6
valid_sources[0x0b]	31056	1			T1	8		T3	24		T4	3
valid_sources[0x0c]	32804	1			T1	29		T3	6		T4	1
valid_sources[0x0d]	39254	1			T1	6		T3	18		T4	2
valid_sources[0x0e]	32652	1			T3	33		T4	7		T5	3
valid_sources[0x0f]	36012	1			T1	24		T3	32		T4	10
valid_sources[0x10]	30480	1			T3	13		T4	3		T7	74
valid_sources[0x11]	30405	1			T1	22		T3	27		T4	8
valid_sources[0x12]	30654	1			T1	2		T3	1		T4	2
valid_sources[0x13]	30535	1			T1	9		T3	21		T4	6
valid_sources[0x14]	32255	1			T1	12		T3	21		T5	3
valid_sources[0x15]	30951	1			T1	2		T3	21		T7	64
valid_sources[0x16]	29765	1			T1	1		T3	52		T4	3
valid_sources[0x17]	32136	1			T3	17		T4	3		T5	6
valid_sources[0x18]	32196	1			T1	10		T3	19		T4	2
valid_sources[0x19]	31543	1			T1	18		T3	28		T4	4
valid_sources[0x1a]	30252	1			T3	26		T4	3		T5	1
valid_sources[0x1b]	30664	1			T1	4		T3	43		T4	1
valid_sources[0x1c]	30412	1			T3	29		T4	3		T7	61
valid_sources[0x1d]	34338	1			T3	42		T4	5		T5	1
valid_sources[0x1e]	37705	1			T1	22		T3	16		T4	2
valid_sources[0x1f]	32984	1			T3	36		T4	8		T5	1
valid_sources[0x20]	28896	1			T1	4		T3	14		T4	2
valid_sources[0x21]	30391	1			T1	29		T2	1		T3	33
valid_sources[0x22]	32269	1			T1	18		T3	42		T4	7
valid_sources[0x23]	29301	1			T1	21		T3	13		T4	8
valid_sources[0x24]	32390	1			T3	31		T4	3		T5	14
valid_sources[0x25]	34092	1			T1	36		T3	47		T4	4
valid_sources[0x26]	33833	1			T1	23		T3	18		T4	3
valid_sources[0x27]	28709	1			T1	20		T3	22		T4	2
valid_sources[0x28]	29775	1			T1	2		T3	12		T4	5
valid_sources[0x29]	34186	1			T1	36		T3	12		T4	3
valid_sources[0x2a]	29078	1			T1	3		T3	21		T4	5
valid_sources[0x2b]	77651	1			T3	24		T4	2		T5	1
valid_sources[0x2c]	31985	1			T1	1		T3	20		T4	6
valid_sources[0x2d]	30833	1			T1	34		T3	25		T4	4
valid_sources[0x2e]	29967	1			T1	40		T2	1		T3	23
valid_sources[0x2f]	30802	1			T1	5		T3	29		T4	1
valid_sources[0x30]	32244	1			T1	18		T3	32		T4	6
valid_sources[0x31]	30804	1			T1	13		T3	19		T4	6
valid_sources[0x32]	35984	1			T1	20		T2	1		T3	13
valid_sources[0x33]	30661	1			T1	5		T3	19		T4	6
valid_sources[0x34]	29872	1			T1	19		T3	36		T4	4
valid_sources[0x35]	33484	1			T1	8		T3	22		T4	2
valid_sources[0x36]	31334	1			T1	1		T3	26		T4	2
valid_sources[0x37]	33498	1			T3	33		T4	4		T5	1
valid_sources[0x38]	30490	1			T1	16		T3	18		T4	3
valid_sources[0x39]	37478	1			T1	28		T3	18		T4	4
valid_sources[0x3a]	33080	1			T3	20		T4	6		T5	1
valid_sources[0x3b]	31638	1			T3	10		T4	3		T5	2
valid_sources[0x3c]	30351	1			T1	2		T3	26		T4	2
valid_sources[0x3d]	33329	1			T1	6		T2	979		T3	22
valid_sources[0x3e]	30153	1			T1	27		T3	32		T4	3
valid_sources[0x3f]	31623	1			T1	47		T3	29		T4	2
valid_sources[0x40]	29558	1			T1	17		T3	19		T4	6
valid_sources[0x41]	32342	1			T3	37		T4	1		T5	4
valid_sources[0x42]	31318	1			T3	14		T5	6		T7	66
valid_sources[0x43]	31170	1			T1	1		T3	37		T4	2
valid_sources[0x44]	29387	1			T1	46		T2	1		T3	28
valid_sources[0x45]	30759	1			T1	9		T3	15		T4	4
valid_sources[0x46]	29769	1			T1	9		T3	37		T4	6
valid_sources[0x47]	31190	1			T1	6		T3	21		T4	4
valid_sources[0x48]	34794	1			T1	15		T3	10		T4	3
valid_sources[0x49]	33350	1			T1	9		T3	13		T5	8
valid_sources[0x4a]	29012	1			T1	11		T3	15		T4	5
valid_sources[0x4b]	31396	1			T1	4		T3	28		T4	3
valid_sources[0x4c]	39632	1			T1	12		T3	22		T4	6
valid_sources[0x4d]	30609	1			T1	6		T2	35		T3	36
valid_sources[0x4e]	30065	1			T1	21		T3	36		T4	4
valid_sources[0x4f]	36307	1			T3	28		T4	5		T5	21
valid_sources[0x50]	34009	1			T1	2		T3	13		T4	2
valid_sources[0x51]	28966	1			T3	47		T4	1		T5	2
valid_sources[0x52]	35282	1			T3	19		T4	3		T5	8
valid_sources[0x53]	30278	1			T1	60		T3	14		T4	5
valid_sources[0x54]	31620	1			T1	16		T3	20		T4	5
valid_sources[0x55]	29440	1			T1	19		T3	60		T4	5
valid_sources[0x56]	31429	1			T1	11		T3	33		T4	7
valid_sources[0x57]	31015	1			T1	10		T3	55		T4	5
valid_sources[0x58]	32931	1			T1	10		T3	31		T4	2
valid_sources[0x59]	31244	1			T1	15		T3	37		T4	2
valid_sources[0x5a]	33003	1			T1	3		T3	21		T4	4
valid_sources[0x5b]	34608	1			T3	24		T4	10		T7	63
valid_sources[0x5c]	29014	1			T1	12		T2	1		T3	36
valid_sources[0x5d]	32028	1			T3	16		T4	5		T7	69
valid_sources[0x5e]	33197	1			T2	1		T3	14		T4	3
valid_sources[0x5f]	33555	1			T1	5		T3	26		T4	5
valid_sources[0x60]	38440	1			T3	44		T4	2		T5	1
valid_sources[0x61]	29006	1			T1	29		T3	27		T4	4
valid_sources[0x62]	30037	1			T1	1		T3	32		T4	8
valid_sources[0x63]	36685	1			T1	2		T3	22		T4	7
valid_sources[0x64]	31451	1			T1	1		T3	15		T4	4
valid_sources[0x65]	32389	1			T1	13		T3	29		T4	3
valid_sources[0x66]	32422	1			T1	13		T3	33		T4	2
valid_sources[0x67]	29990	1			T1	11		T3	28		T4	7
valid_sources[0x68]	32138	1			T1	13		T3	27		T4	2
valid_sources[0x69]	33599	1			T1	24		T3	29		T4	4
valid_sources[0x6a]	29774	1			T1	8		T3	29		T4	4
valid_sources[0x6b]	30453	1			T2	2		T3	29		T4	4
valid_sources[0x6c]	32421	1			T3	31		T4	8		T7	70
valid_sources[0x6d]	33033	1			T1	46		T3	40		T4	3
valid_sources[0x6e]	30893	1			T3	15		T4	4		T5	9
valid_sources[0x6f]	36213	1			T1	2		T2	1148		T3	55
valid_sources[0x70]	36908	1			T1	2		T3	12		T4	4
valid_sources[0x71]	33846	1			T1	7		T3	23		T4	5
valid_sources[0x72]	35281	1			T1	44		T3	25		T4	5
valid_sources[0x73]	32336	1			T1	3		T3	33		T4	6
valid_sources[0x74]	28293	1			T3	34		T4	2		T5	1
valid_sources[0x75]	31360	1			T1	14		T3	25		T4	1
valid_sources[0x76]	29599	1			T3	28		T4	2		T5	10
valid_sources[0x77]	30692	1			T1	8		T3	21		T4	2
valid_sources[0x78]	32879	1			T1	19		T3	15		T4	3
valid_sources[0x79]	31207	1			T1	17		T3	25		T4	1
valid_sources[0x7a]	29305	1			T1	7		T3	31		T4	5
valid_sources[0x7b]	31074	1			T1	18		T2	348		T3	6
valid_sources[0x7c]	32775	1			T1	12		T3	34		T4	1
valid_sources[0x7d]	29687	1			T1	18		T3	17		T4	4
valid_sources[0x7e]	30931	1			T1	10		T3	19		T4	6
valid_sources[0x7f]	31552	1			T1	17		T3	33		T4	7
valid_sources[0x80]	32927	1			T1	12		T3	21		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077185

1

T1

356

T2

2199

T3

2871

values[0x0]

all_enables

biggest_size

1663797

1

T1

1332

T2

1774

T3

456

values[0x1]

all_enables

biggest_size

1639752

1

T1

1306

T2

1731

T3

455