Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3840656

1

T1

180

T2

1948

T3

2800

full_word

4382134

1

T1

2994

T2

5704

T3

3782

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8222330	1			T1	3174		T2	7652		T3	6582
auto[TlIntgErrCmd]	137	1			T100	9		T101	13		T102	4
auto[TlIntgErrData]	161	1			T100	8		T101	12		T102	10
auto[TlIntgErrBoth]	162	1			T100	3		T101	5		T102	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4543248

1

T1

524

T2

4129

T3

5660

auto[1]

3679542

1

T1

2650

T2

3523

T3

922

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3465459	1			T1	168		T2	1930		T3	2789
auto[TlIntgErrNone]	partial	auto[1]	374778	1			T1	12		T2	18		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	1077591	1			T1	356		T2	2199		T3	2871
auto[TlIntgErrNone]	full_word	auto[1]	3304502	1			T1	2638		T2	3505		T3	911
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T100	2		T101	3		T102	2
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T100	6		T101	8		T102	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T100	1		T163	1		T164	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T101	2		T161	1		T165	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T100	2		T101	3		T102	6
auto[TlIntgErrData]	partial	auto[1]	78	1			T100	4		T101	8		T102	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T100	1		T161	2		T166	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T100	1		T101	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T100	1		T101	2		T102	3
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T100	2		T101	2		T102	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T167	1		T168	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	12	1			T101	1		T102	1		T169	3