Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	635444738	3379365	0	0
gen_wmask[1].MaskCheckPortA_A	635444738	3379365	0	0
gen_wmask[2].MaskCheckPortA_A	635444738	3379365	0	0
gen_wmask[3].MaskCheckPortA_A	635444738	3379365	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635444738	3379365	0	0
T1	266773	3515	0	0
T2	611621	11507	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	912337	12588	0	0
T8	536184	14429	0	0
T9	82274	832	0	0
T10	88651	832	0	0
T13	104593	832	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635444738	3379365	0	0
T1	266773	3515	0	0
T2	611621	11507	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	912337	12588	0	0
T8	536184	14429	0	0
T9	82274	832	0	0
T10	88651	832	0	0
T13	104593	832	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635444738	3379365	0	0
T1	266773	3515	0	0
T2	611621	11507	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	912337	12588	0	0
T8	536184	14429	0	0
T9	82274	832	0	0
T10	88651	832	0	0
T13	104593	832	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635444738	3379365	0	0
T1	266773	3515	0	0
T2	611621	11507	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	912337	12588	0	0
T8	536184	14429	0	0
T9	82274	832	0	0
T10	88651	832	0	0
T13	104593	832	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	481547675	2121740	0	0
gen_wmask[1].MaskCheckPortA_A	481547675	2121740	0	0
gen_wmask[2].MaskCheckPortA_A	481547675	2121740	0	0
gen_wmask[3].MaskCheckPortA_A	481547675	2121740	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2121740	0	0
T1	148123	2496	0	0
T2	272698	3328	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	6182	0	0
T8	128571	8880	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2121740	0	0
T1	148123	2496	0	0
T2	272698	3328	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	6182	0	0
T8	128571	8880	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2121740	0	0
T1	148123	2496	0	0
T2	272698	3328	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	6182	0	0
T8	128571	8880	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2121740	0	0
T1	148123	2496	0	0
T2	272698	3328	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	6182	0	0
T8	128571	8880	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	153897063	1257625	0	0
gen_wmask[1].MaskCheckPortA_A	153897063	1257625	0	0
gen_wmask[2].MaskCheckPortA_A	153897063	1257625	0	0
gen_wmask[3].MaskCheckPortA_A	153897063	1257625	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	1257625	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	6406	0	0
T8	407613	5549	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	1257625	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	6406	0	0
T8	407613	5549	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	1257625	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	6406	0	0
T8	407613	5549	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	1257625	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	6406	0	0
T8	407613	5549	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T27	0	918	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0