Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T27
1	0	Covered	T7,T8,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T25
1	0	Unreachable
1	1	Covered	T7,T8,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	789341801	633959580	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	789341801	3797785	0	0
GntImpliesValid_A	789341801	3797785	0	0
GrantKnown_A	789341801	633959580	0	0
IdxKnown_A	789341801	633959580	0	0
IndexIsCorrect_A	789341801	3797785	0	0
LockArbDecision_A	789341801	0	0	0
NoReadyValidNoGrant_A	789341801	0	0	0
ReadyAndValidImplyGrant_A	789341801	3797785	0	0
ReqAndReadyImplyGrant_A	789341801	3797785	0	0
ReqImpliesValid_A	789341801	3797785	0	0
ReqStaysHighUntilGranted0_M	789341801	0	0	0
RoundRobin_A	789341801	6	0	956
ValidKnown_A	789341801	633959580	0	0
gen_data_port_assertion.DataFlow_A	789341801	3797785	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	633959580	0	0
T1	266773	265336	0	0
T2	611621	611165	0	0
T3	253996	253190	0	0
T4	7768	7682	0	0
T5	3349	3289	0	0
T6	958	896	0	0
T7	1357256	905528	0	0
T8	943797	531375	0	0
T9	98025	82191	0	0
T10	109993	88575	0	0
T13	209186	104504	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	633959580	0	0
T1	266773	265336	0	0
T2	611621	611165	0	0
T3	253996	253190	0	0
T4	7768	7682	0	0
T5	3349	3289	0	0
T6	958	896	0	0
T7	1357256	905528	0	0
T8	943797	531375	0	0
T9	98025	82191	0	0
T10	109993	88575	0	0
T13	209186	104504	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	633959580	0	0
T1	266773	265336	0	0
T2	611621	611165	0	0
T3	253996	253190	0	0
T4	7768	7682	0	0
T5	3349	3289	0	0
T6	958	896	0	0
T7	1357256	905528	0	0
T8	943797	531375	0	0
T9	98025	82191	0	0
T10	109993	88575	0	0
T13	209186	104504	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	6	0	956
T55	495775	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	41543	0	0	1
T62	147036	0	0	1
T63	898446	0	0	1
T64	104423	0	0	1
T65	236169	0	0	1
T66	660441	0	0	1
T67	1228	0	0	1
T68	1104	0	0	1
T69	242648	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	633959580	0	0
T1	266773	265336	0	0
T2	611621	611165	0	0
T3	253996	253190	0	0
T4	7768	7682	0	0
T5	3349	3289	0	0
T6	958	896	0	0
T7	1357256	905528	0	0
T8	943797	531375	0	0
T9	98025	82191	0	0
T10	109993	88575	0	0
T13	209186	104504	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	789341801	3797785	0	0
T1	266773	3710	0	0
T2	611621	11839	0	0
T3	253996	832	0	0
T4	7768	832	0	0
T5	3349	832	0	0
T6	958	0	0	0
T7	1357256	15924	0	0
T8	943797	15869	0	0
T9	98025	832	0	0
T10	109993	832	0	0
T13	209186	832	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	10047	0	0
T31	0	170	0	0
T32	0	5629	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T44	0	2	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T27
1	0	Covered	T7,T8,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T25
1	0	Unreachable
1	1	Covered	T7,T8,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T27
0	0	1	Unreachable
0	0	0	Covered	T7,T8,T25

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153897063	30934709	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153897063	695242	0	0
GntImpliesValid_A	153897063	695242	0	0
GrantKnown_A	153897063	30934709	0	0
IdxKnown_A	153897063	30934709	0	0
IndexIsCorrect_A	153897063	695242	0	0
LockArbDecision_A	153897063	0	0	0
NoReadyValidNoGrant_A	153897063	0	0	0
ReadyAndValidImplyGrant_A	153897063	695242	0	0
ReqAndReadyImplyGrant_A	153897063	695242	0	0
ReqImpliesValid_A	153897063	695242	0	0
ReqStaysHighUntilGranted0_M	153897063	0	0	0
RoundRobin_A	153897063	0	0	0
ValidKnown_A	153897063	30934709	0	0
gen_data_port_assertion.DataFlow_A	153897063	695242	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	30934709	0	0
T7	444919	262520	0	0
T8	407613	51616	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	30934709	0	0
T7	444919	262520	0	0
T8	407613	51616	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	30934709	0	0
T7	444919	262520	0	0
T8	407613	51616	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	30934709	0	0
T7	444919	262520	0	0
T8	407613	51616	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	104616	0	0
T26	0	720	0	0
T27	0	49160	0	0
T29	0	944	0	0
T30	0	92664	0	0
T31	0	2272	0	0
T32	0	601120	0	0
T33	0	936	0	0
T51	10948	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	695242	0	0
T7	444919	5948	0	0
T8	407613	1779	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T14	74156	0	0	0
T23	28448	0	0	0
T24	101974	0	0	0
T25	111087	0	0	0
T27	0	1849	0	0
T29	0	32	0	0
T30	0	3925	0	0
T31	0	170	0	0
T32	0	5629	0	0
T51	10948	0	0	0
T52	0	3569	0	0
T53	0	253	0	0
T54	0	31	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153897063	121560924	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153897063	793158	0	0
GntImpliesValid_A	153897063	793158	0	0
GrantKnown_A	153897063	121560924	0	0
IdxKnown_A	153897063	121560924	0	0
IndexIsCorrect_A	153897063	793158	0	0
LockArbDecision_A	153897063	0	0	0
NoReadyValidNoGrant_A	153897063	0	0	0
ReadyAndValidImplyGrant_A	153897063	793158	0	0
ReqAndReadyImplyGrant_A	153897063	793158	0	0
ReqImpliesValid_A	153897063	793158	0	0
ReqStaysHighUntilGranted0_M	153897063	0	0	0
RoundRobin_A	153897063	0	0	0
ValidKnown_A	153897063	121560924	0	0
gen_data_port_assertion.DataFlow_A	153897063	793158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	121560924	0	0
T1	118650	117310	0	0
T2	338923	338472	0	0
T3	41929	41200	0	0
T4	1092	1092	0	0
T5	47	47	0	0
T7	444919	175757	0	0
T8	407613	351198	0	0
T9	15751	15722	0	0
T10	21342	21342	0	0
T13	104593	104504	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	121560924	0	0
T1	118650	117310	0	0
T2	338923	338472	0	0
T3	41929	41200	0	0
T4	1092	1092	0	0
T5	47	47	0	0
T7	444919	175757	0	0
T8	407613	351198	0	0
T9	15751	15722	0	0
T10	21342	21342	0	0
T13	104593	104504	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	121560924	0	0
T1	118650	117310	0	0
T2	338923	338472	0	0
T3	41929	41200	0	0
T4	1092	1092	0	0
T5	47	47	0	0
T7	444919	175757	0	0
T8	407613	351198	0	0
T9	15751	15722	0	0
T10	21342	21342	0	0
T13	104593	104504	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	121560924	0	0
T1	118650	117310	0	0
T2	338923	338472	0	0
T3	41929	41200	0	0
T4	1092	1092	0	0
T5	47	47	0	0
T7	444919	175757	0	0
T8	407613	351198	0	0
T9	15751	15722	0	0
T10	21342	21342	0	0
T13	104593	104504	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153897063	793158	0	0
T1	118650	1019	0	0
T2	338923	8179	0	0
T3	41929	0	0	0
T4	1092	0	0	0
T5	47	0	0	0
T7	444919	2673	0	0
T8	407613	4377	0	0
T9	15751	0	0	0
T10	21342	0	0	0
T13	104593	0	0	0
T30	0	6122	0	0
T34	0	6441	0	0
T38	0	2271	0	0
T39	0	3792	0	0
T40	0	829	0	0
T44	0	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	481547675	481463947	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	481547675	2309385	0	0
GntImpliesValid_A	481547675	2309385	0	0
GrantKnown_A	481547675	481463947	0	0
IdxKnown_A	481547675	481463947	0	0
IndexIsCorrect_A	481547675	2309385	0	0
LockArbDecision_A	481547675	0	0	0
NoReadyValidNoGrant_A	481547675	0	0	0
ReadyAndValidImplyGrant_A	481547675	2309385	0	0
ReqAndReadyImplyGrant_A	481547675	2309385	0	0
ReqImpliesValid_A	481547675	2309385	0	0
ReqStaysHighUntilGranted0_M	481547675	0	0	0
RoundRobin_A	481547675	6	0	956
ValidKnown_A	481547675	481463947	0	0
gen_data_port_assertion.DataFlow_A	481547675	2309385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	481463947	0	0
T1	148123	148026	0	0
T2	272698	272693	0	0
T3	212067	211990	0	0
T4	6676	6590	0	0
T5	3302	3242	0	0
T6	958	896	0	0
T7	467418	467251	0	0
T8	128571	128561	0	0
T9	66523	66469	0	0
T10	67309	67233	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	481463947	0	0
T1	148123	148026	0	0
T2	272698	272693	0	0
T3	212067	211990	0	0
T4	6676	6590	0	0
T5	3302	3242	0	0
T6	958	896	0	0
T7	467418	467251	0	0
T8	128571	128561	0	0
T9	66523	66469	0	0
T10	67309	67233	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	481463947	0	0
T1	148123	148026	0	0
T2	272698	272693	0	0
T3	212067	211990	0	0
T4	6676	6590	0	0
T5	3302	3242	0	0
T6	958	896	0	0
T7	467418	467251	0	0
T8	128571	128561	0	0
T9	66523	66469	0	0
T10	67309	67233	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	6	0	956
T55	495775	1	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	41543	0	0	1
T62	147036	0	0	1
T63	898446	0	0	1
T64	104423	0	0	1
T65	236169	0	0	1
T66	660441	0	0	1
T67	1228	0	0	1
T68	1104	0	0	1
T69	242648	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	481463947	0	0
T1	148123	148026	0	0
T2	272698	272693	0	0
T3	212067	211990	0	0
T4	6676	6590	0	0
T5	3302	3242	0	0
T6	958	896	0	0
T7	467418	467251	0	0
T8	128571	128561	0	0
T9	66523	66469	0	0
T10	67309	67233	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481547675	2309385	0	0
T1	148123	2691	0	0
T2	272698	3660	0	0
T3	212067	832	0	0
T4	6676	832	0	0
T5	3302	832	0	0
T6	958	0	0	0
T7	467418	7303	0	0
T8	128571	9713	0	0
T9	66523	832	0	0
T10	67309	832	0	0
T13	0	832	0	0