Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	484006169	3376	0	0
addr_swap_data_rd_A	484006169	2313	0	0
addr_swap_mask_rd_A	484006169	2389	0	0
cfg_rd_A	484006169	2758	0	0
cmd_filter_0_rd_A	484006169	8632	0	0
cmd_filter_1_rd_A	484006169	9114	0	0
cmd_filter_2_rd_A	484006169	9149	0	0
cmd_filter_3_rd_A	484006169	8881	0	0
cmd_filter_4_rd_A	484006169	8100	0	0
cmd_filter_5_rd_A	484006169	8896	0	0
cmd_filter_6_rd_A	484006169	9163	0	0
cmd_filter_7_rd_A	484006169	7538	0	0
cmd_info_0_rd_A	484006169	4383	0	0
cmd_info_10_rd_A	484006169	5202	0	0
cmd_info_11_rd_A	484006169	4796	0	0
cmd_info_12_rd_A	484006169	4786	0	0
cmd_info_13_rd_A	484006169	4743	0	0
cmd_info_14_rd_A	484006169	4723	0	0
cmd_info_15_rd_A	484006169	4775	0	0
cmd_info_16_rd_A	484006169	5280	0	0
cmd_info_17_rd_A	484006169	4905	0	0
cmd_info_18_rd_A	484006169	4482	0	0
cmd_info_19_rd_A	484006169	4659	0	0
cmd_info_1_rd_A	484006169	4989	0	0
cmd_info_20_rd_A	484006169	4936	0	0
cmd_info_21_rd_A	484006169	5178	0	0
cmd_info_22_rd_A	484006169	4669	0	0
cmd_info_23_rd_A	484006169	4648	0	0
cmd_info_2_rd_A	484006169	4634	0	0
cmd_info_3_rd_A	484006169	5046	0	0
cmd_info_4_rd_A	484006169	5067	0	0
cmd_info_5_rd_A	484006169	4886	0	0
cmd_info_6_rd_A	484006169	4915	0	0
cmd_info_7_rd_A	484006169	4630	0	0
cmd_info_8_rd_A	484006169	4568	0	0
cmd_info_9_rd_A	484006169	4428	0	0
cmd_info_en4b_rd_A	484006169	2368	0	0
cmd_info_ex4b_rd_A	484006169	2533	0	0
cmd_info_wrdi_rd_A	484006169	2561	0	0
cmd_info_wren_rd_A	484006169	2450	0	0
intercept_en_rd_A	484006169	2985	0	0
intr_enable_rd_A	484006169	4486	0	0
jedec_cc_rd_A	484006169	2475	0	0
jedec_id_rd_A	484006169	2418	0	0
mailbox_addr_rd_A	484006169	2278	0	0
payload_swap_data_rd_A	484006169	2372	0	0
payload_swap_mask_rd_A	484006169	2412	0	0
read_threshold_rd_A	484006169	2230	0	0
tpm_access_0_rd_A	484006169	3036	0	0
tpm_access_1_rd_A	484006169	2333	0	0
tpm_cfg_rd_A	484006169	3166	0	0
tpm_did_vid_rd_A	484006169	2430	0	0
tpm_int_enable_rd_A	484006169	2400	0	0
tpm_int_status_rd_A	484006169	2371	0	0
tpm_int_vector_rd_A	484006169	2353	0	0
tpm_intf_capability_rd_A	484006169	2265	0	0
tpm_rid_rd_A	484006169	2341	0	0
tpm_sts_rd_A	484006169	2506	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	3376	0	0
T73	22001	273	0	0
T74	2032	59	0	0
T75	3958	10	0	0
T99	5515	11	0	0
T100	18714	2	0	0
T101	28046	4	0	0
T105	8249	45	0	0
T108	5608	176	0	0
T109	8959	8	0	0
T112	8189	7	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2313	0	0
T87	4880	15	0	0
T102	70087	87	0	0
T123	9747	5	0	0
T148	3410	13	0	0
T149	10445	9	0	0
T150	7205	17	0	0
T151	18231	76	0	0
T152	6886	10	0	0
T153	14091	23	0	0
T154	5876	14	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2389	0	0
T87	4880	2	0	0
T102	70087	75	0	0
T148	3410	5	0	0
T149	10445	2	0	0
T150	7205	25	0	0
T151	18231	3	0	0
T152	6886	11	0	0
T153	14091	36	0	0
T154	5876	11	0	0
T155	6876	10	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2758	0	0
T87	4880	6	0	0
T102	70087	167	0	0
T123	9747	9	0	0
T148	3410	12	0	0
T149	10445	4	0	0
T150	7205	34	0	0
T151	18231	41	0	0
T152	6886	17	0	0
T153	14091	45	0	0
T154	5876	16	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	8632	0	0
T87	4880	22	0	0
T102	70087	998	0	0
T122	4242	72	0	0
T123	9747	79	0	0
T148	3410	7	0	0
T149	10445	113	0	0
T150	7205	42	0	0
T151	18231	30	0	0
T152	6886	113	0	0
T153	14091	66	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	9114	0	0
T87	4880	23	0	0
T102	70087	944	0	0
T122	4242	80	0	0
T123	9747	228	0	0
T148	3410	8	0	0
T149	10445	10	0	0
T150	7205	10	0	0
T151	18231	26	0	0
T152	6886	135	0	0
T153	14091	22	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	9149	0	0
T87	4880	19	0	0
T102	70087	1476	0	0
T123	9747	72	0	0
T148	3410	10	0	0
T149	10445	86	0	0
T150	7205	5	0	0
T151	18231	73	0	0
T152	6886	8	0	0
T153	14091	64	0	0
T154	5876	94	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	8881	0	0
T87	4880	5	0	0
T102	70087	1508	0	0
T122	4242	34	0	0
T123	9747	231	0	0
T148	3410	10	0	0
T149	10445	129	0	0
T150	7205	38	0	0
T151	18231	30	0	0
T152	6886	6	0	0
T153	14091	47	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	8100	0	0
T87	4880	13	0	0
T102	70087	1561	0	0
T123	9747	112	0	0
T148	3410	8	0	0
T149	10445	130	0	0
T150	7205	10	0	0
T151	18231	43	0	0
T152	6886	6	0	0
T153	14091	65	0	0
T154	5876	125	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	8896	0	0
T87	4880	6	0	0
T102	70087	1757	0	0
T122	4242	63	0	0
T123	9747	138	0	0
T148	3410	7	0	0
T149	10445	267	0	0
T151	18231	30	0	0
T152	6886	121	0	0
T153	14091	58	0	0
T154	5876	3	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	9163	0	0
T87	4880	12	0	0
T102	70087	1584	0	0
T122	4242	10	0	0
T123	9747	1	0	0
T148	3410	8	0	0
T150	7205	10	0	0
T151	18231	19	0	0
T152	6886	114	0	0
T153	14091	23	0	0
T154	5876	8	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	7538	0	0
T87	4880	10	0	0
T102	70087	1295	0	0
T122	4242	3	0	0
T148	3410	8	0	0
T149	10445	164	0	0
T150	7205	10	0	0
T151	18231	43	0	0
T152	6886	122	0	0
T153	14091	37	0	0
T154	5876	126	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4383	0	0
T87	4880	16	0	0
T102	70087	369	0	0
T122	4242	22	0	0
T123	9747	37	0	0
T148	3410	18	0	0
T149	10445	98	0	0
T150	7205	24	0	0
T151	18231	30	0	0
T152	6886	66	0	0
T153	14091	31	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	5202	0	0
T87	4880	12	0	0
T102	70087	767	0	0
T123	9747	56	0	0
T148	3410	8	0	0
T149	10445	68	0	0
T150	7205	5	0	0
T151	18231	21	0	0
T152	6886	50	0	0
T153	14091	37	0	0
T154	5876	50	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4796	0	0
T87	4880	11	0	0
T102	70087	604	0	0
T122	4242	5	0	0
T123	9747	64	0	0
T148	3410	9	0	0
T149	10445	45	0	0
T150	7205	28	0	0
T151	18231	31	0	0
T152	6886	5	0	0
T153	14091	53	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4786	0	0
T73	22001	4	0	0
T87	4880	12	0	0
T102	70087	571	0	0
T123	9747	4	0	0
T148	3410	9	0	0
T149	10445	70	0	0
T151	18231	19	0	0
T152	6886	2	0	0
T153	14091	78	0	0
T154	5876	44	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4743	0	0
T87	4880	5	0	0
T102	70087	476	0	0
T122	4242	43	0	0
T123	9747	24	0	0
T148	3410	10	0	0
T149	10445	47	0	0
T150	7205	29	0	0
T151	18231	77	0	0
T152	6886	51	0	0
T153	14091	28	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4723	0	0
T87	4880	13	0	0
T102	70087	497	0	0
T122	4242	21	0	0
T123	9747	26	0	0
T148	3410	6	0	0
T149	10445	44	0	0
T150	7205	46	0	0
T151	18231	12	0	0
T152	6886	62	0	0
T153	14091	32	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4775	0	0
T87	4880	13	0	0
T102	70087	375	0	0
T122	4242	4	0	0
T123	9747	10	0	0
T148	3410	9	0	0
T149	10445	27	0	0
T151	18231	25	0	0
T152	6886	70	0	0
T153	14091	26	0	0
T154	5876	45	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	5280	0	0
T87	4880	4	0	0
T102	70087	792	0	0
T123	9747	108	0	0
T148	3410	10	0	0
T149	10445	35	0	0
T150	7205	10	0	0
T151	18231	54	0	0
T152	6886	7	0	0
T153	14091	68	0	0
T154	5876	42	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4905	0	0
T87	4880	17	0	0
T102	70087	492	0	0
T122	4242	31	0	0
T123	9747	128	0	0
T148	3410	2	0	0
T149	10445	4	0	0
T150	7205	37	0	0
T151	18231	32	0	0
T152	6886	68	0	0
T153	14091	29	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4482	0	0
T87	4880	13	0	0
T102	70087	402	0	0
T122	4242	19	0	0
T123	9747	5	0	0
T148	3410	15	0	0
T149	10445	8	0	0
T151	18231	17	0	0
T152	6886	51	0	0
T153	14091	18	0	0
T154	5876	55	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4659	0	0
T87	4880	8	0	0
T102	70087	618	0	0
T123	9747	50	0	0
T148	3410	8	0	0
T149	10445	36	0	0
T150	7205	14	0	0
T151	18231	19	0	0
T152	6886	6	0	0
T153	14091	17	0	0
T154	5876	14	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4989	0	0
T87	4880	16	0	0
T102	70087	538	0	0
T122	4242	28	0	0
T123	9747	27	0	0
T148	3410	10	0	0
T149	10445	48	0	0
T150	7205	14	0	0
T151	18231	49	0	0
T152	6886	77	0	0
T153	14091	28	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4936	0	0
T87	4880	14	0	0
T102	70087	533	0	0
T122	4242	16	0	0
T123	9747	54	0	0
T148	3410	6	0	0
T149	10445	49	0	0
T150	7205	23	0	0
T151	18231	44	0	0
T152	6886	8	0	0
T153	14091	57	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	5178	0	0
T87	4880	15	0	0
T102	70087	570	0	0
T122	4242	23	0	0
T123	9747	61	0	0
T148	3410	3	0	0
T149	10445	56	0	0
T150	7205	18	0	0
T151	18231	27	0	0
T152	6886	50	0	0
T153	14091	24	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4669	0	0
T87	4880	17	0	0
T102	70087	555	0	0
T122	4242	45	0	0
T123	9747	49	0	0
T148	3410	8	0	0
T149	10445	40	0	0
T150	7205	13	0	0
T151	18231	54	0	0
T152	6886	38	0	0
T153	14091	51	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4648	0	0
T102	70087	517	0	0
T122	4242	7	0	0
T123	9747	6	0	0
T148	3410	5	0	0
T149	10445	96	0	0
T150	7205	11	0	0
T151	18231	65	0	0
T152	6886	5	0	0
T153	14091	29	0	0
T156	17372	9	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4634	0	0
T87	4880	15	0	0
T102	70087	596	0	0
T122	4242	18	0	0
T123	9747	4	0	0
T148	3410	8	0	0
T149	10445	33	0	0
T150	7205	36	0	0
T151	18231	42	0	0
T152	6886	10	0	0
T153	14091	21	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	5046	0	0
T87	4880	1	0	0
T102	70087	644	0	0
T122	4242	29	0	0
T123	9747	45	0	0
T148	3410	3	0	0
T149	10445	59	0	0
T150	7205	39	0	0
T151	18231	19	0	0
T152	6886	46	0	0
T153	14091	59	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	5067	0	0
T87	4880	13	0	0
T102	70087	647	0	0
T123	9747	118	0	0
T148	3410	9	0	0
T149	10445	65	0	0
T150	7205	51	0	0
T151	18231	27	0	0
T152	6886	62	0	0
T153	14091	39	0	0
T154	5876	42	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4886	0	0
T87	4880	1	0	0
T102	70087	770	0	0
T122	4242	2	0	0
T123	9747	34	0	0
T148	3410	4	0	0
T149	10445	30	0	0
T150	7205	38	0	0
T151	18231	34	0	0
T152	6886	4	0	0
T153	14091	31	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4915	0	0
T87	4880	13	0	0
T102	70087	803	0	0
T122	4242	25	0	0
T123	9747	94	0	0
T148	3410	10	0	0
T149	10445	29	0	0
T150	7205	25	0	0
T151	18231	2	0	0
T152	6886	77	0	0
T153	14091	16	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4630	0	0
T87	4880	14	0	0
T102	70087	536	0	0
T122	4242	44	0	0
T123	9747	40	0	0
T148	3410	10	0	0
T149	10445	27	0	0
T150	7205	36	0	0
T151	18231	57	0	0
T152	6886	11	0	0
T153	14091	19	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4568	0	0
T102	70087	435	0	0
T107	7075	4	0	0
T122	4242	22	0	0
T123	9747	82	0	0
T148	3410	13	0	0
T149	10445	26	0	0
T150	7205	25	0	0
T151	18231	37	0	0
T152	6886	2	0	0
T153	14091	52	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4428	0	0
T87	4880	7	0	0
T102	70087	535	0	0
T122	4242	9	0	0
T123	9747	79	0	0
T148	3410	8	0	0
T149	10445	27	0	0
T150	7205	20	0	0
T151	18231	16	0	0
T152	6886	57	0	0
T153	14091	22	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2368	0	0
T87	4880	6	0	0
T102	70087	99	0	0
T122	4242	2	0	0
T123	9747	8	0	0
T148	3410	8	0	0
T149	10445	8	0	0
T150	7205	14	0	0
T151	18231	37	0	0
T152	6886	2	0	0
T153	14091	61	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2533	0	0
T87	4880	6	0	0
T102	70087	135	0	0
T122	4242	1	0	0
T123	9747	14	0	0
T148	3410	4	0	0
T149	10445	5	0	0
T150	7205	4	0	0
T151	18231	30	0	0
T152	6886	11	0	0
T153	14091	49	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2561	0	0
T87	4880	7	0	0
T102	70087	110	0	0
T122	4242	3	0	0
T123	9747	9	0	0
T148	3410	11	0	0
T149	10445	26	0	0
T150	7205	3	0	0
T151	18231	37	0	0
T152	6886	18	0	0
T153	14091	80	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2450	0	0
T87	4880	12	0	0
T102	70087	125	0	0
T122	4242	4	0	0
T123	9747	4	0	0
T148	3410	10	0	0
T149	10445	3	0	0
T150	7205	43	0	0
T151	18231	25	0	0
T152	6886	7	0	0
T153	14091	31	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2985	0	0
T87	4880	15	0	0
T102	70087	215	0	0
T122	4242	2	0	0
T123	9747	20	0	0
T148	3410	11	0	0
T149	10445	15	0	0
T151	18231	38	0	0
T152	6886	21	0	0
T153	14091	28	0	0
T154	5876	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	4486	0	0
T7	467418	22	0	0
T8	128571	0	0	0
T9	66523	0	0	0
T10	67309	0	0	0
T11	1796	0	0	0
T12	5663	0	0	0
T13	317749	0	0	0
T14	78129	0	0	0
T17	0	49	0	0
T19	0	25	0	0
T20	0	31	0	0
T22	0	68	0	0
T23	209402	0	0	0
T24	205943	0	0	0
T36	0	22	0	0
T126	0	23	0	0
T136	0	21	0	0
T157	0	27	0	0
T158	0	31	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2475	0	0
T87	4880	11	0	0
T102	70087	82	0	0
T123	9747	16	0	0
T148	3410	6	0	0
T149	10445	7	0	0
T150	7205	43	0	0
T151	18231	46	0	0
T152	6886	5	0	0
T153	14091	26	0	0
T154	5876	8	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2418	0	0
T87	4880	6	0	0
T102	70087	98	0	0
T123	9747	13	0	0
T148	3410	5	0	0
T149	10445	17	0	0
T150	7205	16	0	0
T151	18231	35	0	0
T152	6886	5	0	0
T153	14091	30	0	0
T154	5876	6	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2278	0	0
T87	4880	7	0	0
T102	70087	74	0	0
T122	4242	4	0	0
T123	9747	4	0	0
T148	3410	6	0	0
T149	10445	16	0	0
T150	7205	17	0	0
T151	18231	17	0	0
T152	6886	7	0	0
T153	14091	27	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2372	0	0
T87	4880	20	0	0
T102	70087	38	0	0
T123	9747	5	0	0
T148	3410	5	0	0
T149	10445	15	0	0
T150	7205	8	0	0
T151	18231	17	0	0
T152	6886	6	0	0
T153	14091	60	0	0
T155	6876	8	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2412	0	0
T87	4880	6	0	0
T102	70087	77	0	0
T122	4242	9	0	0
T123	9747	8	0	0
T148	3410	12	0	0
T149	10445	5	0	0
T150	7205	5	0	0
T151	18231	45	0	0
T152	6886	8	0	0
T153	14091	84	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2230	0	0
T87	4880	12	0	0
T102	70087	48	0	0
T107	7075	4	0	0
T123	9747	11	0	0
T148	3410	2	0	0
T149	10445	5	0	0
T150	7205	26	0	0
T151	18231	19	0	0
T152	6886	1	0	0
T153	14091	26	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	3036	0	0
T87	4880	7	0	0
T102	70087	243	0	0
T123	9747	11	0	0
T148	3410	2	0	0
T149	10445	11	0	0
T150	7205	43	0	0
T151	18231	70	0	0
T152	6886	6	0	0
T153	14091	90	0	0
T154	5876	15	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2333	0	0
T87	4880	12	0	0
T102	70087	61	0	0
T123	9747	4	0	0
T148	3410	15	0	0
T149	10445	7	0	0
T151	18231	20	0	0
T152	6886	7	0	0
T153	14091	71	0	0
T154	5876	7	0	0
T155	6876	3	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	3166	0	0
T87	4880	12	0	0
T102	70087	196	0	0
T123	9747	22	0	0
T148	3410	9	0	0
T149	10445	6	0	0
T150	7205	16	0	0
T151	18231	36	0	0
T152	6886	18	0	0
T153	14091	34	0	0
T154	5876	26	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2430	0	0
T87	4880	10	0	0
T102	70087	112	0	0
T123	9747	6	0	0
T148	3410	15	0	0
T149	10445	10	0	0
T150	7205	28	0	0
T151	18231	57	0	0
T152	6886	17	0	0
T153	14091	33	0	0
T154	5876	14	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2400	0	0
T87	4880	20	0	0
T102	70087	95	0	0
T123	9747	13	0	0
T148	3410	2	0	0
T149	10445	10	0	0
T150	7205	28	0	0
T151	18231	13	0	0
T152	6886	11	0	0
T153	14091	46	0	0
T154	5876	5	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2371	0	0
T87	4880	19	0	0
T102	70087	58	0	0
T122	4242	4	0	0
T123	9747	5	0	0
T148	3410	3	0	0
T149	10445	8	0	0
T150	7205	40	0	0
T151	18231	19	0	0
T152	6886	12	0	0
T153	14091	70	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2353	0	0
T87	4880	15	0	0
T102	70087	93	0	0
T122	4242	5	0	0
T123	9747	9	0	0
T148	3410	12	0	0
T149	10445	3	0	0
T150	7205	12	0	0
T151	18231	41	0	0
T152	6886	1	0	0
T153	14091	26	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2265	0	0
T87	4880	9	0	0
T102	70087	69	0	0
T123	9747	11	0	0
T148	3410	13	0	0
T149	10445	5	0	0
T151	18231	38	0	0
T152	6886	5	0	0
T153	14091	18	0	0
T154	5876	14	0	0
T155	6876	5	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2341	0	0
T73	22001	5	0	0
T87	4880	6	0	0
T102	70087	82	0	0
T123	9747	3	0	0
T148	3410	9	0	0
T149	10445	12	0	0
T150	7205	23	0	0
T151	18231	37	0	0
T152	6886	12	0	0
T153	14091	50	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484006169	2506	0	0
T87	4880	8	0	0
T102	70087	101	0	0
T122	4242	9	0	0
T123	9747	16	0	0
T148	3410	8	0	0
T149	10445	9	0	0
T150	7205	28	0	0
T151	18231	35	0	0
T152	6886	11	0	0
T153	14091	33	0	0