Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T86 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1839757521 Jul 31 05:47:51 PM PDT 24 Jul 31 05:47:52 PM PDT 24 57329825 ps
T1019 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1724551173 Jul 31 05:48:14 PM PDT 24 Jul 31 05:48:14 PM PDT 24 76510667 ps
T123 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.694784719 Jul 31 05:47:58 PM PDT 24 Jul 31 05:48:00 PM PDT 24 98474231 ps
T1020 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3291194579 Jul 31 05:48:07 PM PDT 24 Jul 31 05:48:10 PM PDT 24 169824765 ps
T1021 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2414525010 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:10 PM PDT 24 41621733 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.859628189 Jul 31 05:47:55 PM PDT 24 Jul 31 05:48:17 PM PDT 24 1241386645 ps
T1022 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1514198635 Jul 31 05:48:13 PM PDT 24 Jul 31 05:48:14 PM PDT 24 19628155 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3515186405 Jul 31 05:47:57 PM PDT 24 Jul 31 05:47:57 PM PDT 24 12213147 ps
T1024 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2259783488 Jul 31 05:48:16 PM PDT 24 Jul 31 05:48:17 PM PDT 24 16029051 ps
T161 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4126435223 Jul 31 05:47:57 PM PDT 24 Jul 31 05:48:19 PM PDT 24 3479067444 ps
T1025 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3730406434 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:11 PM PDT 24 56470691 ps
T1026 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.960495706 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:10 PM PDT 24 43944586 ps
T1027 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3287960046 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:12 PM PDT 24 36918603 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3149556165 Jul 31 05:47:44 PM PDT 24 Jul 31 05:48:06 PM PDT 24 1663294169 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1114147294 Jul 31 05:47:57 PM PDT 24 Jul 31 05:47:59 PM PDT 24 28613818 ps
T1028 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3644610635 Jul 31 05:47:58 PM PDT 24 Jul 31 05:47:59 PM PDT 24 567218003 ps
T156 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2262663574 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:05 PM PDT 24 180990882 ps
T87 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2829114413 Jul 31 05:47:53 PM PDT 24 Jul 31 05:47:55 PM PDT 24 51390235 ps
T1029 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.813595510 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:13 PM PDT 24 333718685 ps
T1030 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.414236643 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:05 PM PDT 24 75277131 ps
T1031 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.868449636 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:08 PM PDT 24 88275901 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2172098427 Jul 31 05:47:51 PM PDT 24 Jul 31 05:47:51 PM PDT 24 16388313 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2546773310 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:12 PM PDT 24 524574829 ps
T1034 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.698784119 Jul 31 05:48:16 PM PDT 24 Jul 31 05:48:17 PM PDT 24 52713842 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.526387155 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:02 PM PDT 24 15187763 ps
T1036 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2199041990 Jul 31 05:48:11 PM PDT 24 Jul 31 05:48:13 PM PDT 24 207803408 ps
T1037 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3263940626 Jul 31 05:48:07 PM PDT 24 Jul 31 05:48:08 PM PDT 24 16879164 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3532102115 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:53 PM PDT 24 107002725 ps
T1039 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1949133623 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 14266305 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2672488931 Jul 31 05:47:49 PM PDT 24 Jul 31 05:47:50 PM PDT 24 33282308 ps
T1041 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1683826848 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:11 PM PDT 24 11819435 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3750476746 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:47 PM PDT 24 38740053 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3621881983 Jul 31 05:47:54 PM PDT 24 Jul 31 05:47:55 PM PDT 24 20992795 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2855885327 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:11 PM PDT 24 12632768 ps
T1044 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2995740663 Jul 31 05:48:05 PM PDT 24 Jul 31 05:48:07 PM PDT 24 78990346 ps
T154 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.389306693 Jul 31 05:47:53 PM PDT 24 Jul 31 05:47:55 PM PDT 24 452069475 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3983485716 Jul 31 05:47:54 PM PDT 24 Jul 31 05:47:56 PM PDT 24 70609241 ps
T163 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1241452891 Jul 31 05:47:51 PM PDT 24 Jul 31 05:48:07 PM PDT 24 2244721699 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3291180841 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:55 PM PDT 24 447179103 ps
T1047 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2592424051 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:11 PM PDT 24 52469474 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.872983110 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 28264236 ps
T1049 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1404901926 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:06 PM PDT 24 854200786 ps
T155 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1256721934 Jul 31 05:48:06 PM PDT 24 Jul 31 05:48:08 PM PDT 24 275113508 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.510623224 Jul 31 05:47:58 PM PDT 24 Jul 31 05:48:06 PM PDT 24 694288098 ps
T166 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3632010955 Jul 31 05:47:55 PM PDT 24 Jul 31 05:48:14 PM PDT 24 299926746 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3767123587 Jul 31 05:47:50 PM PDT 24 Jul 31 05:47:58 PM PDT 24 62989474 ps
T1052 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3800371684 Jul 31 05:47:50 PM PDT 24 Jul 31 05:48:06 PM PDT 24 2851054024 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2083891848 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:04 PM PDT 24 165499503 ps
T1054 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.392168585 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:07 PM PDT 24 91692258 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1978930168 Jul 31 05:47:49 PM PDT 24 Jul 31 05:47:54 PM PDT 24 737811708 ps
T1056 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1262238104 Jul 31 05:48:13 PM PDT 24 Jul 31 05:48:13 PM PDT 24 13739136 ps
T162 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4211425551 Jul 31 05:48:03 PM PDT 24 Jul 31 05:48:18 PM PDT 24 1328552688 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2137038982 Jul 31 05:47:50 PM PDT 24 Jul 31 05:47:52 PM PDT 24 166292529 ps
T1058 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3427135177 Jul 31 05:47:57 PM PDT 24 Jul 31 05:47:58 PM PDT 24 17283634 ps
T1059 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3821552145 Jul 31 05:48:03 PM PDT 24 Jul 31 05:48:04 PM PDT 24 18783881 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4109029855 Jul 31 05:48:00 PM PDT 24 Jul 31 05:48:04 PM PDT 24 422645993 ps
T1061 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.228180230 Jul 31 05:48:06 PM PDT 24 Jul 31 05:48:08 PM PDT 24 31389507 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2785151129 Jul 31 05:48:03 PM PDT 24 Jul 31 05:48:04 PM PDT 24 39860944 ps
T1063 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3706895079 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:09 PM PDT 24 110649521 ps
T164 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1315689965 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:31 PM PDT 24 2048417114 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3141403036 Jul 31 05:47:56 PM PDT 24 Jul 31 05:47:57 PM PDT 24 15422836 ps
T1065 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3692276811 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:10 PM PDT 24 241749472 ps
T1066 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.947585284 Jul 31 05:48:00 PM PDT 24 Jul 31 05:48:01 PM PDT 24 12887617 ps
T1067 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1019303582 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 14876617 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2950823396 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:20 PM PDT 24 1189225639 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1118613139 Jul 31 05:48:06 PM PDT 24 Jul 31 05:48:08 PM PDT 24 108222641 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2492292497 Jul 31 05:47:56 PM PDT 24 Jul 31 05:47:59 PM PDT 24 43226111 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3693321832 Jul 31 05:47:51 PM PDT 24 Jul 31 05:48:11 PM PDT 24 300032157 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.293617721 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:53 PM PDT 24 17717633 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2084045338 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:06 PM PDT 24 246058419 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3645218713 Jul 31 05:48:02 PM PDT 24 Jul 31 05:48:06 PM PDT 24 508627153 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.851121032 Jul 31 05:47:51 PM PDT 24 Jul 31 05:48:30 PM PDT 24 11206940086 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2383335940 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:09 PM PDT 24 216881630 ps
T1077 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3954778531 Jul 31 05:48:13 PM PDT 24 Jul 31 05:48:14 PM PDT 24 19109322 ps
T165 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1017407962 Jul 31 05:48:14 PM PDT 24 Jul 31 05:48:26 PM PDT 24 205955278 ps
T1078 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1963486153 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 15770160 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.172369740 Jul 31 05:47:58 PM PDT 24 Jul 31 05:48:12 PM PDT 24 661257560 ps
T1080 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.934971072 Jul 31 05:48:11 PM PDT 24 Jul 31 05:48:26 PM PDT 24 2302023366 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1239631671 Jul 31 05:47:50 PM PDT 24 Jul 31 05:48:26 PM PDT 24 3613567784 ps
T1082 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.287782989 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:16 PM PDT 24 717723053 ps
T1083 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1734753171 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 19966926 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2481130769 Jul 31 05:47:56 PM PDT 24 Jul 31 05:48:08 PM PDT 24 1239505793 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4106318446 Jul 31 05:47:45 PM PDT 24 Jul 31 05:47:48 PM PDT 24 755213656 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3842863636 Jul 31 05:47:58 PM PDT 24 Jul 31 05:48:11 PM PDT 24 212296066 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3043518564 Jul 31 05:48:04 PM PDT 24 Jul 31 05:48:05 PM PDT 24 39859231 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3502285484 Jul 31 05:47:59 PM PDT 24 Jul 31 05:48:02 PM PDT 24 144136023 ps
T167 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3713303629 Jul 31 05:48:11 PM PDT 24 Jul 31 05:48:30 PM PDT 24 3995746159 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2844442180 Jul 31 05:47:47 PM PDT 24 Jul 31 05:47:49 PM PDT 24 48361374 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.546599801 Jul 31 05:47:55 PM PDT 24 Jul 31 05:47:59 PM PDT 24 1057553794 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1939629743 Jul 31 05:47:49 PM PDT 24 Jul 31 05:47:50 PM PDT 24 18255339 ps
T1092 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.218550555 Jul 31 05:47:50 PM PDT 24 Jul 31 05:47:51 PM PDT 24 15275607 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.67201863 Jul 31 05:48:05 PM PDT 24 Jul 31 05:48:12 PM PDT 24 323429325 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4285391265 Jul 31 05:47:55 PM PDT 24 Jul 31 05:47:57 PM PDT 24 191423230 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1200640223 Jul 31 05:48:05 PM PDT 24 Jul 31 05:48:06 PM PDT 24 36263812 ps
T1096 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2315327054 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:09 PM PDT 24 19835234 ps
T1097 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1892643048 Jul 31 05:48:07 PM PDT 24 Jul 31 05:48:11 PM PDT 24 147938288 ps
T1098 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1482439803 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:03 PM PDT 24 55752045 ps
T1099 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2235169021 Jul 31 05:47:54 PM PDT 24 Jul 31 05:47:56 PM PDT 24 187302289 ps
T1100 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3710652173 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:12 PM PDT 24 75219201 ps
T1101 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1560550306 Jul 31 05:48:03 PM PDT 24 Jul 31 05:48:06 PM PDT 24 131599579 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1120314354 Jul 31 05:47:54 PM PDT 24 Jul 31 05:48:12 PM PDT 24 1864434518 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2770362615 Jul 31 05:47:41 PM PDT 24 Jul 31 05:47:43 PM PDT 24 96356860 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3170762991 Jul 31 05:47:50 PM PDT 24 Jul 31 05:47:57 PM PDT 24 105174707 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1046222160 Jul 31 05:47:54 PM PDT 24 Jul 31 05:47:58 PM PDT 24 236712211 ps
T1106 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.626276500 Jul 31 05:48:11 PM PDT 24 Jul 31 05:48:12 PM PDT 24 18356590 ps
T1107 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1136647201 Jul 31 05:47:58 PM PDT 24 Jul 31 05:47:59 PM PDT 24 18367428 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3380005851 Jul 31 05:48:10 PM PDT 24 Jul 31 05:48:14 PM PDT 24 102508624 ps
T1109 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4160149313 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:04 PM PDT 24 156567319 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2959666245 Jul 31 05:47:52 PM PDT 24 Jul 31 05:47:53 PM PDT 24 30428862 ps
T1111 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3047217940 Jul 31 05:47:59 PM PDT 24 Jul 31 05:48:00 PM PDT 24 49511111 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.950969502 Jul 31 05:47:57 PM PDT 24 Jul 31 05:47:58 PM PDT 24 37793265 ps
T1113 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.313307715 Jul 31 05:48:00 PM PDT 24 Jul 31 05:48:03 PM PDT 24 147554514 ps
T1114 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3766145809 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:10 PM PDT 24 13074478 ps
T1115 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3877387294 Jul 31 05:47:59 PM PDT 24 Jul 31 05:48:03 PM PDT 24 242050632 ps
T1116 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.36127920 Jul 31 05:48:16 PM PDT 24 Jul 31 05:48:17 PM PDT 24 47363839 ps
T1117 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1546089533 Jul 31 05:47:53 PM PDT 24 Jul 31 05:47:57 PM PDT 24 129678720 ps
T1118 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2522047262 Jul 31 05:48:01 PM PDT 24 Jul 31 05:48:05 PM PDT 24 1247114178 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.455556734 Jul 31 05:47:43 PM PDT 24 Jul 31 05:47:51 PM PDT 24 1173608884 ps
T1120 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1649068444 Jul 31 05:48:03 PM PDT 24 Jul 31 05:48:07 PM PDT 24 61859135 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.272718002 Jul 31 05:47:44 PM PDT 24 Jul 31 05:47:45 PM PDT 24 51516023 ps
T1122 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1798409513 Jul 31 05:48:08 PM PDT 24 Jul 31 05:48:08 PM PDT 24 44540223 ps
T1123 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1802752144 Jul 31 05:48:13 PM PDT 24 Jul 31 05:48:14 PM PDT 24 11579553 ps
T1124 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3781351992 Jul 31 05:48:12 PM PDT 24 Jul 31 05:48:13 PM PDT 24 32006612 ps
T1125 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2054704398 Jul 31 05:48:06 PM PDT 24 Jul 31 05:48:10 PM PDT 24 189426673 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4177381920 Jul 31 05:47:57 PM PDT 24 Jul 31 05:48:31 PM PDT 24 2180866684 ps
T1127 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.929424437 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:10 PM PDT 24 20060643 ps
T1128 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.350759791 Jul 31 05:48:14 PM PDT 24 Jul 31 05:48:17 PM PDT 24 149449234 ps
T1129 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1374912428 Jul 31 05:47:48 PM PDT 24 Jul 31 05:47:51 PM PDT 24 178082761 ps
T168 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2855944704 Jul 31 05:47:59 PM PDT 24 Jul 31 05:48:21 PM PDT 24 6126589660 ps
T1130 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2664303805 Jul 31 05:48:09 PM PDT 24 Jul 31 05:48:10 PM PDT 24 50314414 ps
T1131 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4187883945 Jul 31 05:47:57 PM PDT 24 Jul 31 05:48:00 PM PDT 24 377654939 ps

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1778439373
Short name T8
Test name
Test status
Simulation time 12857169355 ps
CPU time 139.18 seconds
Started Jul 31 07:38:33 PM PDT 24
Finished Jul 31 07:40:52 PM PDT 24
Peak memory 257796 kb
Host smart-ec687c14-05da-4d58-88a5-3dc96f818ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778439373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1778439373
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3624910843
Short name T32
Test name
Test status
Simulation time 18447055952 ps
CPU time 127.66 seconds
Started Jul 31 07:38:16 PM PDT 24
Finished Jul 31 07:40:24 PM PDT 24
Peak memory 273264 kb
Host smart-363b04c5-1594-496b-b82d-abf04d372aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624910843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3624910843
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.472871598
Short name T24
Test name
Test status
Simulation time 34324201623 ps
CPU time 12.16 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:42 PM PDT 24
Peak memory 241128 kb
Host smart-5e53c709-3043-4910-a67f-f5f51082d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472871598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
472871598
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.166549489
Short name T19
Test name
Test status
Simulation time 12512488894 ps
CPU time 212.87 seconds
Started Jul 31 07:35:41 PM PDT 24
Finished Jul 31 07:39:14 PM PDT 24
Peak memory 263952 kb
Host smart-44b3e238-bbf0-4ce3-8094-d00f9d6ba122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166549489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.166549489
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3578745243
Short name T102
Test name
Test status
Simulation time 2803541483 ps
CPU time 16.14 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:21 PM PDT 24
Peak memory 215384 kb
Host smart-bbffef42-789f-4555-a0c0-a99b024c5fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578745243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3578745243
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1873458400
Short name T46
Test name
Test status
Simulation time 53769675245 ps
CPU time 358.97 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:42:32 PM PDT 24
Peak memory 252112 kb
Host smart-d9056a77-eaad-4508-b52d-2726e2004f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873458400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1873458400
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3312926756
Short name T126
Test name
Test status
Simulation time 844332744931 ps
CPU time 1111.71 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:56:36 PM PDT 24
Peak memory 268288 kb
Host smart-63fff44d-04e5-4aea-add6-17b9f6d055f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312926756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3312926756
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.411205394
Short name T56
Test name
Test status
Simulation time 23452359581 ps
CPU time 306.86 seconds
Started Jul 31 07:38:03 PM PDT 24
Finished Jul 31 07:43:10 PM PDT 24
Peak memory 273112 kb
Host smart-9afd9756-11a0-4c9e-9113-1ba5c6bf9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411205394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.411205394
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2218652395
Short name T76
Test name
Test status
Simulation time 17274826 ps
CPU time 0.77 seconds
Started Jul 31 07:34:50 PM PDT 24
Finished Jul 31 07:34:51 PM PDT 24
Peak memory 216440 kb
Host smart-4c3a33ad-8115-4f3e-8392-279e1bd289c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218652395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2218652395
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2013083148
Short name T73
Test name
Test status
Simulation time 222249485 ps
CPU time 4.89 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 215288 kb
Host smart-4d8fdc9c-12b5-4ba0-b409-c0e33b2773e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013083148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
013083148
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1494043580
Short name T35
Test name
Test status
Simulation time 122869660251 ps
CPU time 1063.72 seconds
Started Jul 31 07:35:33 PM PDT 24
Finished Jul 31 07:53:17 PM PDT 24
Peak memory 285868 kb
Host smart-d1523ec1-d115-4708-93bb-37025e931743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494043580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1494043580
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3047230053
Short name T17
Test name
Test status
Simulation time 108635370084 ps
CPU time 285.63 seconds
Started Jul 31 07:35:25 PM PDT 24
Finished Jul 31 07:40:11 PM PDT 24
Peak memory 268648 kb
Host smart-865f78a1-2dc0-40a2-bcf4-e52a3ee9c2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047230053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3047230053
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1056996182
Short name T15
Test name
Test status
Simulation time 115694000 ps
CPU time 1.09 seconds
Started Jul 31 07:34:55 PM PDT 24
Finished Jul 31 07:34:56 PM PDT 24
Peak memory 236908 kb
Host smart-4e78a74b-dd0b-4be1-ad53-8f40fd43c0bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056996182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1056996182
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4047275780
Short name T143
Test name
Test status
Simulation time 729985803 ps
CPU time 7.92 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:23 PM PDT 24
Peak memory 241208 kb
Host smart-8844b5c4-ed2e-46b6-8a99-0e7b0241ed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047275780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4047275780
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3839092560
Short name T298
Test name
Test status
Simulation time 304272829649 ps
CPU time 698.75 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:49:36 PM PDT 24
Peak memory 281412 kb
Host smart-e986ead3-541c-470d-9004-f6b3d321b95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839092560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3839092560
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1665919322
Short name T276
Test name
Test status
Simulation time 6189992756 ps
CPU time 144.82 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:40:13 PM PDT 24
Peak memory 274064 kb
Host smart-5edb6e0a-d296-4085-bbd7-fb746a5ba9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665919322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1665919322
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1052569553
Short name T16
Test name
Test status
Simulation time 190110656939 ps
CPU time 414.7 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:45:26 PM PDT 24
Peak memory 265996 kb
Host smart-7d5324c4-7660-4b2f-974b-ce2f06570a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052569553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1052569553
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1839757521
Short name T86
Test name
Test status
Simulation time 57329825 ps
CPU time 1.16 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:47:52 PM PDT 24
Peak memory 206920 kb
Host smart-7529a4c6-8e47-4977-8b89-cc4db5483393
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839757521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1839757521
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3815031677
Short name T2
Test name
Test status
Simulation time 129856507349 ps
CPU time 182.46 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:38:15 PM PDT 24
Peak memory 253428 kb
Host smart-6ebf7268-eb23-423b-9a33-b9ff41ba5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815031677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3815031677
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2558272256
Short name T22
Test name
Test status
Simulation time 35949057328 ps
CPU time 407.49 seconds
Started Jul 31 07:36:55 PM PDT 24
Finished Jul 31 07:43:43 PM PDT 24
Peak memory 269476 kb
Host smart-c03e8a20-e6a4-4d28-95fd-eba542457e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558272256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2558272256
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.597700271
Short name T275
Test name
Test status
Simulation time 72588702161 ps
CPU time 296.63 seconds
Started Jul 31 07:37:01 PM PDT 24
Finished Jul 31 07:41:58 PM PDT 24
Peak memory 265576 kb
Host smart-d1b886e9-cdd0-4d87-bb71-968b32087370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597700271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.597700271
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3888466305
Short name T180
Test name
Test status
Simulation time 43740945958 ps
CPU time 510.27 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:46:10 PM PDT 24
Peak memory 264036 kb
Host smart-a82629b5-cf7f-4301-bc92-e52734a6509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888466305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3888466305
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4261491513
Short name T185
Test name
Test status
Simulation time 161068967800 ps
CPU time 527.66 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:47:12 PM PDT 24
Peak memory 265956 kb
Host smart-feb111a9-8e81-49e6-89ca-8e908729a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261491513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4261491513
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1760120539
Short name T25
Test name
Test status
Simulation time 27178395901 ps
CPU time 18.84 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:38:32 PM PDT 24
Peak memory 216748 kb
Host smart-5eb922e4-2dac-4119-be1d-9a7f52fa3ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760120539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1760120539
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.931076611
Short name T182
Test name
Test status
Simulation time 81929085928 ps
CPU time 308.96 seconds
Started Jul 31 07:37:01 PM PDT 24
Finished Jul 31 07:42:10 PM PDT 24
Peak memory 255980 kb
Host smart-1c7c770e-ee84-417d-9031-410bda1aa5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931076611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.931076611
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.173355155
Short name T68
Test name
Test status
Simulation time 50295789 ps
CPU time 0.75 seconds
Started Jul 31 07:34:59 PM PDT 24
Finished Jul 31 07:34:59 PM PDT 24
Peak memory 205780 kb
Host smart-a2700b7b-11a0-4b2d-aa00-15050912329d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173355155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.173355155
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2855944704
Short name T168
Test name
Test status
Simulation time 6126589660 ps
CPU time 21.42 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:21 PM PDT 24
Peak memory 215720 kb
Host smart-b2c5bcf2-fc68-4cc1-860a-52b6626479ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855944704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2855944704
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2628664456
Short name T36
Test name
Test status
Simulation time 113352700381 ps
CPU time 283.27 seconds
Started Jul 31 07:38:42 PM PDT 24
Finished Jul 31 07:43:25 PM PDT 24
Peak memory 251816 kb
Host smart-4acc9497-fbb5-4eee-aea4-ae11e895fddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628664456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2628664456
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.788369650
Short name T183
Test name
Test status
Simulation time 6775864601 ps
CPU time 145.82 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:37:49 PM PDT 24
Peak memory 271948 kb
Host smart-b8bea2a3-946f-4339-88e8-65c4fac3ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788369650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.788369650
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2820893136
Short name T268
Test name
Test status
Simulation time 30245030432 ps
CPU time 89.39 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 250660 kb
Host smart-175af2ea-b31e-421b-82e5-df1b67a52063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820893136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2820893136
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3762696279
Short name T208
Test name
Test status
Simulation time 4149762724 ps
CPU time 54.87 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:37:12 PM PDT 24
Peak memory 250656 kb
Host smart-79a5f35c-2ed6-495d-a278-0db33dcf1df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762696279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3762696279
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3382678513
Short name T49
Test name
Test status
Simulation time 34189657046 ps
CPU time 274.88 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:41:42 PM PDT 24
Peak memory 266096 kb
Host smart-a579571b-2d3e-4869-9da9-0a1ec8ae6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382678513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3382678513
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2013008932
Short name T195
Test name
Test status
Simulation time 15549767718 ps
CPU time 92.49 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:39:37 PM PDT 24
Peak memory 257224 kb
Host smart-2199a127-35de-40af-b067-49ccde5ce2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013008932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2013008932
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1404901926
Short name T1049
Test name
Test status
Simulation time 854200786 ps
CPU time 4.77 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 215228 kb
Host smart-c0c73f41-4ec7-4d2b-8fbd-843614c0a5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404901926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1404901926
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3842863636
Short name T1086
Test name
Test status
Simulation time 212296066 ps
CPU time 13.08 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 215108 kb
Host smart-29f9ad02-a7f0-4465-bf6a-e43b60fb0abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842863636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3842863636
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.834172363
Short name T176
Test name
Test status
Simulation time 11925013324 ps
CPU time 139.02 seconds
Started Jul 31 07:35:49 PM PDT 24
Finished Jul 31 07:38:08 PM PDT 24
Peak memory 253376 kb
Host smart-4ac17ae0-4834-4099-a5b7-49145b0d79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834172363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.834172363
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3842227448
Short name T911
Test name
Test status
Simulation time 442745582 ps
CPU time 6.43 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 233140 kb
Host smart-2918cecb-aa25-4a16-baa2-58b0949377f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842227448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3842227448
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1060808574
Short name T211
Test name
Test status
Simulation time 94881159783 ps
CPU time 396.86 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:43:25 PM PDT 24
Peak memory 260372 kb
Host smart-dd8b4e54-f062-44fc-95fa-00887bf4f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060808574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1060808574
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3006319820
Short name T290
Test name
Test status
Simulation time 968603360 ps
CPU time 21.14 seconds
Started Jul 31 07:37:09 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 233220 kb
Host smart-38138ea6-082b-4e52-8747-470684f63d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006319820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3006319820
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1620944170
Short name T47
Test name
Test status
Simulation time 23776819642 ps
CPU time 76.06 seconds
Started Jul 31 07:35:28 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 257740 kb
Host smart-75f76237-c6d1-4b4c-9b0e-e9b59f6cebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620944170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1620944170
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1820391013
Short name T93
Test name
Test status
Simulation time 126215423 ps
CPU time 2.96 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:37:32 PM PDT 24
Peak memory 224860 kb
Host smart-3528999d-97b7-4dc4-9858-fea28c98152f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820391013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1820391013
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2195910421
Short name T280
Test name
Test status
Simulation time 43118886086 ps
CPU time 319.01 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:40:56 PM PDT 24
Peak memory 265940 kb
Host smart-d7693a36-acc6-40ee-987d-26048d087c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195910421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2195910421
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.382280486
Short name T272
Test name
Test status
Simulation time 53572158704 ps
CPU time 224.97 seconds
Started Jul 31 07:35:35 PM PDT 24
Finished Jul 31 07:39:20 PM PDT 24
Peak memory 256776 kb
Host smart-cd3ddfb3-6bfe-4bc8-852f-f9051603c3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382280486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.382280486
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1313206270
Short name T259
Test name
Test status
Simulation time 13774268128 ps
CPU time 136.57 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:38:47 PM PDT 24
Peak memory 256520 kb
Host smart-836312d5-3fb7-4370-836b-9a86350b3803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313206270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1313206270
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.821289211
Short name T971
Test name
Test status
Simulation time 130207927 ps
CPU time 4.58 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:36:36 PM PDT 24
Peak memory 224816 kb
Host smart-b391c894-dbef-4e2a-ad5c-1e9dcf3e6b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821289211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.821289211
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4106394869
Short name T181
Test name
Test status
Simulation time 14559652422 ps
CPU time 209.11 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:41:44 PM PDT 24
Peak memory 272612 kb
Host smart-d3cbd33b-5096-408e-be27-3fdaae84a69d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106394869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4106394869
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1978930168
Short name T1055
Test name
Test status
Simulation time 737811708 ps
CPU time 4.73 seconds
Started Jul 31 05:47:49 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 215404 kb
Host smart-06ba0ea7-93d6-48b5-88f2-35affc47dd80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978930168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
978930168
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3800371684
Short name T1052
Test name
Test status
Simulation time 2851054024 ps
CPU time 15.16 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 215256 kb
Host smart-ee0f7df0-001f-4af5-bd66-6d0ef822f8c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800371684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3800371684
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3149556165
Short name T125
Test name
Test status
Simulation time 1663294169 ps
CPU time 22.61 seconds
Started Jul 31 05:47:44 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 206960 kb
Host smart-ce346108-e2e4-4b4b-854e-853067c71f3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149556165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3149556165
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3750476746
Short name T88
Test name
Test status
Simulation time 38740053 ps
CPU time 1.37 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 215132 kb
Host smart-e7b9b1b0-e6e8-449d-9a49-8e16d8d10e6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750476746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3750476746
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1374912428
Short name T1129
Test name
Test status
Simulation time 178082761 ps
CPU time 3.32 seconds
Started Jul 31 05:47:48 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 217112 kb
Host smart-062ec8ab-fa33-478b-b8c1-bafaf6d51e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374912428 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1374912428
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2137038982
Short name T1057
Test name
Test status
Simulation time 166292529 ps
CPU time 2.44 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:47:52 PM PDT 24
Peak memory 215236 kb
Host smart-790e1ba7-198d-45b2-97cd-923fee7b3776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137038982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
137038982
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.272718002
Short name T1121
Test name
Test status
Simulation time 51516023 ps
CPU time 0.76 seconds
Started Jul 31 05:47:44 PM PDT 24
Finished Jul 31 05:47:45 PM PDT 24
Peak memory 203676 kb
Host smart-45b69744-5ce3-46b8-ba71-7bd19251cbee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272718002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.272718002
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1939629743
Short name T1091
Test name
Test status
Simulation time 18255339 ps
CPU time 1.27 seconds
Started Jul 31 05:47:49 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 215064 kb
Host smart-59dd0b80-a408-4e46-adaf-34632b3d2b01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939629743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1939629743
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2672488931
Short name T1040
Test name
Test status
Simulation time 33282308 ps
CPU time 0.66 seconds
Started Jul 31 05:47:49 PM PDT 24
Finished Jul 31 05:47:50 PM PDT 24
Peak memory 203656 kb
Host smart-4dfc2cc6-cdac-42d5-819c-cc17a3035e61
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672488931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2672488931
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2844442180
Short name T1089
Test name
Test status
Simulation time 48361374 ps
CPU time 1.96 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:49 PM PDT 24
Peak memory 215260 kb
Host smart-1efcf318-d867-4aac-8660-46c97057499b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844442180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2844442180
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4106318446
Short name T1085
Test name
Test status
Simulation time 755213656 ps
CPU time 3.14 seconds
Started Jul 31 05:47:45 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 215324 kb
Host smart-609405fe-d07d-4375-8e9c-81db9c2c4f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106318446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
106318446
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1241452891
Short name T163
Test name
Test status
Simulation time 2244721699 ps
CPU time 15.78 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:48:07 PM PDT 24
Peak memory 215324 kb
Host smart-6fd0b6de-f570-481f-8c6a-9e4b8460a38c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241452891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1241452891
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.455556734
Short name T1119
Test name
Test status
Simulation time 1173608884 ps
CPU time 7.75 seconds
Started Jul 31 05:47:43 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 206952 kb
Host smart-f417456b-26e1-469f-8873-ac2ea77b4d0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455556734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.455556734
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.851121032
Short name T1075
Test name
Test status
Simulation time 11206940086 ps
CPU time 38.96 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:48:30 PM PDT 24
Peak memory 215244 kb
Host smart-a334a81b-fbb0-4d84-8825-d9d604cbdc40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851121032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.851121032
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2271260596
Short name T148
Test name
Test status
Simulation time 142156511 ps
CPU time 1.22 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 217188 kb
Host smart-57236bc2-c37b-4b8f-a3ed-e606c94e0eee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271260596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2271260596
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2770362615
Short name T1103
Test name
Test status
Simulation time 96356860 ps
CPU time 1.69 seconds
Started Jul 31 05:47:41 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 216188 kb
Host smart-bbe36b88-dbcb-4ea6-a8a6-2bd8a96e9d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770362615 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2770362615
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1597613206
Short name T115
Test name
Test status
Simulation time 339344963 ps
CPU time 2.46 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 215156 kb
Host smart-b88ce37f-fd33-4527-bb1a-fe9d62ea9cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597613206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
597613206
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.293617721
Short name T1072
Test name
Test status
Simulation time 17717633 ps
CPU time 0.77 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 203632 kb
Host smart-b4a4b496-ea74-429c-b832-035c7d5566cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293617721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.293617721
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1017497113
Short name T117
Test name
Test status
Simulation time 244497926 ps
CPU time 2.32 seconds
Started Jul 31 05:47:56 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 215184 kb
Host smart-b3c788e7-56e1-445b-bf98-d06991fef853
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017497113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1017497113
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.438816791
Short name T1018
Test name
Test status
Simulation time 67876215 ps
CPU time 0.69 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:47:55 PM PDT 24
Peak memory 203968 kb
Host smart-c9b6047f-ab28-43b0-ba49-734c8260a111
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438816791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.438816791
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3294002087
Short name T150
Test name
Test status
Simulation time 105986701 ps
CPU time 1.91 seconds
Started Jul 31 05:47:47 PM PDT 24
Finished Jul 31 05:47:49 PM PDT 24
Peak memory 215168 kb
Host smart-c54f5241-b261-4ffb-ad2d-270ea808d617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294002087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3294002087
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2854193048
Short name T169
Test name
Test status
Simulation time 303257669 ps
CPU time 19.68 seconds
Started Jul 31 05:47:44 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 215200 kb
Host smart-49f1b3a9-7b00-41f0-8d4a-367f45703220
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854193048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2854193048
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3400103627
Short name T152
Test name
Test status
Simulation time 95678759 ps
CPU time 1.9 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 216188 kb
Host smart-f21759c3-10a3-4984-8023-97d65fda3586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400103627 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3400103627
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2471261325
Short name T119
Test name
Test status
Simulation time 29312031 ps
CPU time 1.88 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 206952 kb
Host smart-a125472b-9520-41b8-8fad-22b097ed1d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471261325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2471261325
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3141403036
Short name T1064
Test name
Test status
Simulation time 15422836 ps
CPU time 0.76 seconds
Started Jul 31 05:47:56 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 203624 kb
Host smart-0686cd65-1d5c-417c-823e-f5fd73b91ab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141403036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3141403036
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3877387294
Short name T1115
Test name
Test status
Simulation time 242050632 ps
CPU time 3.75 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 215140 kb
Host smart-4544c8f5-866c-4fac-be7a-4333e5f4ea2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877387294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3877387294
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1118613139
Short name T1069
Test name
Test status
Simulation time 108222641 ps
CPU time 2.11 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 215304 kb
Host smart-ba969915-dfcd-402b-884b-ddbfcc1738fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118613139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1118613139
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4126435223
Short name T161
Test name
Test status
Simulation time 3479067444 ps
CPU time 22.8 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:48:19 PM PDT 24
Peak memory 215592 kb
Host smart-36d00f17-9f1b-4213-b862-5a04d30800c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126435223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4126435223
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.868449636
Short name T1031
Test name
Test status
Simulation time 88275901 ps
CPU time 3.06 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 217860 kb
Host smart-a4e69f48-83ad-4d11-811e-38480897155f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868449636 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.868449636
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3427135177
Short name T1058
Test name
Test status
Simulation time 17283634 ps
CPU time 1.18 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 206964 kb
Host smart-59dcfccf-ff44-43ff-a834-84e7082e85a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427135177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3427135177
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1200640223
Short name T1095
Test name
Test status
Simulation time 36263812 ps
CPU time 0.69 seconds
Started Jul 31 05:48:05 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 203992 kb
Host smart-7278db96-43ad-4702-8830-c22a3c528f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200640223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1200640223
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3644610635
Short name T1028
Test name
Test status
Simulation time 567218003 ps
CPU time 1.88 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 215108 kb
Host smart-5e9156b7-e3b1-4906-8bc3-8baeaa9297ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644610635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3644610635
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3380005851
Short name T1108
Test name
Test status
Simulation time 102508624 ps
CPU time 3.23 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 215364 kb
Host smart-62a88cb8-7d8e-4a42-903d-04c790c6a0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380005851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3380005851
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1397302140
Short name T112
Test name
Test status
Simulation time 341329208 ps
CPU time 2.66 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 217296 kb
Host smart-88ee0e1b-3db6-4ae5-a499-9f5f4ab6dc75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397302140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1397302140
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2084045338
Short name T1073
Test name
Test status
Simulation time 246058419 ps
CPU time 2.05 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 215188 kb
Host smart-d119430d-3eab-42ff-be52-54388b58a445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084045338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2084045338
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3821552145
Short name T1059
Test name
Test status
Simulation time 18783881 ps
CPU time 0.8 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 203648 kb
Host smart-5e1c1681-af0c-4853-86e4-156895363667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821552145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3821552145
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.287782989
Short name T1082
Test name
Test status
Simulation time 717723053 ps
CPU time 4.05 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 215120 kb
Host smart-c296af74-583c-493f-9e22-d094235fb87c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287782989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.287782989
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3785358026
Short name T74
Test name
Test status
Simulation time 42348105 ps
CPU time 1.66 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215296 kb
Host smart-bd88dd1d-0dc4-4e95-97d1-69a110418391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785358026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3785358026
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.67201863
Short name T1093
Test name
Test status
Simulation time 323429325 ps
CPU time 7.64 seconds
Started Jul 31 05:48:05 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215356 kb
Host smart-7b514495-2b25-4911-9914-bf424941e58d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67201863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_
tl_intg_err.67201863
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.929926957
Short name T1017
Test name
Test status
Simulation time 154543413 ps
CPU time 2.6 seconds
Started Jul 31 05:48:11 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 217060 kb
Host smart-ad9b7d76-b30d-4f1a-beb1-559f187d7f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929926957 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.929926957
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2083891848
Short name T1053
Test name
Test status
Simulation time 165499503 ps
CPU time 2.64 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 215188 kb
Host smart-d49a7068-f394-4033-984a-344c6d34722d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083891848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2083891848
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3043518564
Short name T1087
Test name
Test status
Simulation time 39859231 ps
CPU time 0.71 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 203656 kb
Host smart-b28c255c-ee87-4c35-90f6-1815a236e34d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043518564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3043518564
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3291194579
Short name T1020
Test name
Test status
Simulation time 169824765 ps
CPU time 2.84 seconds
Started Jul 31 05:48:07 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 215696 kb
Host smart-a3c6cde2-37cd-4232-a611-e32b487b4fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291194579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3291194579
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.813595510
Short name T1029
Test name
Test status
Simulation time 333718685 ps
CPU time 4.17 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 215216 kb
Host smart-121f8fe5-335d-4ac2-b525-5b4baee086f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813595510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.813595510
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1017407962
Short name T165
Test name
Test status
Simulation time 205955278 ps
CPU time 12.24 seconds
Started Jul 31 05:48:14 PM PDT 24
Finished Jul 31 05:48:26 PM PDT 24
Peak memory 215236 kb
Host smart-824a6ec5-c9fa-4ead-a58b-4f3664182ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017407962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1017407962
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1482439803
Short name T1098
Test name
Test status
Simulation time 55752045 ps
CPU time 1.89 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 216248 kb
Host smart-ec6be0de-1b62-444d-9f99-f9f776a3a228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482439803 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1482439803
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1490869836
Short name T116
Test name
Test status
Simulation time 145688791 ps
CPU time 1.9 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 206952 kb
Host smart-1ef180ac-c538-4a78-ab0b-e826adadda1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490869836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1490869836
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2855885327
Short name T1043
Test name
Test status
Simulation time 12632768 ps
CPU time 0.79 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 203656 kb
Host smart-3a49b16d-e45c-4559-8aef-607feb0b8799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855885327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2855885327
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3710652173
Short name T1100
Test name
Test status
Simulation time 75219201 ps
CPU time 1.86 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215228 kb
Host smart-8309ccac-5d88-4bb3-8544-1f52b63826ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710652173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3710652173
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.228180230
Short name T1061
Test name
Test status
Simulation time 31389507 ps
CPU time 1.96 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 206988 kb
Host smart-1f079a20-f658-40c5-954d-0c898178c842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228180230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.228180230
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2950823396
Short name T1068
Test name
Test status
Simulation time 1189225639 ps
CPU time 16.72 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:20 PM PDT 24
Peak memory 215608 kb
Host smart-54a0c1b1-e8ce-46dc-be27-f1fce8537b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950823396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2950823396
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3692276811
Short name T1065
Test name
Test status
Simulation time 241749472 ps
CPU time 1.7 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 215256 kb
Host smart-8496d3e5-c8d9-4828-a7e6-59bea091a03a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692276811 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3692276811
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.610310158
Short name T149
Test name
Test status
Simulation time 105526158 ps
CPU time 2.52 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215172 kb
Host smart-64dfc07c-0950-457d-af06-1efe84543283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610310158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.610310158
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2785151129
Short name T1062
Test name
Test status
Simulation time 39860944 ps
CPU time 0.77 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 203644 kb
Host smart-1137b3ed-e7c5-4c80-b961-be6a1d6f742d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785151129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2785151129
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1892643048
Short name T1097
Test name
Test status
Simulation time 147938288 ps
CPU time 3.23 seconds
Started Jul 31 05:48:07 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 215116 kb
Host smart-af05b017-4161-42e7-a991-bed6c72966b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892643048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1892643048
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.147061475
Short name T105
Test name
Test status
Simulation time 330012551 ps
CPU time 2.51 seconds
Started Jul 31 05:48:07 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215244 kb
Host smart-cb4d2ce9-6e0f-4d49-8814-2696b248ca45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147061475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.147061475
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4048128485
Short name T114
Test name
Test status
Simulation time 206225104 ps
CPU time 12.61 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215168 kb
Host smart-143739e8-a4e4-43a6-b330-64278455963f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048128485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4048128485
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.529931934
Short name T99
Test name
Test status
Simulation time 229892699 ps
CPU time 4.02 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 218636 kb
Host smart-bb5fea80-4237-43f3-b128-04f4b2db0457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529931934 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.529931934
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.414236643
Short name T1030
Test name
Test status
Simulation time 75277131 ps
CPU time 1.37 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 206968 kb
Host smart-d50f3df2-b3d1-4a5e-a62c-21be54efcab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414236643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.414236643
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.526387155
Short name T1035
Test name
Test status
Simulation time 15187763 ps
CPU time 0.82 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 203684 kb
Host smart-bcc0ae40-13cf-475c-8655-b3a1d17c60ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526387155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.526387155
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2383335940
Short name T1076
Test name
Test status
Simulation time 216881630 ps
CPU time 4.56 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215084 kb
Host smart-e336e04a-9f7c-47a0-9b2a-2473646af7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383335940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2383335940
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.313307715
Short name T1113
Test name
Test status
Simulation time 147554514 ps
CPU time 3.79 seconds
Started Jul 31 05:48:00 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 215316 kb
Host smart-ff9133be-9ece-4190-a859-7bf0a5c4e89e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313307715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.313307715
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4211425551
Short name T162
Test name
Test status
Simulation time 1328552688 ps
CPU time 15.36 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:18 PM PDT 24
Peak memory 218724 kb
Host smart-67ec0e5d-cc6b-430f-a87f-a9dd5ce53e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211425551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4211425551
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.392168585
Short name T1054
Test name
Test status
Simulation time 91692258 ps
CPU time 2.72 seconds
Started Jul 31 05:48:04 PM PDT 24
Finished Jul 31 05:48:07 PM PDT 24
Peak memory 216596 kb
Host smart-f3d16d69-c8e4-46a0-96f6-366894d826ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392168585 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.392168585
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2995740663
Short name T1044
Test name
Test status
Simulation time 78990346 ps
CPU time 1.46 seconds
Started Jul 31 05:48:05 PM PDT 24
Finished Jul 31 05:48:07 PM PDT 24
Peak memory 207160 kb
Host smart-2fcec0cf-5a27-41ee-a5a3-227057503b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995740663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2995740663
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1683826848
Short name T1041
Test name
Test status
Simulation time 11819435 ps
CPU time 0.72 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 203992 kb
Host smart-d6241a37-d5be-4575-974f-721583793114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683826848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1683826848
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2546773310
Short name T1033
Test name
Test status
Simulation time 524574829 ps
CPU time 2.49 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215192 kb
Host smart-95786f83-835f-4009-8bca-201236c24eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546773310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2546773310
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2828789545
Short name T110
Test name
Test status
Simulation time 318274991 ps
CPU time 2.6 seconds
Started Jul 31 05:48:02 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 215248 kb
Host smart-0451b77a-6c47-43c8-b5ea-6e2240854120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828789545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2828789545
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.934971072
Short name T1080
Test name
Test status
Simulation time 2302023366 ps
CPU time 14.18 seconds
Started Jul 31 05:48:11 PM PDT 24
Finished Jul 31 05:48:26 PM PDT 24
Peak memory 215244 kb
Host smart-b6d760a2-1126-4620-9967-63b954c497bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934971072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.934971072
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1560550306
Short name T1101
Test name
Test status
Simulation time 131599579 ps
CPU time 3.65 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 216628 kb
Host smart-c4d8a3af-cbfb-497e-840c-800c8ea73d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560550306 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1560550306
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4160149313
Short name T1109
Test name
Test status
Simulation time 156567319 ps
CPU time 2.38 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 206904 kb
Host smart-23285055-7eb7-49ec-9897-98acabd60c5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160149313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4160149313
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3679001831
Short name T1010
Test name
Test status
Simulation time 28877430 ps
CPU time 0.68 seconds
Started Jul 31 05:48:16 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 203708 kb
Host smart-c77a3b4e-eb78-459b-add8-78746f687ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679001831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3679001831
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2054704398
Short name T1125
Test name
Test status
Simulation time 189426673 ps
CPU time 4.21 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 215204 kb
Host smart-d2dfba33-6e76-4b75-a849-2bc9cbdb4b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054704398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2054704398
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4059592905
Short name T100
Test name
Test status
Simulation time 779819745 ps
CPU time 12.38 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:15 PM PDT 24
Peak memory 215580 kb
Host smart-ac42943c-c717-4fa3-8d17-4e007a09606d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059592905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4059592905
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.350759791
Short name T1128
Test name
Test status
Simulation time 149449234 ps
CPU time 3.07 seconds
Started Jul 31 05:48:14 PM PDT 24
Finished Jul 31 05:48:17 PM PDT 24
Peak memory 217372 kb
Host smart-43efdd28-6c18-4476-b303-18eeb784d19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350759791 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.350759791
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2199041990
Short name T1036
Test name
Test status
Simulation time 207803408 ps
CPU time 1.74 seconds
Started Jul 31 05:48:11 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 215268 kb
Host smart-1f71b0d8-bb70-43ff-bab2-30d0855521bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199041990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2199041990
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.872983110
Short name T1048
Test name
Test status
Simulation time 28264236 ps
CPU time 0.72 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203624 kb
Host smart-3549c492-4a26-44f8-bf30-c211d5d6369b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872983110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.872983110
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1024904473
Short name T151
Test name
Test status
Simulation time 759682994 ps
CPU time 3.96 seconds
Started Jul 31 05:48:16 PM PDT 24
Finished Jul 31 05:48:20 PM PDT 24
Peak memory 215216 kb
Host smart-5e21c955-6706-411b-b712-806ef4ac6abf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024904473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1024904473
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2262663574
Short name T156
Test name
Test status
Simulation time 180990882 ps
CPU time 4.49 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 215308 kb
Host smart-e054c6b8-3c9e-4645-9fb6-e5c0ee745b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262663574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2262663574
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1315689965
Short name T164
Test name
Test status
Simulation time 2048417114 ps
CPU time 22.97 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:31 PM PDT 24
Peak memory 216500 kb
Host smart-6aa0876e-4bdd-448f-934b-f2039629537a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315689965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1315689965
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.859628189
Short name T124
Test name
Test status
Simulation time 1241386645 ps
CPU time 22.13 seconds
Started Jul 31 05:47:55 PM PDT 24
Finished Jul 31 05:48:17 PM PDT 24
Peak memory 215180 kb
Host smart-d21c90f7-a62d-42f3-a9f4-7541a1f43f58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859628189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.859628189
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1239631671
Short name T1081
Test name
Test status
Simulation time 3613567784 ps
CPU time 36.13 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:48:26 PM PDT 24
Peak memory 215164 kb
Host smart-c7b64d11-cc37-4b1a-bb30-1ecaacd6ae4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239631671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1239631671
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.389306693
Short name T154
Test name
Test status
Simulation time 452069475 ps
CPU time 1.96 seconds
Started Jul 31 05:47:53 PM PDT 24
Finished Jul 31 05:47:55 PM PDT 24
Peak memory 216248 kb
Host smart-c741f672-7cec-45d0-a185-8226406b59c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389306693 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.389306693
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2959666245
Short name T1110
Test name
Test status
Simulation time 30428862 ps
CPU time 1.77 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 215116 kb
Host smart-e4a5e8fe-6250-4f9e-8274-4941a0ab66fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959666245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
959666245
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.218550555
Short name T1092
Test name
Test status
Simulation time 15275607 ps
CPU time 0.77 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 203624 kb
Host smart-dc101cb5-2aee-4446-a5c5-63ba5aaa812f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218550555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.218550555
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3767123587
Short name T1051
Test name
Test status
Simulation time 62989474 ps
CPU time 2.21 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 215128 kb
Host smart-7bbdf5cf-478f-47fa-a0d5-9beb928de113
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767123587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3767123587
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3515186405
Short name T1023
Test name
Test status
Simulation time 12213147 ps
CPU time 0.67 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 203636 kb
Host smart-3a14cae0-bbe2-45b7-aa53-844078dc6cd2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515186405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3515186405
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3291180841
Short name T1046
Test name
Test status
Simulation time 447179103 ps
CPU time 3.06 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:55 PM PDT 24
Peak memory 215208 kb
Host smart-9ac5a67c-3e58-4a57-b798-a3dcdcd6f5a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291180841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3291180841
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3366225983
Short name T108
Test name
Test status
Simulation time 116851854 ps
CPU time 3.94 seconds
Started Jul 31 05:47:48 PM PDT 24
Finished Jul 31 05:47:52 PM PDT 24
Peak memory 215300 kb
Host smart-ae478524-a98d-46d2-8ca8-a9c2ca16db17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366225983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
366225983
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3693321832
Short name T1071
Test name
Test status
Simulation time 300032157 ps
CPU time 19.28 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 215308 kb
Host smart-5a4eddc9-dbd1-49fe-a009-faad879aa650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693321832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3693321832
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2414525010
Short name T1021
Test name
Test status
Simulation time 41621733 ps
CPU time 0.75 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 203960 kb
Host smart-f6d56c24-d816-4d64-9004-064dddf60796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414525010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2414525010
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2315327054
Short name T1096
Test name
Test status
Simulation time 19835234 ps
CPU time 0.7 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 203652 kb
Host smart-57b97e73-c026-4d6e-806b-04a2a107c12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315327054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2315327054
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3766145809
Short name T1114
Test name
Test status
Simulation time 13074478 ps
CPU time 0.72 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 204008 kb
Host smart-9378117f-4f61-4d02-b9ee-629a2cdf71f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766145809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3766145809
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1262238104
Short name T1056
Test name
Test status
Simulation time 13739136 ps
CPU time 0.71 seconds
Started Jul 31 05:48:13 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203992 kb
Host smart-6540a3f6-471c-42b5-9b7c-020310a3d233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262238104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1262238104
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3263940626
Short name T1037
Test name
Test status
Simulation time 16879164 ps
CPU time 0.82 seconds
Started Jul 31 05:48:07 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 203680 kb
Host smart-11af8216-1e7e-4ae1-987a-9e34e45b9e6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263940626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3263940626
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.991727255
Short name T1015
Test name
Test status
Simulation time 13890651 ps
CPU time 0.72 seconds
Started Jul 31 05:48:15 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 203680 kb
Host smart-94c14e7b-7779-4db1-bc99-ba65746e299c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991727255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.991727255
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3287960046
Short name T1027
Test name
Test status
Simulation time 36918603 ps
CPU time 0.69 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 203992 kb
Host smart-2eea60fd-12f1-4c39-9b6c-97189095c362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287960046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3287960046
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1514198635
Short name T1022
Test name
Test status
Simulation time 19628155 ps
CPU time 0.78 seconds
Started Jul 31 05:48:13 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 203668 kb
Host smart-b564fe07-8b8c-42d0-8701-465519bbee4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514198635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1514198635
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1963486153
Short name T1078
Test name
Test status
Simulation time 15770160 ps
CPU time 0.78 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203680 kb
Host smart-2aea3a7e-f26c-4c49-b11f-6e384d9d923b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963486153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1963486153
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2592424051
Short name T1047
Test name
Test status
Simulation time 52469474 ps
CPU time 0.78 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 203968 kb
Host smart-21e3ea6f-d15f-4312-9949-589712fc96b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592424051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2592424051
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1120314354
Short name T1102
Test name
Test status
Simulation time 1864434518 ps
CPU time 17.62 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215156 kb
Host smart-331433bd-484a-4244-a841-4ca603f044dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120314354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1120314354
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4177381920
Short name T1126
Test name
Test status
Simulation time 2180866684 ps
CPU time 34.17 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:48:31 PM PDT 24
Peak memory 215640 kb
Host smart-448cae7f-2acd-4285-bdc8-1220d309622a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177381920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4177381920
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3983485716
Short name T1045
Test name
Test status
Simulation time 70609241 ps
CPU time 1.35 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:47:56 PM PDT 24
Peak memory 206932 kb
Host smart-44bfd258-2f46-4af9-86b3-0861a457c817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983485716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3983485716
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3300487432
Short name T109
Test name
Test status
Simulation time 373404529 ps
CPU time 2.76 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 216800 kb
Host smart-c8d72ba9-2854-4177-834c-e73145b9a282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300487432 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3300487432
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1499386517
Short name T121
Test name
Test status
Simulation time 34651050 ps
CPU time 1.34 seconds
Started Jul 31 05:48:00 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 206960 kb
Host smart-318ab21d-f29b-465b-9580-2f6b09d5b07e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499386517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
499386517
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2172098427
Short name T1032
Test name
Test status
Simulation time 16388313 ps
CPU time 0.78 seconds
Started Jul 31 05:47:51 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 203620 kb
Host smart-806c11ee-1658-4d90-bef5-3fc5e431e27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172098427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
172098427
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4285391265
Short name T1094
Test name
Test status
Simulation time 191423230 ps
CPU time 1.71 seconds
Started Jul 31 05:47:55 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 215180 kb
Host smart-74c2435f-dc23-4386-a043-cd85280beac3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285391265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4285391265
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3532102115
Short name T1038
Test name
Test status
Simulation time 107002725 ps
CPU time 0.68 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 203580 kb
Host smart-4427e934-4f2e-46d9-8d9e-dd4122c16d56
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532102115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3532102115
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1046222160
Short name T1105
Test name
Test status
Simulation time 236712211 ps
CPU time 3.87 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 215100 kb
Host smart-aa82038e-10c2-4808-8ba9-ee96740398e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046222160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1046222160
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1567188536
Short name T101
Test name
Test status
Simulation time 292181277 ps
CPU time 16.31 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 215424 kb
Host smart-a108175d-67f0-42c3-9202-5c4399af5c04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567188536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1567188536
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2259783488
Short name T1024
Test name
Test status
Simulation time 16029051 ps
CPU time 0.73 seconds
Started Jul 31 05:48:16 PM PDT 24
Finished Jul 31 05:48:17 PM PDT 24
Peak memory 203692 kb
Host smart-15612f70-d39e-4074-af6d-c9d96d1d4610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259783488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2259783488
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3954778531
Short name T1077
Test name
Test status
Simulation time 19109322 ps
CPU time 0.7 seconds
Started Jul 31 05:48:13 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 203652 kb
Host smart-ae67043a-53d9-4846-b321-30aa57a35628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954778531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3954778531
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2844718422
Short name T1016
Test name
Test status
Simulation time 24933429 ps
CPU time 0.77 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203992 kb
Host smart-6b296f21-3e0a-4e6a-8ea7-6d4d04990f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844718422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2844718422
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1074667049
Short name T1008
Test name
Test status
Simulation time 23608139 ps
CPU time 0.73 seconds
Started Jul 31 05:48:18 PM PDT 24
Finished Jul 31 05:48:18 PM PDT 24
Peak memory 203692 kb
Host smart-fdeb84c5-cf68-470b-92a6-ec574d450a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074667049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1074667049
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1019303582
Short name T1067
Test name
Test status
Simulation time 14876617 ps
CPU time 0.73 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203960 kb
Host smart-cf81b8cf-4e5f-4178-8336-ee150af9761b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019303582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1019303582
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.626276500
Short name T1106
Test name
Test status
Simulation time 18356590 ps
CPU time 0.73 seconds
Started Jul 31 05:48:11 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 203688 kb
Host smart-3336cb83-ae1a-4229-9764-351edb02e412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626276500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.626276500
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1724551173
Short name T1019
Test name
Test status
Simulation time 76510667 ps
CPU time 0.71 seconds
Started Jul 31 05:48:14 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 203684 kb
Host smart-b84651c5-1618-43cf-a17b-9bf801203e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724551173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1724551173
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.960495706
Short name T1026
Test name
Test status
Simulation time 43944586 ps
CPU time 0.78 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 203976 kb
Host smart-76e891a5-9947-4428-a52e-981019c0d916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960495706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.960495706
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3730406434
Short name T1025
Test name
Test status
Simulation time 56470691 ps
CPU time 0.78 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 203628 kb
Host smart-f00abe9b-7d9f-4e96-9fde-1bffd1b0cf28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730406434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3730406434
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.698784119
Short name T1034
Test name
Test status
Simulation time 52713842 ps
CPU time 0.74 seconds
Started Jul 31 05:48:16 PM PDT 24
Finished Jul 31 05:48:17 PM PDT 24
Peak memory 203684 kb
Host smart-06214261-08ec-49f8-bd23-813dce13c4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698784119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.698784119
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.510623224
Short name T1050
Test name
Test status
Simulation time 694288098 ps
CPU time 7.58 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 207028 kb
Host smart-4c2e2238-94ef-4489-8241-12ff3b74ed35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510623224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.510623224
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2481130769
Short name T1084
Test name
Test status
Simulation time 1239505793 ps
CPU time 12.11 seconds
Started Jul 31 05:47:56 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 206988 kb
Host smart-254c53e4-154b-4ab7-afd6-b2286c090e34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481130769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2481130769
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2829114413
Short name T87
Test name
Test status
Simulation time 51390235 ps
CPU time 1.47 seconds
Started Jul 31 05:47:53 PM PDT 24
Finished Jul 31 05:47:55 PM PDT 24
Peak memory 215148 kb
Host smart-ce8f0f14-9e8d-41bd-80da-b49e5ff3098c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829114413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2829114413
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3645218713
Short name T1074
Test name
Test status
Simulation time 508627153 ps
CPU time 3.54 seconds
Started Jul 31 05:48:02 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 217636 kb
Host smart-fc6a9691-0ac2-475a-8774-fd670274b6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645218713 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3645218713
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3621881983
Short name T1042
Test name
Test status
Simulation time 20992795 ps
CPU time 1.31 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:47:55 PM PDT 24
Peak memory 215272 kb
Host smart-4c26ebce-9d33-4e3e-b7bc-46b39a5d047c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621881983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
621881983
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.950969502
Short name T1112
Test name
Test status
Simulation time 37793265 ps
CPU time 0.74 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 203964 kb
Host smart-5d22749b-76f1-416f-a118-6927f5aaf31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950969502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.950969502
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1387230118
Short name T120
Test name
Test status
Simulation time 38972616 ps
CPU time 1.34 seconds
Started Jul 31 05:47:52 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 215064 kb
Host smart-30e92caf-8afd-41a5-84d4-7c0b5c748393
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387230118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1387230118
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.365525052
Short name T1012
Test name
Test status
Simulation time 35124328 ps
CPU time 0.66 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 203620 kb
Host smart-b9c02a64-35a6-4e48-9334-7ee09884882f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365525052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.365525052
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3502285484
Short name T1088
Test name
Test status
Simulation time 144136023 ps
CPU time 2.53 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 215236 kb
Host smart-b53c465b-480c-469c-a10b-563a21cceb85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502285484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3502285484
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1114147294
Short name T111
Test name
Test status
Simulation time 28613818 ps
CPU time 1.75 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 216456 kb
Host smart-cfdb0212-dd4a-44d7-b496-84f7ec9ab064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114147294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
114147294
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3170762991
Short name T1104
Test name
Test status
Simulation time 105174707 ps
CPU time 6.91 seconds
Started Jul 31 05:47:50 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 215196 kb
Host smart-f5941b9e-ae7a-4adf-a9fc-92c7a30e501d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170762991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3170762991
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3706895079
Short name T1063
Test name
Test status
Simulation time 110649521 ps
CPU time 0.75 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 203996 kb
Host smart-f330b540-33bf-46dc-ab57-0ab8021e9a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706895079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3706895079
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3781351992
Short name T1124
Test name
Test status
Simulation time 32006612 ps
CPU time 0.75 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203648 kb
Host smart-fe812e3a-1e91-4e9e-ac05-81112a33a78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781351992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3781351992
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.929424437
Short name T1127
Test name
Test status
Simulation time 20060643 ps
CPU time 0.7 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 204000 kb
Host smart-cfb34040-812d-42e0-a31a-39a065fd216d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929424437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.929424437
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2664303805
Short name T1130
Test name
Test status
Simulation time 50314414 ps
CPU time 0.81 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 203644 kb
Host smart-d42c9a3f-49f7-47f9-8924-f16a38c9d7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664303805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2664303805
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2222480182
Short name T1013
Test name
Test status
Simulation time 19741710 ps
CPU time 0.76 seconds
Started Jul 31 05:48:09 PM PDT 24
Finished Jul 31 05:48:10 PM PDT 24
Peak memory 203684 kb
Host smart-e0d1b5fe-0b26-4a00-8b61-21d86c21e6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222480182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2222480182
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1734753171
Short name T1083
Test name
Test status
Simulation time 19966926 ps
CPU time 0.76 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203944 kb
Host smart-8e502737-4f30-42b0-bb0f-c0bdf70aa8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734753171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1734753171
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.36127920
Short name T1116
Test name
Test status
Simulation time 47363839 ps
CPU time 0.74 seconds
Started Jul 31 05:48:16 PM PDT 24
Finished Jul 31 05:48:17 PM PDT 24
Peak memory 203980 kb
Host smart-46a037a5-1a23-4d95-9fad-4dce40411f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.36127920
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1949133623
Short name T1039
Test name
Test status
Simulation time 14266305 ps
CPU time 0.74 seconds
Started Jul 31 05:48:12 PM PDT 24
Finished Jul 31 05:48:13 PM PDT 24
Peak memory 203680 kb
Host smart-9641917d-7538-48ad-bf22-50a9fad83c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949133623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1949133623
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1802752144
Short name T1123
Test name
Test status
Simulation time 11579553 ps
CPU time 0.75 seconds
Started Jul 31 05:48:13 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 203988 kb
Host smart-275b8b06-06d0-4e46-bced-b8e2c3a41f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802752144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1802752144
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1798409513
Short name T1122
Test name
Test status
Simulation time 44540223 ps
CPU time 0.77 seconds
Started Jul 31 05:48:08 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 203668 kb
Host smart-a018262c-5e83-43b9-acb6-61f0b2fed46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798409513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1798409513
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4187883945
Short name T1131
Test name
Test status
Simulation time 377654939 ps
CPU time 2.85 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 216232 kb
Host smart-3993f1d4-acc9-400b-822a-2e1e2f38e6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187883945 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4187883945
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3113080615
Short name T118
Test name
Test status
Simulation time 231473459 ps
CPU time 1.91 seconds
Started Jul 31 05:48:10 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215132 kb
Host smart-cb9c7d27-c071-41f1-bb15-2aebaa817589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113080615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
113080615
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2607941298
Short name T1009
Test name
Test status
Simulation time 53939533 ps
CPU time 0.7 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 203684 kb
Host smart-96f7b88b-52c7-4f87-823f-092c011fac05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607941298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
607941298
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1649068444
Short name T1120
Test name
Test status
Simulation time 61859135 ps
CPU time 3.83 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:07 PM PDT 24
Peak memory 215132 kb
Host smart-b325a4f5-610d-4a72-a45d-7d245d0e62be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649068444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1649068444
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.623056633
Short name T107
Test name
Test status
Simulation time 73730654 ps
CPU time 1.92 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 215384 kb
Host smart-48aaac67-f1d8-40e5-805c-ad168dd9b419
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623056633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.623056633
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3713303629
Short name T167
Test name
Test status
Simulation time 3995746159 ps
CPU time 18.85 seconds
Started Jul 31 05:48:11 PM PDT 24
Finished Jul 31 05:48:30 PM PDT 24
Peak memory 215264 kb
Host smart-14727e00-b3b4-4200-852e-31db064fa4d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713303629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3713303629
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.546599801
Short name T1090
Test name
Test status
Simulation time 1057553794 ps
CPU time 3.83 seconds
Started Jul 31 05:47:55 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 217152 kb
Host smart-303b726d-13d1-4da8-8ecd-3d920ebd9043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546599801 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.546599801
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.694784719
Short name T123
Test name
Test status
Simulation time 98474231 ps
CPU time 2.4 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 215144 kb
Host smart-365871e0-aa82-4487-a384-1c9360e4b760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694784719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.694784719
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.947585284
Short name T1066
Test name
Test status
Simulation time 12887617 ps
CPU time 0.78 seconds
Started Jul 31 05:48:00 PM PDT 24
Finished Jul 31 05:48:01 PM PDT 24
Peak memory 203928 kb
Host smart-e16c6f7b-e4d1-4c87-bd37-6e1d96e35984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947585284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.947585284
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4109029855
Short name T1060
Test name
Test status
Simulation time 422645993 ps
CPU time 3.82 seconds
Started Jul 31 05:48:00 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 215232 kb
Host smart-47975d61-5699-4c9c-960b-0be163dcabc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109029855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4109029855
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2522047262
Short name T1118
Test name
Test status
Simulation time 1247114178 ps
CPU time 4.17 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 215244 kb
Host smart-70d23a89-4310-4999-9330-6d6ae79eb050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522047262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
522047262
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3632010955
Short name T166
Test name
Test status
Simulation time 299926746 ps
CPU time 19.44 seconds
Started Jul 31 05:47:55 PM PDT 24
Finished Jul 31 05:48:14 PM PDT 24
Peak memory 215240 kb
Host smart-20af87ee-2920-4bff-82ac-deab2e94716f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632010955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3632010955
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.548229273
Short name T113
Test name
Test status
Simulation time 86052277 ps
CPU time 1.73 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 216272 kb
Host smart-b3ac9cbf-4b2d-4361-8aaa-1e5e606b5d0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548229273 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.548229273
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1256721934
Short name T155
Test name
Test status
Simulation time 275113508 ps
CPU time 2 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 215120 kb
Host smart-73b74dec-0c69-43e4-ac0d-d492cc960f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256721934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
256721934
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3047217940
Short name T1111
Test name
Test status
Simulation time 49511111 ps
CPU time 0.76 seconds
Started Jul 31 05:47:59 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 203968 kb
Host smart-077edb78-1bfc-45ae-b0e2-e1c13282acc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047217940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
047217940
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1933871034
Short name T153
Test name
Test status
Simulation time 142356973 ps
CPU time 3.15 seconds
Started Jul 31 05:48:13 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 215164 kb
Host smart-45d27bcd-cf18-4f97-8ce0-d6818e36721c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933871034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1933871034
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1655409430
Short name T104
Test name
Test status
Simulation time 92149077 ps
CPU time 5.44 seconds
Started Jul 31 05:47:56 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 215316 kb
Host smart-de091c97-1958-4210-8d4f-8be79d646af4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655409430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
655409430
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2647874907
Short name T75
Test name
Test status
Simulation time 158424384 ps
CPU time 2.88 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 216660 kb
Host smart-c0e5644d-ef7b-49ff-a146-c0b24097af07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647874907 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2647874907
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2492292497
Short name T1070
Test name
Test status
Simulation time 43226111 ps
CPU time 1.99 seconds
Started Jul 31 05:47:56 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 215164 kb
Host smart-f8a55c8d-cc03-4afd-a86a-d2345b64c118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492292497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
492292497
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3403745399
Short name T1011
Test name
Test status
Simulation time 18180356 ps
CPU time 0.77 seconds
Started Jul 31 05:48:01 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 203612 kb
Host smart-07c83796-a937-46d2-9366-dcf4cb91e8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403745399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
403745399
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2286118044
Short name T1014
Test name
Test status
Simulation time 29033585 ps
CPU time 1.75 seconds
Started Jul 31 05:48:03 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 215128 kb
Host smart-4fb0b9ca-2fe6-4615-bb18-8ef289f24065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286118044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2286118044
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2158553924
Short name T103
Test name
Test status
Simulation time 275322307 ps
CPU time 4.7 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:48:02 PM PDT 24
Peak memory 215328 kb
Host smart-e9f29b7d-b751-4a0b-8f16-f10ff317fe3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158553924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
158553924
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.172369740
Short name T1079
Test name
Test status
Simulation time 661257560 ps
CPU time 13.2 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 215200 kb
Host smart-8b108482-5572-4e96-99ed-5ca89b1be570
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172369740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.172369740
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1546089533
Short name T1117
Test name
Test status
Simulation time 129678720 ps
CPU time 3.65 seconds
Started Jul 31 05:47:53 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 216728 kb
Host smart-9ffcadc9-e5b1-4ba5-98c3-0dc6f7e96926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546089533 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1546089533
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3627527790
Short name T122
Test name
Test status
Simulation time 42450803 ps
CPU time 1.34 seconds
Started Jul 31 05:47:57 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 206912 kb
Host smart-6a106350-6dd9-4e83-8ae5-c8483c6bbeac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627527790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
627527790
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1136647201
Short name T1107
Test name
Test status
Simulation time 18367428 ps
CPU time 0.76 seconds
Started Jul 31 05:47:58 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 204008 kb
Host smart-3eab03e5-cee9-4466-a8cc-28f95a85bed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136647201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
136647201
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2235169021
Short name T1099
Test name
Test status
Simulation time 187302289 ps
CPU time 1.96 seconds
Started Jul 31 05:47:54 PM PDT 24
Finished Jul 31 05:47:56 PM PDT 24
Peak memory 215240 kb
Host smart-981237dc-6c1e-402b-8971-dabd432181da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235169021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2235169021
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.619187599
Short name T106
Test name
Test status
Simulation time 241795192 ps
CPU time 3.59 seconds
Started Jul 31 05:48:06 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215356 kb
Host smart-7217d77a-2466-4a5f-8a6a-7c31078bf0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619187599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.619187599
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.550841821
Short name T783
Test name
Test status
Simulation time 171039381 ps
CPU time 0.76 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:34:57 PM PDT 24
Peak memory 205680 kb
Host smart-03582af5-5966-4bd1-8568-278303cf36dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550841821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.550841821
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3526069832
Short name T432
Test name
Test status
Simulation time 619603429 ps
CPU time 8.72 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:35:06 PM PDT 24
Peak memory 233084 kb
Host smart-c85c0de3-b2ca-4c45-9020-da8a97c17458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526069832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3526069832
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4001423286
Short name T942
Test name
Test status
Simulation time 162929372 ps
CPU time 0.81 seconds
Started Jul 31 07:34:50 PM PDT 24
Finished Jul 31 07:34:51 PM PDT 24
Peak memory 207000 kb
Host smart-ab00ef63-10c1-44b7-8abb-26053d673f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001423286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4001423286
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.828860935
Short name T218
Test name
Test status
Simulation time 4324822599 ps
CPU time 28.28 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:35:25 PM PDT 24
Peak memory 253888 kb
Host smart-6a3a323e-b068-4c1f-b2ef-a44871d48540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828860935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.828860935
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.707130033
Short name T202
Test name
Test status
Simulation time 87101155862 ps
CPU time 448.33 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:42:25 PM PDT 24
Peak memory 266040 kb
Host smart-648b37f3-ec76-4b17-a3df-33cec6832e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707130033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.707130033
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2093016168
Short name T213
Test name
Test status
Simulation time 2068475198 ps
CPU time 40.48 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 257764 kb
Host smart-1fa63319-6ba3-438d-a276-00133216f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093016168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2093016168
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1781307992
Short name T293
Test name
Test status
Simulation time 6693931031 ps
CPU time 27.48 seconds
Started Jul 31 07:34:55 PM PDT 24
Finished Jul 31 07:35:22 PM PDT 24
Peak memory 238824 kb
Host smart-54ad8435-2038-48fa-88b8-85680f5dcca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781307992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1781307992
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1615127277
Short name T39
Test name
Test status
Simulation time 43921958266 ps
CPU time 324.69 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:40:22 PM PDT 24
Peak memory 254324 kb
Host smart-43fb490b-0704-4cb7-8fa5-704adb37f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615127277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1615127277
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.719090543
Short name T502
Test name
Test status
Simulation time 578064880 ps
CPU time 7.27 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:35:04 PM PDT 24
Peak memory 224924 kb
Host smart-0cd082bd-9169-49e4-adfc-2f58afd67692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719090543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.719090543
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2031196570
Short name T13
Test name
Test status
Simulation time 3177515232 ps
CPU time 32.03 seconds
Started Jul 31 07:34:59 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 225012 kb
Host smart-e0868a64-7b72-4dcf-9328-242fe6845eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031196570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2031196570
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4249082037
Short name T461
Test name
Test status
Simulation time 569046323 ps
CPU time 5.23 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:02 PM PDT 24
Peak memory 224968 kb
Host smart-9749975c-2242-4e7c-8650-52e795203284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249082037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4249082037
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1073030746
Short name T938
Test name
Test status
Simulation time 11055329960 ps
CPU time 29.98 seconds
Started Jul 31 07:34:55 PM PDT 24
Finished Jul 31 07:35:25 PM PDT 24
Peak memory 233080 kb
Host smart-3ba70ffa-dae9-44c3-9baf-7d9ad8dd7e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073030746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1073030746
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2792053488
Short name T899
Test name
Test status
Simulation time 1634225670 ps
CPU time 7.27 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:04 PM PDT 24
Peak memory 223600 kb
Host smart-b734a897-96f0-4ed2-8130-43d2081231cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2792053488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2792053488
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1827115425
Short name T79
Test name
Test status
Simulation time 301796976 ps
CPU time 0.98 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:34:59 PM PDT 24
Peak memory 236272 kb
Host smart-b3fce23d-1b8f-4ae1-b273-ace4f981b351
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827115425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1827115425
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.23340603
Short name T509
Test name
Test status
Simulation time 56001085 ps
CPU time 1.08 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:35:00 PM PDT 24
Peak memory 207468 kb
Host smart-6f8e8a06-4190-4b59-80c4-e1197e9622fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23340603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_
all.23340603
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1391961487
Short name T884
Test name
Test status
Simulation time 11837928959 ps
CPU time 37.96 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 220444 kb
Host smart-3b1f8464-3057-4319-847e-a96bd7ea9f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391961487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1391961487
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1001387766
Short name T803
Test name
Test status
Simulation time 4614975781 ps
CPU time 3.27 seconds
Started Jul 31 07:34:50 PM PDT 24
Finished Jul 31 07:34:54 PM PDT 24
Peak memory 216672 kb
Host smart-cbb00359-8517-4a1b-9a10-6cfd780c857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001387766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1001387766
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3736392564
Short name T555
Test name
Test status
Simulation time 64186293 ps
CPU time 0.83 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:34:58 PM PDT 24
Peak memory 207388 kb
Host smart-fd5a00b0-742a-4d7e-9431-ad1e6e041f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736392564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3736392564
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2901606707
Short name T908
Test name
Test status
Simulation time 16651764 ps
CPU time 0.75 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:34:56 PM PDT 24
Peak memory 206308 kb
Host smart-9c200a1c-9610-47fc-9dc1-18ddd03d8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901606707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2901606707
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3869389774
Short name T834
Test name
Test status
Simulation time 26221613660 ps
CPU time 23.32 seconds
Started Jul 31 07:34:55 PM PDT 24
Finished Jul 31 07:35:19 PM PDT 24
Peak memory 233108 kb
Host smart-6051c72d-dc22-4321-b4d1-0c65a82b6ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869389774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3869389774
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2106954085
Short name T652
Test name
Test status
Simulation time 1075037611 ps
CPU time 12.54 seconds
Started Jul 31 07:34:59 PM PDT 24
Finished Jul 31 07:35:12 PM PDT 24
Peak memory 233000 kb
Host smart-794bd02f-97ce-4c20-a209-aee3d1647c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106954085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2106954085
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4145468811
Short name T513
Test name
Test status
Simulation time 28626153 ps
CPU time 0.79 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:34:59 PM PDT 24
Peak memory 205916 kb
Host smart-bc01c602-070c-4c10-9b7e-b0d3e0195857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145468811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4145468811
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1570405332
Short name T48
Test name
Test status
Simulation time 10087389167 ps
CPU time 68.05 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:36:04 PM PDT 24
Peak memory 254264 kb
Host smart-f0fa1de4-aa4c-4380-b964-ac655ccee61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570405332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1570405332
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3723529970
Short name T625
Test name
Test status
Simulation time 7375997311 ps
CPU time 62.42 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:35:58 PM PDT 24
Peak memory 250368 kb
Host smart-892661d8-a89a-4db5-a8c6-ddb4e756f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723529970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3723529970
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3672127899
Short name T798
Test name
Test status
Simulation time 17024005776 ps
CPU time 152.76 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 249660 kb
Host smart-e0071f23-be98-44e1-9072-77dffe446f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672127899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3672127899
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4040963922
Short name T5
Test name
Test status
Simulation time 80553006 ps
CPU time 2.81 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:35:01 PM PDT 24
Peak memory 233092 kb
Host smart-5851c94a-d1c1-4320-acda-274eb23848a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040963922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4040963922
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2506206060
Short name T951
Test name
Test status
Simulation time 30351055453 ps
CPU time 190.96 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:38:08 PM PDT 24
Peak memory 252924 kb
Host smart-952be0cc-229f-4bc6-8b82-d40f5fbde1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506206060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2506206060
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.328208242
Short name T642
Test name
Test status
Simulation time 219934593 ps
CPU time 4.24 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:35:00 PM PDT 24
Peak memory 224952 kb
Host smart-eb579f7c-18a8-4e7f-bc81-22e6a6c33c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328208242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.328208242
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2707802583
Short name T607
Test name
Test status
Simulation time 357811852 ps
CPU time 6.9 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:04 PM PDT 24
Peak memory 233064 kb
Host smart-ac22652a-9d8d-43a8-9ae1-10d310f1d93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707802583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2707802583
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2167185862
Short name T914
Test name
Test status
Simulation time 7015236694 ps
CPU time 7.22 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:04 PM PDT 24
Peak memory 233200 kb
Host smart-78f747c9-4bd0-4555-985b-8df3d86a44d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167185862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2167185862
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2719761052
Short name T863
Test name
Test status
Simulation time 897193601 ps
CPU time 3.1 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:34:59 PM PDT 24
Peak memory 224844 kb
Host smart-10fb9d11-913e-4bd1-894c-9e57b96ab586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719761052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2719761052
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3903319079
Short name T854
Test name
Test status
Simulation time 410947062 ps
CPU time 5.25 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:35:03 PM PDT 24
Peak memory 219620 kb
Host smart-38b3a1f0-3bbc-4e35-a395-365fee3070a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903319079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3903319079
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1093280086
Short name T277
Test name
Test status
Simulation time 39862855149 ps
CPU time 281.59 seconds
Started Jul 31 07:34:58 PM PDT 24
Finished Jul 31 07:39:39 PM PDT 24
Peak memory 255884 kb
Host smart-7419a8d4-fe85-441a-bf94-059defa04788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093280086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1093280086
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3490070973
Short name T762
Test name
Test status
Simulation time 1278806157 ps
CPU time 8.33 seconds
Started Jul 31 07:34:59 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 216864 kb
Host smart-e508dfc7-633a-431a-a8e6-11a1cc59de7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490070973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3490070973
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2168047693
Short name T537
Test name
Test status
Simulation time 6974143925 ps
CPU time 6.26 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:35:03 PM PDT 24
Peak memory 216740 kb
Host smart-0e0fce06-2059-4876-924c-8090378d7cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168047693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2168047693
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4049990138
Short name T659
Test name
Test status
Simulation time 38837771 ps
CPU time 1.07 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:34:58 PM PDT 24
Peak memory 207988 kb
Host smart-aeecd450-77b7-4b7f-9e8f-5bdff535c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049990138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4049990138
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2457478990
Short name T463
Test name
Test status
Simulation time 74864606 ps
CPU time 0.84 seconds
Started Jul 31 07:34:57 PM PDT 24
Finished Jul 31 07:34:58 PM PDT 24
Peak memory 206348 kb
Host smart-df14f923-91ed-4207-be2a-5f2680382401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457478990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2457478990
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1832779081
Short name T225
Test name
Test status
Simulation time 19927108178 ps
CPU time 16.66 seconds
Started Jul 31 07:34:56 PM PDT 24
Finished Jul 31 07:35:12 PM PDT 24
Peak memory 233116 kb
Host smart-691c8be6-ccf1-457f-ac9f-8b80ff32b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832779081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1832779081
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3578834717
Short name T871
Test name
Test status
Simulation time 12245357 ps
CPU time 0.74 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 205304 kb
Host smart-640f8478-4c38-4cd4-ac8e-c6ba56dda67a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578834717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3578834717
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2845430665
Short name T757
Test name
Test status
Simulation time 122615010 ps
CPU time 2.5 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:35:35 PM PDT 24
Peak memory 224924 kb
Host smart-1f1b3739-a03d-4bc1-a03c-43e86ab55dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845430665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2845430665
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3885655081
Short name T497
Test name
Test status
Simulation time 14989695 ps
CPU time 0.72 seconds
Started Jul 31 07:35:28 PM PDT 24
Finished Jul 31 07:35:28 PM PDT 24
Peak memory 205916 kb
Host smart-710e9f48-fed7-4bc3-9bd6-8cddbf3bb1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885655081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3885655081
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.450341112
Short name T707
Test name
Test status
Simulation time 3919100429 ps
CPU time 28.58 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:36:06 PM PDT 24
Peak memory 235272 kb
Host smart-9098717c-2a25-49d8-a8e5-cf60e1ceea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450341112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.450341112
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2324701371
Short name T286
Test name
Test status
Simulation time 17628902317 ps
CPU time 112.1 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 239084 kb
Host smart-a4d7da2b-63c5-45ca-874a-3f8b3b0bd3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324701371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2324701371
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1432860906
Short name T955
Test name
Test status
Simulation time 791338599 ps
CPU time 6.01 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 233096 kb
Host smart-f49cfc56-a38a-4dd8-ae9d-e85575a4684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432860906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1432860906
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1645198675
Short name T688
Test name
Test status
Simulation time 2669845383 ps
CPU time 11.79 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:42 PM PDT 24
Peak memory 224972 kb
Host smart-14d7a06f-0cdd-4009-849d-1b5398990c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645198675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1645198675
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.337546950
Short name T722
Test name
Test status
Simulation time 4471096813 ps
CPU time 13.91 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:44 PM PDT 24
Peak memory 240780 kb
Host smart-ca251204-ed50-4ad2-b3cf-8dc70971fadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337546950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.337546950
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1598718360
Short name T575
Test name
Test status
Simulation time 19766247022 ps
CPU time 16.75 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:46 PM PDT 24
Peak memory 233200 kb
Host smart-7b9f061a-92a2-4ca5-8d65-b6d76fcfb0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598718360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1598718360
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3678824297
Short name T990
Test name
Test status
Simulation time 36200383 ps
CPU time 2.15 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:34 PM PDT 24
Peak memory 232740 kb
Host smart-deded026-305c-4b4f-90a1-653a29de3b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678824297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3678824297
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3946069074
Short name T349
Test name
Test status
Simulation time 1220386766 ps
CPU time 14.29 seconds
Started Jul 31 07:35:38 PM PDT 24
Finished Jul 31 07:35:52 PM PDT 24
Peak memory 222680 kb
Host smart-90aa2ad7-90fc-45c1-a28a-828d3fb9fd65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946069074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3946069074
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.413336926
Short name T528
Test name
Test status
Simulation time 9036849684 ps
CPU time 29.5 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:36:02 PM PDT 24
Peak memory 216824 kb
Host smart-606a9a21-11d1-4749-88f4-b25d60968863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413336926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.413336926
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3086105914
Short name T686
Test name
Test status
Simulation time 924597012 ps
CPU time 7.26 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 216568 kb
Host smart-b72d752e-d415-4d71-a4e6-d9514aae44cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086105914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3086105914
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.996159990
Short name T54
Test name
Test status
Simulation time 187489482 ps
CPU time 1.17 seconds
Started Jul 31 07:35:33 PM PDT 24
Finished Jul 31 07:35:34 PM PDT 24
Peak memory 216684 kb
Host smart-bfa05f75-0ba9-4bb3-bc51-92a3747d8e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996159990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.996159990
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.785839557
Short name T697
Test name
Test status
Simulation time 42338822 ps
CPU time 0.76 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:30 PM PDT 24
Peak memory 206360 kb
Host smart-fc674ee8-4141-4a5e-98f6-069603634660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785839557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.785839557
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1040040110
Short name T248
Test name
Test status
Simulation time 313355022 ps
CPU time 3.57 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 224896 kb
Host smart-08209cb4-3c94-4a7a-95f5-146aea36eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040040110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1040040110
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.122962550
Short name T487
Test name
Test status
Simulation time 107808757 ps
CPU time 0.72 seconds
Started Jul 31 07:35:36 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 205840 kb
Host smart-a9aed669-b9ca-46e0-97ef-6b14ec5837eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122962550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.122962550
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4112842522
Short name T749
Test name
Test status
Simulation time 1636342695 ps
CPU time 15.93 seconds
Started Jul 31 07:35:36 PM PDT 24
Finished Jul 31 07:35:52 PM PDT 24
Peak memory 233068 kb
Host smart-b9b196dd-aa17-4e44-8990-883add015d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112842522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4112842522
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2190406975
Short name T327
Test name
Test status
Simulation time 55021240 ps
CPU time 0.82 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 206936 kb
Host smart-c9030cf9-59ae-4ccc-beb5-5bb7a9fd8173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190406975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2190406975
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.329330178
Short name T810
Test name
Test status
Simulation time 46342550224 ps
CPU time 172.98 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 252148 kb
Host smart-418bac88-4d0d-4efe-bcfb-3df6be5d6a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329330178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.329330178
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4264973528
Short name T669
Test name
Test status
Simulation time 15830327946 ps
CPU time 143.25 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 249216 kb
Host smart-a21d3fdb-e6de-4cf8-b996-eb1b9ed03600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264973528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4264973528
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3357382319
Short name T665
Test name
Test status
Simulation time 3312429757 ps
CPU time 69.45 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:36:49 PM PDT 24
Peak memory 249632 kb
Host smart-c89acdbc-82f1-49e3-84b3-df17e64c234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357382319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3357382319
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1012339490
Short name T848
Test name
Test status
Simulation time 1602928253 ps
CPU time 15.85 seconds
Started Jul 31 07:35:35 PM PDT 24
Finished Jul 31 07:35:51 PM PDT 24
Peak memory 233036 kb
Host smart-45df6171-754b-4b9f-a1ee-b5e606f1f6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012339490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1012339490
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.831187297
Short name T568
Test name
Test status
Simulation time 316868251515 ps
CPU time 414.06 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:42:31 PM PDT 24
Peak memory 264700 kb
Host smart-27e08cd5-4b90-402e-bf81-855eae7ae5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831187297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.831187297
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3097986693
Short name T368
Test name
Test status
Simulation time 230797333 ps
CPU time 3.75 seconds
Started Jul 31 07:35:36 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 233112 kb
Host smart-0d787238-eb38-490c-ad5b-539df815d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097986693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3097986693
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3550518408
Short name T851
Test name
Test status
Simulation time 1748853687 ps
CPU time 6.7 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:35:47 PM PDT 24
Peak memory 233124 kb
Host smart-a103eaab-2809-4408-9d0b-ebf68ccde55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550518408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3550518408
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3529961453
Short name T69
Test name
Test status
Simulation time 2527691711 ps
CPU time 12.85 seconds
Started Jul 31 07:35:38 PM PDT 24
Finished Jul 31 07:35:51 PM PDT 24
Peak memory 233188 kb
Host smart-abfac2a0-46ef-4e6e-9584-e0de3c6ad024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529961453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3529961453
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3446631504
Short name T410
Test name
Test status
Simulation time 2139233656 ps
CPU time 5.12 seconds
Started Jul 31 07:35:38 PM PDT 24
Finished Jul 31 07:35:43 PM PDT 24
Peak memory 233168 kb
Host smart-e1e9488b-e5d2-4f9b-9562-3fd44d82d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446631504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3446631504
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3167607360
Short name T396
Test name
Test status
Simulation time 1610109187 ps
CPU time 16.76 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:35:57 PM PDT 24
Peak memory 219232 kb
Host smart-d846651c-266d-49e6-b56f-9591f18b8de1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3167607360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3167607360
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4291970978
Short name T941
Test name
Test status
Simulation time 160371983647 ps
CPU time 176.74 seconds
Started Jul 31 07:35:38 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 281496 kb
Host smart-900dc128-00d9-4eab-9349-de747cec70b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291970978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4291970978
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1681352535
Short name T987
Test name
Test status
Simulation time 981500816 ps
CPU time 9.19 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:35:46 PM PDT 24
Peak memory 216748 kb
Host smart-a1353c57-9d48-438a-8346-a820fafefbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681352535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1681352535
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3627338065
Short name T958
Test name
Test status
Simulation time 102347421 ps
CPU time 1.15 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:35:41 PM PDT 24
Peak memory 208236 kb
Host smart-b49439db-3aa3-4cd5-9ae9-f306f60ec2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627338065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3627338065
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.575992653
Short name T520
Test name
Test status
Simulation time 83088739 ps
CPU time 1.39 seconds
Started Jul 31 07:35:41 PM PDT 24
Finished Jul 31 07:35:42 PM PDT 24
Peak memory 216644 kb
Host smart-ff4777a8-4d8d-48be-8ff8-e6efe35ffeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575992653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.575992653
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.290469936
Short name T341
Test name
Test status
Simulation time 42521551 ps
CPU time 0.82 seconds
Started Jul 31 07:35:39 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 206308 kb
Host smart-29a5c4ef-1a8b-4db0-9364-e24c708f979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290469936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.290469936
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4039260507
Short name T735
Test name
Test status
Simulation time 1034554952 ps
CPU time 8.19 seconds
Started Jul 31 07:35:39 PM PDT 24
Finished Jul 31 07:35:47 PM PDT 24
Peak memory 238068 kb
Host smart-f032808b-2135-4f0d-850a-3cddcd4011f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039260507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4039260507
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2950860106
Short name T378
Test name
Test status
Simulation time 21701683 ps
CPU time 0.72 seconds
Started Jul 31 07:35:50 PM PDT 24
Finished Jul 31 07:35:51 PM PDT 24
Peak memory 205244 kb
Host smart-60214ee4-6ce3-41e6-bd09-3b5de36f3da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950860106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2950860106
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1711467658
Short name T646
Test name
Test status
Simulation time 510973014 ps
CPU time 2.87 seconds
Started Jul 31 07:35:49 PM PDT 24
Finished Jul 31 07:35:52 PM PDT 24
Peak memory 225012 kb
Host smart-348e5273-931c-4af4-812a-f483fdb07c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711467658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1711467658
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1062481175
Short name T698
Test name
Test status
Simulation time 15831967 ps
CPU time 0.73 seconds
Started Jul 31 07:35:37 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 205936 kb
Host smart-32359249-b00c-4012-83bb-edcf9422a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062481175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1062481175
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2505233484
Short name T920
Test name
Test status
Simulation time 510306171 ps
CPU time 5.46 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:53 PM PDT 24
Peak memory 249560 kb
Host smart-23aca8a4-d98f-4a7d-aac0-c759a80dd99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505233484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2505233484
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3855329810
Short name T90
Test name
Test status
Simulation time 8631956252 ps
CPU time 26.63 seconds
Started Jul 31 07:35:49 PM PDT 24
Finished Jul 31 07:36:15 PM PDT 24
Peak memory 218116 kb
Host smart-287140a1-a82b-47d7-9872-1a72f3e91797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855329810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3855329810
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.800888785
Short name T289
Test name
Test status
Simulation time 1930237350 ps
CPU time 14.52 seconds
Started Jul 31 07:35:46 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 233120 kb
Host smart-7f98ac8c-e83a-4c5f-bf84-c82abf1766fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800888785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.800888785
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1680735441
Short name T682
Test name
Test status
Simulation time 6877319904 ps
CPU time 92.08 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:37:20 PM PDT 24
Peak memory 256984 kb
Host smart-49130fe8-af67-4036-b8e0-0763cccb9a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680735441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1680735441
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3566455805
Short name T404
Test name
Test status
Simulation time 4567608853 ps
CPU time 10.94 seconds
Started Jul 31 07:35:48 PM PDT 24
Finished Jul 31 07:35:59 PM PDT 24
Peak memory 224940 kb
Host smart-c9f25397-55ed-49ae-94db-ee8641e8019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566455805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3566455805
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1635239127
Short name T405
Test name
Test status
Simulation time 4511240100 ps
CPU time 32.39 seconds
Started Jul 31 07:35:49 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 233280 kb
Host smart-34f992e4-6090-42da-95d2-5e53efc57811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635239127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1635239127
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.441371034
Short name T624
Test name
Test status
Simulation time 2061775369 ps
CPU time 7.55 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:55 PM PDT 24
Peak memory 240004 kb
Host smart-559ef6ba-438a-43a8-b8b4-1562943e5aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441371034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.441371034
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3594836476
Short name T257
Test name
Test status
Simulation time 228077080 ps
CPU time 2.29 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:49 PM PDT 24
Peak memory 224736 kb
Host smart-f9d2ec9c-954a-4c62-9bd8-ddad4df2d3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594836476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3594836476
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1707125274
Short name T718
Test name
Test status
Simulation time 4156616241 ps
CPU time 8.22 seconds
Started Jul 31 07:35:49 PM PDT 24
Finished Jul 31 07:35:57 PM PDT 24
Peak memory 221448 kb
Host smart-c1922b01-a46a-4e9d-9dfa-cc9a6c2e0b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1707125274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1707125274
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3580982019
Short name T760
Test name
Test status
Simulation time 69896847091 ps
CPU time 321.93 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:41:10 PM PDT 24
Peak memory 257336 kb
Host smart-d7f61f4f-0477-4bf8-b95d-490d782db747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580982019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3580982019
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2846549645
Short name T963
Test name
Test status
Simulation time 846564132 ps
CPU time 5.74 seconds
Started Jul 31 07:35:40 PM PDT 24
Finished Jul 31 07:35:46 PM PDT 24
Peak memory 216956 kb
Host smart-77c6f866-a8c7-4356-b123-24d586c62adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846549645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2846549645
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2158583515
Short name T986
Test name
Test status
Simulation time 3013002437 ps
CPU time 6.22 seconds
Started Jul 31 07:35:36 PM PDT 24
Finished Jul 31 07:35:42 PM PDT 24
Peak memory 216728 kb
Host smart-c04dae63-ebe0-46ca-8a10-7aa085ddb377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158583515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2158583515
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3955631338
Short name T853
Test name
Test status
Simulation time 22843756 ps
CPU time 1.35 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:49 PM PDT 24
Peak memory 216708 kb
Host smart-ac58187c-effc-4853-8e5c-6b1692b162fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955631338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3955631338
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2798245813
Short name T724
Test name
Test status
Simulation time 27838187 ps
CPU time 0.81 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:48 PM PDT 24
Peak memory 206340 kb
Host smart-3de9325c-25df-43a7-b748-9b12b1222bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798245813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2798245813
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2646619437
Short name T535
Test name
Test status
Simulation time 11207823167 ps
CPU time 16.25 seconds
Started Jul 31 07:35:53 PM PDT 24
Finished Jul 31 07:36:10 PM PDT 24
Peak memory 241160 kb
Host smart-653e82ca-0645-4c6b-bb06-7cc6a2e09141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646619437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2646619437
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2457802027
Short name T785
Test name
Test status
Simulation time 11628782 ps
CPU time 0.74 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 205788 kb
Host smart-7992a930-81cc-4963-bfe6-bbef0e00352c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457802027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2457802027
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1879715228
Short name T224
Test name
Test status
Simulation time 390817519 ps
CPU time 5.86 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:06 PM PDT 24
Peak memory 224932 kb
Host smart-97ea4094-b222-4983-8c24-b3782f52b42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879715228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1879715228
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1026556288
Short name T812
Test name
Test status
Simulation time 13030519 ps
CPU time 0.78 seconds
Started Jul 31 07:35:47 PM PDT 24
Finished Jul 31 07:35:48 PM PDT 24
Peak memory 206972 kb
Host smart-65799a8e-119e-4a59-86d4-3b429b2c8c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026556288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1026556288
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4037342143
Short name T478
Test name
Test status
Simulation time 47165080161 ps
CPU time 50.09 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 249900 kb
Host smart-ae688e1f-b09b-4609-967e-c0b52e8d1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037342143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4037342143
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4217222147
Short name T758
Test name
Test status
Simulation time 22638247 ps
CPU time 0.85 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:02 PM PDT 24
Peak memory 217316 kb
Host smart-e374c0fd-1521-4152-b529-c7f70e741b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217222147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4217222147
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3435253135
Short name T790
Test name
Test status
Simulation time 18109835766 ps
CPU time 118.34 seconds
Started Jul 31 07:36:11 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 249728 kb
Host smart-16331ea0-04e8-4787-8cff-3948b607bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435253135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3435253135
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3681790601
Short name T905
Test name
Test status
Simulation time 1122993991 ps
CPU time 10.57 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:11 PM PDT 24
Peak memory 233156 kb
Host smart-99545fcb-b593-4c22-a65a-b742759b80ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681790601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3681790601
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3401906510
Short name T793
Test name
Test status
Simulation time 22205702862 ps
CPU time 191.92 seconds
Started Jul 31 07:36:02 PM PDT 24
Finished Jul 31 07:39:14 PM PDT 24
Peak memory 257844 kb
Host smart-1fafa753-aa7b-434a-a571-5a017a6b123d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401906510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3401906510
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4099149448
Short name T717
Test name
Test status
Simulation time 8132629600 ps
CPU time 17.17 seconds
Started Jul 31 07:35:52 PM PDT 24
Finished Jul 31 07:36:09 PM PDT 24
Peak memory 224928 kb
Host smart-efb7e966-08c6-4ed5-8b36-d44876c0a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099149448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4099149448
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2367133487
Short name T570
Test name
Test status
Simulation time 37967138565 ps
CPU time 106.23 seconds
Started Jul 31 07:35:51 PM PDT 24
Finished Jul 31 07:37:37 PM PDT 24
Peak memory 225036 kb
Host smart-539dde1e-a9da-4bea-b295-e6498517118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367133487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2367133487
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3142550867
Short name T359
Test name
Test status
Simulation time 1775497515 ps
CPU time 5.79 seconds
Started Jul 31 07:35:50 PM PDT 24
Finished Jul 31 07:35:56 PM PDT 24
Peak memory 224912 kb
Host smart-4e55f174-b6ca-4fb6-be59-a4c4d7441426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142550867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3142550867
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2713483217
Short name T428
Test name
Test status
Simulation time 30806886 ps
CPU time 2.1 seconds
Started Jul 31 07:35:50 PM PDT 24
Finished Jul 31 07:35:52 PM PDT 24
Peak memory 224288 kb
Host smart-4a492161-8a6b-4ae0-be5c-285c7b3c089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713483217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2713483217
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3025681222
Short name T780
Test name
Test status
Simulation time 1100155388 ps
CPU time 10.32 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:09 PM PDT 24
Peak memory 222944 kb
Host smart-003d2053-942c-48aa-baeb-01e1a2e3fd57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3025681222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3025681222
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1283257141
Short name T58
Test name
Test status
Simulation time 237843143783 ps
CPU time 517.94 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:44:37 PM PDT 24
Peak memory 257716 kb
Host smart-835900bf-693e-43f0-b201-94e17b1df06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283257141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1283257141
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2050950925
Short name T898
Test name
Test status
Simulation time 9362377911 ps
CPU time 17.65 seconds
Started Jul 31 07:35:51 PM PDT 24
Finished Jul 31 07:36:09 PM PDT 24
Peak memory 216748 kb
Host smart-664f2ac6-411b-4b17-be4e-2cae7314fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050950925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2050950925
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4081012224
Short name T901
Test name
Test status
Simulation time 1653249926 ps
CPU time 6.12 seconds
Started Jul 31 07:35:51 PM PDT 24
Finished Jul 31 07:35:57 PM PDT 24
Peak memory 216680 kb
Host smart-5a5adab9-a888-468d-bd79-2c29258631ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081012224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4081012224
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1378923889
Short name T822
Test name
Test status
Simulation time 54874182 ps
CPU time 1.09 seconds
Started Jul 31 07:35:53 PM PDT 24
Finished Jul 31 07:35:55 PM PDT 24
Peak memory 216376 kb
Host smart-7b4127ad-67d8-4dea-8dfa-45d0d3941c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378923889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1378923889
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1768993512
Short name T392
Test name
Test status
Simulation time 941281535 ps
CPU time 0.89 seconds
Started Jul 31 07:35:50 PM PDT 24
Finished Jul 31 07:35:51 PM PDT 24
Peak memory 206472 kb
Host smart-55bc970e-2285-4c84-b92d-e2ed74f77e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768993512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1768993512
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3047210894
Short name T159
Test name
Test status
Simulation time 2537716663 ps
CPU time 7.48 seconds
Started Jul 31 07:35:51 PM PDT 24
Finished Jul 31 07:35:59 PM PDT 24
Peak memory 234136 kb
Host smart-201bbff5-c834-42ee-a19a-cb28fff03850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047210894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3047210894
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1728258856
Short name T627
Test name
Test status
Simulation time 42974338 ps
CPU time 0.69 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:00 PM PDT 24
Peak memory 205276 kb
Host smart-20a8a547-6091-449f-857d-b9acf8cc2f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728258856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1728258856
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.572873321
Short name T237
Test name
Test status
Simulation time 786299702 ps
CPU time 3.81 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:05 PM PDT 24
Peak memory 233000 kb
Host smart-1ea041ba-d400-4a1b-9f24-6e8730e0f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572873321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.572873321
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2712599384
Short name T763
Test name
Test status
Simulation time 18165790 ps
CPU time 0.78 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 205924 kb
Host smart-f3309be3-426f-49a3-9523-3a433d816ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712599384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2712599384
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1352401520
Short name T982
Test name
Test status
Simulation time 1496304684 ps
CPU time 38.24 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:38 PM PDT 24
Peak memory 249528 kb
Host smart-fa414b45-c453-4782-acac-509ad44c51a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352401520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1352401520
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3352678178
Short name T825
Test name
Test status
Simulation time 64722616605 ps
CPU time 130.58 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:38:11 PM PDT 24
Peak memory 249544 kb
Host smart-60fcb4fb-66a3-426d-8a87-0dc971c45535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352678178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3352678178
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.681557047
Short name T137
Test name
Test status
Simulation time 90419366182 ps
CPU time 186 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:39:07 PM PDT 24
Peak memory 249576 kb
Host smart-e48b77a0-8da3-40e6-b646-d17e15a57a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681557047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.681557047
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1800414609
Short name T287
Test name
Test status
Simulation time 2035856902 ps
CPU time 9.12 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:08 PM PDT 24
Peak memory 234924 kb
Host smart-0fb20ddf-d5e0-4e0a-866c-c429799741c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800414609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1800414609
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1962192322
Short name T683
Test name
Test status
Simulation time 12989711 ps
CPU time 0.75 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:00 PM PDT 24
Peak memory 216124 kb
Host smart-579fac64-9e12-4449-ae5d-8fd33d445256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962192322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1962192322
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2652111155
Short name T586
Test name
Test status
Simulation time 23859789750 ps
CPU time 34.25 seconds
Started Jul 31 07:36:02 PM PDT 24
Finished Jul 31 07:36:36 PM PDT 24
Peak memory 225080 kb
Host smart-475c3413-b62a-4adb-beea-44e03326e877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652111155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2652111155
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1844921165
Short name T421
Test name
Test status
Simulation time 9430863237 ps
CPU time 79.05 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 240152 kb
Host smart-28804455-2fb2-42e3-ae68-52db91fe57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844921165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1844921165
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3809244930
Short name T670
Test name
Test status
Simulation time 266611104 ps
CPU time 2.07 seconds
Started Jul 31 07:35:59 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 224316 kb
Host smart-a77cea7c-22bf-41cc-956e-c326257df5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809244930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3809244930
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4191314768
Short name T199
Test name
Test status
Simulation time 1002816026 ps
CPU time 4.95 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:05 PM PDT 24
Peak memory 233132 kb
Host smart-6b1e2374-698e-4360-8220-f347f3f65a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191314768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4191314768
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1524740709
Short name T433
Test name
Test status
Simulation time 291502502 ps
CPU time 4.64 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:05 PM PDT 24
Peak memory 223132 kb
Host smart-66eb8e36-4afa-4796-81f6-7a6804d2539b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1524740709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1524740709
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3929764847
Short name T809
Test name
Test status
Simulation time 191313327 ps
CPU time 0.95 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 207744 kb
Host smart-c125bf4a-277e-480e-8480-3032322a6d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929764847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3929764847
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2772849481
Short name T974
Test name
Test status
Simulation time 17292532194 ps
CPU time 36.26 seconds
Started Jul 31 07:36:03 PM PDT 24
Finished Jul 31 07:36:39 PM PDT 24
Peak memory 216888 kb
Host smart-ba4350f6-8794-401b-98bd-d45f1539679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772849481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2772849481
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1498639990
Short name T989
Test name
Test status
Simulation time 8814018816 ps
CPU time 20.72 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 216720 kb
Host smart-6836c3bf-ffc7-46b7-b8b6-4ac5eabb3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498639990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1498639990
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1057791344
Short name T356
Test name
Test status
Simulation time 40052836 ps
CPU time 0.77 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 206376 kb
Host smart-4adede44-802f-4e67-b70f-ada5b8b7e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057791344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1057791344
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.341617426
Short name T375
Test name
Test status
Simulation time 12878681 ps
CPU time 0.72 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:01 PM PDT 24
Peak memory 206000 kb
Host smart-10b6675e-5951-4857-a63a-862294c36dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341617426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.341617426
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.722118784
Short name T845
Test name
Test status
Simulation time 3727112383 ps
CPU time 11.58 seconds
Started Jul 31 07:36:03 PM PDT 24
Finished Jul 31 07:36:14 PM PDT 24
Peak memory 233156 kb
Host smart-e18a321c-3629-4a04-8b44-9fbc6a36632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722118784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.722118784
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.748266007
Short name T468
Test name
Test status
Simulation time 136211492 ps
CPU time 0.77 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:18 PM PDT 24
Peak memory 205196 kb
Host smart-7fb68036-462c-4717-a474-1356414f17c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748266007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.748266007
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4065936031
Short name T560
Test name
Test status
Simulation time 96236048 ps
CPU time 3.9 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 233068 kb
Host smart-800fb4cf-8952-4ce8-ae2c-a112248a2dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065936031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4065936031
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3297899769
Short name T11
Test name
Test status
Simulation time 18533636 ps
CPU time 0.87 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:02 PM PDT 24
Peak memory 206928 kb
Host smart-9b1a8cf2-7016-4103-a0a4-fbeb5c2924d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297899769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3297899769
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.894531097
Short name T450
Test name
Test status
Simulation time 3303087350 ps
CPU time 44.46 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:59 PM PDT 24
Peak memory 256660 kb
Host smart-55078bcf-ef30-443b-80ea-37ec474887c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894531097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.894531097
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4230725864
Short name T872
Test name
Test status
Simulation time 17819188714 ps
CPU time 204.43 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:39:39 PM PDT 24
Peak memory 254620 kb
Host smart-ac69b52b-63c1-4c6a-9b52-7af4cd93ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230725864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4230725864
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1356288414
Short name T699
Test name
Test status
Simulation time 8162735766 ps
CPU time 86.93 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 249644 kb
Host smart-10b2fbde-4976-4b15-87c1-297cbbd45256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356288414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1356288414
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3453278618
Short name T81
Test name
Test status
Simulation time 83741297 ps
CPU time 4.67 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:18 PM PDT 24
Peak memory 233148 kb
Host smart-5dafe4dc-d91d-423d-8e04-ebebb83d3e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453278618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3453278618
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.281444855
Short name T488
Test name
Test status
Simulation time 12674129215 ps
CPU time 104.92 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 251148 kb
Host smart-142b48e5-c84e-4591-85ad-1658d113e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281444855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.281444855
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.964488336
Short name T491
Test name
Test status
Simulation time 438525004 ps
CPU time 2.31 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:03 PM PDT 24
Peak memory 218888 kb
Host smart-e41cdbd1-5f8a-4e2f-915c-bdfa3e6d51a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964488336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.964488336
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1804914417
Short name T663
Test name
Test status
Simulation time 369726435 ps
CPU time 6.09 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:07 PM PDT 24
Peak memory 236152 kb
Host smart-31fdc837-696d-4d49-a494-d97c53e337c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804914417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1804914417
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3934713270
Short name T827
Test name
Test status
Simulation time 2733704690 ps
CPU time 7.66 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:07 PM PDT 24
Peak memory 233096 kb
Host smart-08122d2b-d73b-4a78-bc28-ee104792411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934713270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3934713270
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3388161804
Short name T232
Test name
Test status
Simulation time 7712865272 ps
CPU time 7.83 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:09 PM PDT 24
Peak memory 219468 kb
Host smart-204220c4-d1ca-4761-85f6-e90f48ebf1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388161804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3388161804
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2355365864
Short name T360
Test name
Test status
Simulation time 1734694823 ps
CPU time 8.94 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:25 PM PDT 24
Peak memory 222484 kb
Host smart-be8c2d6e-eca0-4ccf-b514-cd6d9f421dbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355365864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2355365864
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2855903006
Short name T140
Test name
Test status
Simulation time 24840481279 ps
CPU time 261.29 seconds
Started Jul 31 07:36:18 PM PDT 24
Finished Jul 31 07:40:40 PM PDT 24
Peak memory 255036 kb
Host smart-e321e555-f2d9-4bb1-8e04-6b92301dac27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855903006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2855903006
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.348665752
Short name T617
Test name
Test status
Simulation time 2707419882 ps
CPU time 25.62 seconds
Started Jul 31 07:36:00 PM PDT 24
Finished Jul 31 07:36:26 PM PDT 24
Peak memory 216748 kb
Host smart-1f1055a6-9906-45fd-84c4-7b088359b4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348665752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.348665752
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3214568481
Short name T472
Test name
Test status
Simulation time 6230684824 ps
CPU time 13.84 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:15 PM PDT 24
Peak memory 216840 kb
Host smart-c8c1fe5a-be79-41bc-bab3-fb73ca8b1534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214568481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3214568481
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.786464637
Short name T622
Test name
Test status
Simulation time 25944616 ps
CPU time 1.08 seconds
Started Jul 31 07:36:02 PM PDT 24
Finished Jul 31 07:36:03 PM PDT 24
Peak memory 208268 kb
Host smart-8359c54c-ec8a-4136-9bdd-736922934e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786464637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.786464637
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2286640983
Short name T367
Test name
Test status
Simulation time 50899131 ps
CPU time 0.83 seconds
Started Jul 31 07:36:01 PM PDT 24
Finished Jul 31 07:36:02 PM PDT 24
Peak memory 206316 kb
Host smart-6ba30f93-6d8a-4936-ad83-2ecc60723a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286640983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2286640983
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1179914429
Short name T373
Test name
Test status
Simulation time 6090840056 ps
CPU time 9.04 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:23 PM PDT 24
Peak memory 225000 kb
Host smart-4164548b-73a6-479c-8829-ca1ff0ea56ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179914429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1179914429
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2782248054
Short name T983
Test name
Test status
Simulation time 14108587 ps
CPU time 0.75 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:17 PM PDT 24
Peak memory 205224 kb
Host smart-cc204c32-7d19-48c1-a0b4-3441090cb446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782248054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2782248054
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1391178809
Short name T628
Test name
Test status
Simulation time 237005515 ps
CPU time 3.1 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:18 PM PDT 24
Peak memory 233120 kb
Host smart-571cef00-67b6-4ead-8c81-35013830a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391178809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1391178809
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.772214718
Short name T351
Test name
Test status
Simulation time 40541178 ps
CPU time 0.78 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:14 PM PDT 24
Peak memory 206976 kb
Host smart-59f75420-d684-42bb-b3cf-b5040c60707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772214718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.772214718
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1933040196
Short name T409
Test name
Test status
Simulation time 4031269695 ps
CPU time 26.51 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 225076 kb
Host smart-1cebc56b-c3b9-4e42-8507-1ced2a9077cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933040196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1933040196
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3263265654
Short name T815
Test name
Test status
Simulation time 11179017140 ps
CPU time 108.64 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:38:03 PM PDT 24
Peak memory 249588 kb
Host smart-5dbc4c6c-a5e8-4171-b9d7-e71e4113e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263265654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3263265654
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.26909589
Short name T892
Test name
Test status
Simulation time 4369363900 ps
CPU time 58.1 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:37:15 PM PDT 24
Peak memory 250400 kb
Host smart-37723643-faa0-4bb1-ac88-512efec41813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26909589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.26909589
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2003323466
Short name T696
Test name
Test status
Simulation time 1215330688 ps
CPU time 5.13 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 233232 kb
Host smart-aaf8bd02-4d0e-4967-a3ef-84b4d1045504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003323466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2003323466
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3929199184
Short name T552
Test name
Test status
Simulation time 1448703154 ps
CPU time 11.56 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:25 PM PDT 24
Peak memory 241264 kb
Host smart-e87128fa-e046-46d3-8339-616ad121bced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929199184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3929199184
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1404537191
Short name T251
Test name
Test status
Simulation time 4453349619 ps
CPU time 18.35 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:35 PM PDT 24
Peak memory 224892 kb
Host smart-76bc046c-78b0-4f50-b691-3769897b358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404537191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1404537191
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3756583645
Short name T975
Test name
Test status
Simulation time 54603684707 ps
CPU time 27.08 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:42 PM PDT 24
Peak memory 251692 kb
Host smart-89526266-bd20-41e7-af9a-6c01ea2c3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756583645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3756583645
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3640200227
Short name T326
Test name
Test status
Simulation time 404513486 ps
CPU time 3.61 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:19 PM PDT 24
Peak memory 221080 kb
Host smart-6680c527-fc58-4319-8e9f-ea20f6f00325
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3640200227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3640200227
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2475032412
Short name T1001
Test name
Test status
Simulation time 168612226261 ps
CPU time 259.98 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:40:33 PM PDT 24
Peak memory 250700 kb
Host smart-6511142e-9d8d-4d4f-850d-6c9ebcd72c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475032412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2475032412
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3747733801
Short name T684
Test name
Test status
Simulation time 10578973610 ps
CPU time 22.75 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 216836 kb
Host smart-2bcba15d-6ace-444d-bc28-18c89a19699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747733801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3747733801
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1993064880
Short name T950
Test name
Test status
Simulation time 17545404 ps
CPU time 0.72 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:13 PM PDT 24
Peak memory 206064 kb
Host smart-a9c68402-65b1-4161-aa2c-562f0604a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993064880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1993064880
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2994765887
Short name T496
Test name
Test status
Simulation time 105820771 ps
CPU time 4.04 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:19 PM PDT 24
Peak memory 216564 kb
Host smart-b503d737-a5d2-4e9d-b4e7-a10c451bdbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994765887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2994765887
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1782976142
Short name T33
Test name
Test status
Simulation time 1307889452 ps
CPU time 1 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:16 PM PDT 24
Peak memory 207272 kb
Host smart-a9b1deb1-ac1f-407c-b26c-d0f2eaf9a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782976142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1782976142
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.788296449
Short name T817
Test name
Test status
Simulation time 704982464 ps
CPU time 5.36 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 224948 kb
Host smart-c56edb04-52d2-4c62-af0b-b4c6c46334b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788296449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.788296449
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3440313826
Short name T445
Test name
Test status
Simulation time 42978365 ps
CPU time 0.72 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:16 PM PDT 24
Peak memory 205836 kb
Host smart-1be35f15-9666-462b-b931-c783ce4f8c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440313826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3440313826
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2149856393
Short name T601
Test name
Test status
Simulation time 1998365679 ps
CPU time 14.32 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:31 PM PDT 24
Peak memory 233224 kb
Host smart-647d098f-0613-45e8-b240-334a32b6c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149856393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2149856393
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2884722205
Short name T808
Test name
Test status
Simulation time 59114186 ps
CPU time 0.78 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:14 PM PDT 24
Peak memory 207260 kb
Host smart-284c6391-24c6-441e-a9c6-b00959a0ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884722205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2884722205
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1442908983
Short name T814
Test name
Test status
Simulation time 20287144033 ps
CPU time 151.76 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:38:46 PM PDT 24
Peak memory 249584 kb
Host smart-ee63ef00-7327-4d7f-981c-f13fe9442044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442908983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1442908983
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.869706805
Short name T212
Test name
Test status
Simulation time 22010177470 ps
CPU time 138.06 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:38:34 PM PDT 24
Peak memory 249644 kb
Host smart-37e37865-493a-44fa-8b9a-c7eb74f3d94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869706805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.869706805
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.641807743
Short name T805
Test name
Test status
Simulation time 16812145870 ps
CPU time 178.51 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:39:13 PM PDT 24
Peak memory 256732 kb
Host smart-36f01326-7c03-43fd-a75f-4e4f720427f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641807743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.641807743
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3795707740
Short name T346
Test name
Test status
Simulation time 246770356 ps
CPU time 2.93 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 233144 kb
Host smart-343486b4-489d-428e-977e-bf7b06dc4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795707740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3795707740
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1387623879
Short name T649
Test name
Test status
Simulation time 1368677871 ps
CPU time 26.28 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 238516 kb
Host smart-48b8300d-a416-49fd-87de-2524c93e2bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387623879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1387623879
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.451612273
Short name T393
Test name
Test status
Simulation time 1539159708 ps
CPU time 5.13 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 224892 kb
Host smart-f796e762-87b6-4ec5-a7a3-e99407a9967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451612273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.451612273
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3803663898
Short name T10
Test name
Test status
Simulation time 1463254935 ps
CPU time 7.26 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:24 PM PDT 24
Peak memory 233152 kb
Host smart-1e64fb4c-b69f-435e-97a7-3c6d84e64025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803663898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3803663898
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2000965138
Short name T839
Test name
Test status
Simulation time 1259948300 ps
CPU time 7.48 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 233068 kb
Host smart-ba8cd2a7-485f-4c4a-8f0b-7dff12ce63e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000965138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2000965138
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.867437016
Short name T382
Test name
Test status
Simulation time 33402140 ps
CPU time 2.32 seconds
Started Jul 31 07:36:12 PM PDT 24
Finished Jul 31 07:36:14 PM PDT 24
Peak memory 232836 kb
Host smart-bd8339f8-8e10-4a2e-a808-435466016b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867437016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.867437016
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3169621479
Short name T146
Test name
Test status
Simulation time 728707576 ps
CPU time 6.43 seconds
Started Jul 31 07:36:13 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 222024 kb
Host smart-a2c0c3a9-dcae-49a6-a2b4-d271d0b24edc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3169621479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3169621479
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.419250452
Short name T647
Test name
Test status
Simulation time 17174181740 ps
CPU time 132.74 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:38:29 PM PDT 24
Peak memory 257836 kb
Host smart-29063ff8-bc23-4a15-9f9a-40fd37020fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419250452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.419250452
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.565393074
Short name T705
Test name
Test status
Simulation time 46967444307 ps
CPU time 32 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:48 PM PDT 24
Peak memory 216772 kb
Host smart-3e809332-6840-4065-ae33-3bc582297a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565393074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.565393074
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.305344591
Short name T347
Test name
Test status
Simulation time 1599395277 ps
CPU time 5.01 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:22 PM PDT 24
Peak memory 216600 kb
Host smart-a2ec956d-8773-4fef-ada2-f443535c1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305344591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.305344591
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3427577766
Short name T352
Test name
Test status
Simulation time 37634753 ps
CPU time 0.71 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:17 PM PDT 24
Peak memory 205984 kb
Host smart-777f1806-2386-4b56-b3bf-c22685e65928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427577766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3427577766
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1455841110
Short name T667
Test name
Test status
Simulation time 124873029 ps
CPU time 0.79 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:18 PM PDT 24
Peak memory 206368 kb
Host smart-c38fcf5e-fd0a-4a81-8441-e3fe2350c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455841110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1455841110
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.279851026
Short name T576
Test name
Test status
Simulation time 8759748432 ps
CPU time 27.6 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:42 PM PDT 24
Peak memory 224868 kb
Host smart-82a86737-70fc-4f2e-b52c-cae0821029fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279851026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.279851026
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.591982735
Short name T336
Test name
Test status
Simulation time 13602902 ps
CPU time 0.73 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 205992 kb
Host smart-746ebc44-3d7a-438e-852f-0657da246b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591982735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.591982735
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2610038909
Short name T776
Test name
Test status
Simulation time 331602094 ps
CPU time 2.52 seconds
Started Jul 31 07:36:18 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 224944 kb
Host smart-7b5e5829-d68f-4d5f-be90-a6b0c654eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610038909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2610038909
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2294363928
Short name T726
Test name
Test status
Simulation time 14274743 ps
CPU time 0.82 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:16 PM PDT 24
Peak memory 207256 kb
Host smart-0b7a7a02-dd1a-4c51-8d27-6f53f2be4ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294363928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2294363928
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3109071308
Short name T270
Test name
Test status
Simulation time 3323529435 ps
CPU time 21.97 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:38 PM PDT 24
Peak memory 241476 kb
Host smart-af71f74a-c717-49ac-bbe6-5ea1930c9615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109071308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3109071308
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1842078269
Short name T171
Test name
Test status
Simulation time 268245685569 ps
CPU time 260.59 seconds
Started Jul 31 07:36:19 PM PDT 24
Finished Jul 31 07:40:40 PM PDT 24
Peak memory 240636 kb
Host smart-cc60b745-6967-4234-90ba-794f0dff37c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842078269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1842078269
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3455989736
Short name T778
Test name
Test status
Simulation time 5427472406 ps
CPU time 96.63 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:38:05 PM PDT 24
Peak memory 256528 kb
Host smart-52f2aebe-789b-4695-b94b-78f611d98fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455989736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3455989736
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.407055541
Short name T615
Test name
Test status
Simulation time 58051718 ps
CPU time 2.31 seconds
Started Jul 31 07:36:19 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 224564 kb
Host smart-7b10c0cb-2eae-4315-a82a-d1fcb401733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407055541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.407055541
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1118669712
Short name T631
Test name
Test status
Simulation time 886676663 ps
CPU time 5.56 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:22 PM PDT 24
Peak memory 230568 kb
Host smart-ffa4b31d-def9-4da1-b3ae-7ce9cfcb55f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118669712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1118669712
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.94660597
Short name T209
Test name
Test status
Simulation time 12452362506 ps
CPU time 116.53 seconds
Started Jul 31 07:36:19 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 234132 kb
Host smart-ee26d15e-cea6-4f05-b68b-8814f9b77690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94660597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.94660597
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.872355552
Short name T739
Test name
Test status
Simulation time 1081399404 ps
CPU time 4.35 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:22 PM PDT 24
Peak memory 224852 kb
Host smart-ab76e46d-42b5-4719-b981-57dd1259af7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872355552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.872355552
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3653659994
Short name T238
Test name
Test status
Simulation time 824916475 ps
CPU time 7.16 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:23 PM PDT 24
Peak memory 238436 kb
Host smart-8f3a313b-10bd-46ea-b198-5f5b8ca25023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653659994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3653659994
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1900003865
Short name T794
Test name
Test status
Simulation time 397689005 ps
CPU time 3.67 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 220968 kb
Host smart-c510801a-8cbd-4c13-8755-1ca3368e8f8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1900003865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1900003865
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2158293917
Short name T981
Test name
Test status
Simulation time 2706509447 ps
CPU time 71.24 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 254156 kb
Host smart-bded4912-d8f6-4663-afc8-bef586e0e379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158293917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2158293917
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1974124958
Short name T27
Test name
Test status
Simulation time 14252832029 ps
CPU time 18 seconds
Started Jul 31 07:36:17 PM PDT 24
Finished Jul 31 07:36:35 PM PDT 24
Peak memory 216648 kb
Host smart-d2e5330d-4021-400b-8829-d8ce48e20cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974124958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1974124958
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.855413216
Short name T944
Test name
Test status
Simulation time 2877859916 ps
CPU time 5.2 seconds
Started Jul 31 07:36:14 PM PDT 24
Finished Jul 31 07:36:19 PM PDT 24
Peak memory 216764 kb
Host smart-a6929f0a-5a88-40cd-bfb3-b7657d9e9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855413216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.855413216
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1527661741
Short name T311
Test name
Test status
Simulation time 52423902 ps
CPU time 0.82 seconds
Started Jul 31 07:36:19 PM PDT 24
Finished Jul 31 07:36:20 PM PDT 24
Peak memory 206316 kb
Host smart-fb8fb4aa-1eec-41ec-b9a9-cc33387ed3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527661741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1527661741
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3536365353
Short name T741
Test name
Test status
Simulation time 60224781 ps
CPU time 0.76 seconds
Started Jul 31 07:36:15 PM PDT 24
Finished Jul 31 07:36:16 PM PDT 24
Peak memory 206344 kb
Host smart-5e754ba1-706c-49c9-9934-4bc905692f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536365353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3536365353
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.417739332
Short name T325
Test name
Test status
Simulation time 198404149 ps
CPU time 2.43 seconds
Started Jul 31 07:36:16 PM PDT 24
Finished Jul 31 07:36:18 PM PDT 24
Peak memory 232852 kb
Host smart-47939985-ae48-4597-98d7-930f18129849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417739332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.417739332
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3317860393
Short name T406
Test name
Test status
Simulation time 21153024 ps
CPU time 0.72 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:36:29 PM PDT 24
Peak memory 205812 kb
Host smart-9fac6839-7525-42dd-a46d-51608072c2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317860393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3317860393
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.995367995
Short name T609
Test name
Test status
Simulation time 2714304373 ps
CPU time 12.01 seconds
Started Jul 31 07:36:41 PM PDT 24
Finished Jul 31 07:36:53 PM PDT 24
Peak memory 224964 kb
Host smart-49686fc0-9df5-425d-8e4d-78425d97462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995367995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.995367995
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1092760453
Short name T842
Test name
Test status
Simulation time 15728503 ps
CPU time 0.76 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:36:30 PM PDT 24
Peak memory 205868 kb
Host smart-47bb3b13-f636-45ad-86fc-a0f1e40c33f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092760453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1092760453
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.776215928
Short name T197
Test name
Test status
Simulation time 14532481052 ps
CPU time 27.8 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:57 PM PDT 24
Peak memory 232524 kb
Host smart-edbe22de-c125-4913-81be-ac94eacf4457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776215928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.776215928
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4015225039
Short name T860
Test name
Test status
Simulation time 28867775997 ps
CPU time 200.07 seconds
Started Jul 31 07:36:37 PM PDT 24
Finished Jul 31 07:39:58 PM PDT 24
Peak memory 254004 kb
Host smart-64bbdcf4-2a47-4d60-b22d-ab03dff94bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015225039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4015225039
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1493253473
Short name T343
Test name
Test status
Simulation time 185158979 ps
CPU time 3.57 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:36:34 PM PDT 24
Peak memory 225020 kb
Host smart-553cc455-a380-44cc-a1f1-4638171394b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493253473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1493253473
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1678153399
Short name T924
Test name
Test status
Simulation time 100946215320 ps
CPU time 84.54 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:37:54 PM PDT 24
Peak memory 252260 kb
Host smart-97091026-662f-4d4e-8223-7ac6040ed444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678153399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1678153399
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3639018551
Short name T840
Test name
Test status
Simulation time 49349922 ps
CPU time 2.55 seconds
Started Jul 31 07:36:35 PM PDT 24
Finished Jul 31 07:36:38 PM PDT 24
Peak memory 233168 kb
Host smart-334be687-c466-413d-8fe6-f157e75e5e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639018551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3639018551
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1527995395
Short name T242
Test name
Test status
Simulation time 31119562923 ps
CPU time 72.51 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 233208 kb
Host smart-07023d06-c38f-4670-a465-93992e90db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527995395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1527995395
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2749634891
Short name T198
Test name
Test status
Simulation time 28133465116 ps
CPU time 29.04 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 233120 kb
Host smart-4fa7fba0-1c54-441f-bb63-405aede546d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749634891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2749634891
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4029460730
Short name T732
Test name
Test status
Simulation time 4233602184 ps
CPU time 9.06 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 232020 kb
Host smart-60e47254-d4df-451c-997c-e239daa1674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029460730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4029460730
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2498631072
Short name T821
Test name
Test status
Simulation time 3921750717 ps
CPU time 16.18 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 222448 kb
Host smart-122e5b77-57fc-401b-80b0-310d2e5bf9e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2498631072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2498631072
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1557666828
Short name T20
Test name
Test status
Simulation time 237991551 ps
CPU time 1.02 seconds
Started Jul 31 07:36:40 PM PDT 24
Finished Jul 31 07:36:41 PM PDT 24
Peak memory 207324 kb
Host smart-be35182d-b61b-4b44-a4df-bd6ed3467398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557666828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1557666828
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2100153089
Short name T995
Test name
Test status
Simulation time 18918999902 ps
CPU time 22.18 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 216776 kb
Host smart-ac8e7e68-bbee-49dc-8fa4-0a3c4562fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100153089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2100153089
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.343768517
Short name T923
Test name
Test status
Simulation time 1745380896 ps
CPU time 4.66 seconds
Started Jul 31 07:36:37 PM PDT 24
Finished Jul 31 07:36:42 PM PDT 24
Peak memory 216640 kb
Host smart-1dea3808-4bfb-42b7-9d56-08fc7ebab14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343768517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.343768517
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1310533954
Short name T937
Test name
Test status
Simulation time 780143752 ps
CPU time 2.59 seconds
Started Jul 31 07:36:27 PM PDT 24
Finished Jul 31 07:36:30 PM PDT 24
Peak memory 216644 kb
Host smart-3693068f-b146-4f4e-b089-20569414ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310533954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1310533954
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3430762338
Short name T645
Test name
Test status
Simulation time 126342152 ps
CPU time 0.81 seconds
Started Jul 31 07:36:39 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 206320 kb
Host smart-0dcf41f7-c788-4280-9ae8-28fef2417ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430762338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3430762338
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2161212323
Short name T779
Test name
Test status
Simulation time 3032601070 ps
CPU time 11.87 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:36:41 PM PDT 24
Peak memory 233204 kb
Host smart-498d0779-89b6-47fb-8f18-74c3e5c56bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161212323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2161212323
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4159217954
Short name T748
Test name
Test status
Simulation time 24455187 ps
CPU time 0.69 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:07 PM PDT 24
Peak memory 205836 kb
Host smart-0e1f84bf-a00f-46c4-90d7-0d7a0bf54511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159217954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
159217954
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1374675270
Short name T868
Test name
Test status
Simulation time 8364654904 ps
CPU time 18.07 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:23 PM PDT 24
Peak memory 224956 kb
Host smart-aaa41fd3-b4a2-44bc-861a-e06d41a3785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374675270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1374675270
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4199453345
Short name T475
Test name
Test status
Simulation time 25527902 ps
CPU time 0.79 seconds
Started Jul 31 07:35:04 PM PDT 24
Finished Jul 31 07:35:05 PM PDT 24
Peak memory 206996 kb
Host smart-3c849585-7dbe-408f-b3cd-df88bdb2ae65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199453345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4199453345
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2490546741
Short name T539
Test name
Test status
Simulation time 16861075 ps
CPU time 0.72 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:06 PM PDT 24
Peak memory 216132 kb
Host smart-8847d5cb-4068-4ba1-953c-b90a5195bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490546741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2490546741
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.179908772
Short name T737
Test name
Test status
Simulation time 7842890686 ps
CPU time 158.04 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 274168 kb
Host smart-90311723-96c3-4b1a-abdb-bf74ae2e3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179908772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.179908772
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1423222727
Short name T55
Test name
Test status
Simulation time 99155078332 ps
CPU time 468.86 seconds
Started Jul 31 07:35:09 PM PDT 24
Finished Jul 31 07:42:58 PM PDT 24
Peak memory 264656 kb
Host smart-50d4640d-ca60-496a-9260-5af6c42cc42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423222727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1423222727
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2555837562
Short name T630
Test name
Test status
Simulation time 2809339688 ps
CPU time 15.41 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 237056 kb
Host smart-7040ff49-0b37-434f-a341-ee9a29ff33e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555837562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2555837562
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2820339211
Short name T412
Test name
Test status
Simulation time 3594603936 ps
CPU time 37.3 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:44 PM PDT 24
Peak memory 249548 kb
Host smart-8abe5fa9-ba7d-4c2e-96a0-7a238b654de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820339211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2820339211
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3178483427
Short name T685
Test name
Test status
Simulation time 165732405 ps
CPU time 3.91 seconds
Started Jul 31 07:35:04 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 224936 kb
Host smart-199d60fe-1ea9-4731-baf3-dec7505d4518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178483427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3178483427
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3534997010
Short name T371
Test name
Test status
Simulation time 34893629 ps
CPU time 2.3 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 232740 kb
Host smart-341b3e05-2c7e-4f5b-85f6-5e4ba1037f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534997010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3534997010
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3980314543
Short name T844
Test name
Test status
Simulation time 867237366 ps
CPU time 3.38 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 224764 kb
Host smart-d325e8f3-7a41-4d7e-8d1a-b32c98821e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980314543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3980314543
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3808144223
Short name T134
Test name
Test status
Simulation time 102805797 ps
CPU time 2.91 seconds
Started Jul 31 07:35:07 PM PDT 24
Finished Jul 31 07:35:10 PM PDT 24
Peak memory 233092 kb
Host smart-59c51f7f-6f95-4ebd-a448-4c3f53292c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808144223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3808144223
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1210836049
Short name T921
Test name
Test status
Simulation time 465701383 ps
CPU time 7.02 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:13 PM PDT 24
Peak memory 222572 kb
Host smart-f6eb53ca-db2f-408e-9146-d80643fd3010
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1210836049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1210836049
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2708722601
Short name T78
Test name
Test status
Simulation time 234028943 ps
CPU time 1.15 seconds
Started Jul 31 07:35:09 PM PDT 24
Finished Jul 31 07:35:11 PM PDT 24
Peak memory 236380 kb
Host smart-f677e2fd-7920-4f79-92de-f0dc870b0440
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708722601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2708722601
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.734542893
Short name T425
Test name
Test status
Simulation time 164618003 ps
CPU time 1.06 seconds
Started Jul 31 07:35:09 PM PDT 24
Finished Jul 31 07:35:10 PM PDT 24
Peak memory 207340 kb
Host smart-75f5a9ec-72c9-411c-b7bc-ae720b556ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734542893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.734542893
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.32932393
Short name T313
Test name
Test status
Simulation time 19967893007 ps
CPU time 14.07 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 216764 kb
Host smart-dcad25ec-b86d-4dcb-9456-446b7df434c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32932393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.32932393
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.424891518
Short name T91
Test name
Test status
Simulation time 623430232 ps
CPU time 5.14 seconds
Started Jul 31 07:35:05 PM PDT 24
Finished Jul 31 07:35:10 PM PDT 24
Peak memory 216584 kb
Host smart-e955f06d-86de-4534-9bd2-d2db748b0ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424891518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.424891518
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.40408413
Short name T379
Test name
Test status
Simulation time 25160734 ps
CPU time 1.13 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:07 PM PDT 24
Peak memory 207752 kb
Host smart-e929596e-ed8c-494f-9d71-cc2f8d8b6cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40408413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.40408413
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.50040629
Short name T430
Test name
Test status
Simulation time 15781902 ps
CPU time 0.73 seconds
Started Jul 31 07:35:03 PM PDT 24
Finished Jul 31 07:35:04 PM PDT 24
Peak memory 206324 kb
Host smart-486973c8-4e33-460f-a063-b49bed519169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50040629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.50040629
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1360862188
Short name T194
Test name
Test status
Simulation time 16037494766 ps
CPU time 14.76 seconds
Started Jul 31 07:35:07 PM PDT 24
Finished Jul 31 07:35:22 PM PDT 24
Peak memory 241332 kb
Host smart-1f58c0de-10a6-4f0a-a036-d9d2ae31e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360862188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1360862188
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3360176952
Short name T561
Test name
Test status
Simulation time 14063002 ps
CPU time 0.7 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:36:29 PM PDT 24
Peak memory 205220 kb
Host smart-6cba7ba9-f9fb-4a2e-ad05-74735bca1fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360176952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3360176952
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.176171746
Short name T800
Test name
Test status
Simulation time 193864101 ps
CPU time 3.08 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 233072 kb
Host smart-39aec502-bbc9-4d0c-9f15-bd3bd3e8505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176171746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.176171746
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1569218614
Short name T965
Test name
Test status
Simulation time 13431038 ps
CPU time 0.79 seconds
Started Jul 31 07:36:40 PM PDT 24
Finished Jul 31 07:36:41 PM PDT 24
Peak memory 207056 kb
Host smart-e6b00250-9222-4f5c-a4b2-4be582c90230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569218614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1569218614
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4292098670
Short name T285
Test name
Test status
Simulation time 58907534782 ps
CPU time 420.33 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:43:31 PM PDT 24
Peak memory 255360 kb
Host smart-0154fa1e-64b9-44ed-8829-fd737d294d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292098670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4292098670
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.249418992
Short name T215
Test name
Test status
Simulation time 23951965162 ps
CPU time 104.42 seconds
Started Jul 31 07:36:34 PM PDT 24
Finished Jul 31 07:38:18 PM PDT 24
Peak memory 255964 kb
Host smart-34dd0cc5-7629-4f58-8434-cf817932a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249418992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.249418992
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3629026361
Short name T57
Test name
Test status
Simulation time 49731019409 ps
CPU time 507.19 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:44:59 PM PDT 24
Peak memory 272124 kb
Host smart-7f410c18-69a8-4445-928d-ce4ef3589739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629026361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3629026361
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3255159824
Short name T376
Test name
Test status
Simulation time 35032833868 ps
CPU time 15.65 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 236304 kb
Host smart-4d164015-ef62-4a1c-af51-628b07b22fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255159824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3255159824
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4133321557
Short name T178
Test name
Test status
Simulation time 635063900 ps
CPU time 7.74 seconds
Started Jul 31 07:36:35 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 233092 kb
Host smart-5df93aab-59a3-4a94-b4af-01184296658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133321557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4133321557
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2393284567
Short name T676
Test name
Test status
Simulation time 22998766396 ps
CPU time 64.82 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 233148 kb
Host smart-c69d0bc7-b81c-483f-9d22-7bb4abbb70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393284567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2393284567
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1338020010
Short name T255
Test name
Test status
Simulation time 8332127807 ps
CPU time 8 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:36:36 PM PDT 24
Peak memory 224940 kb
Host smart-e1e28d31-fdd2-4a8a-b268-43f1812e0e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338020010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1338020010
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3028991767
Short name T650
Test name
Test status
Simulation time 8986434820 ps
CPU time 14.36 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 225020 kb
Host smart-b484079c-74f3-4c55-ab4a-9c3befe1f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028991767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3028991767
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1132793372
Short name T621
Test name
Test status
Simulation time 201168207 ps
CPU time 4.91 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:38 PM PDT 24
Peak memory 223536 kb
Host smart-aa2da53e-ec83-49d2-a9d0-4881aad75631
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132793372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1132793372
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1557127822
Short name T139
Test name
Test status
Simulation time 313792395112 ps
CPU time 633.09 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:47:20 PM PDT 24
Peak memory 282448 kb
Host smart-8228a678-8868-4c27-897f-603251e70e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557127822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1557127822
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3079896944
Short name T498
Test name
Test status
Simulation time 7815022481 ps
CPU time 41.65 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:37:14 PM PDT 24
Peak memory 216624 kb
Host smart-fed2cce2-a617-463e-88ef-eb126f39e822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079896944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3079896944
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3540362948
Short name T403
Test name
Test status
Simulation time 14043941 ps
CPU time 0.71 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:34 PM PDT 24
Peak memory 206076 kb
Host smart-c66dcca5-a54b-428d-bf0c-9927ffa3f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540362948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3540362948
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2099312972
Short name T362
Test name
Test status
Simulation time 526716798 ps
CPU time 2.21 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 216576 kb
Host smart-eeddc699-b092-4953-9500-5ba7bd3a5836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099312972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2099312972
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.185338675
Short name T693
Test name
Test status
Simulation time 68372106 ps
CPU time 0.86 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:36:46 PM PDT 24
Peak memory 206348 kb
Host smart-23e7aede-7e05-4049-83a6-eac8f016b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185338675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.185338675
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2192300334
Short name T420
Test name
Test status
Simulation time 251726150 ps
CPU time 5.07 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:35 PM PDT 24
Peak memory 233044 kb
Host smart-8ded4f18-8ffa-4a88-bc6e-c0f8bb60f4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192300334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2192300334
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4169617419
Short name T634
Test name
Test status
Simulation time 12731131 ps
CPU time 0.69 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 205844 kb
Host smart-4fa5a268-f593-486e-9525-d3c3ed46804c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169617419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4169617419
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1942550756
Short name T830
Test name
Test status
Simulation time 6207016406 ps
CPU time 14.61 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 233132 kb
Host smart-12d547f1-4d60-4b1b-9240-6c98133053ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942550756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1942550756
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4001069057
Short name T446
Test name
Test status
Simulation time 81897272 ps
CPU time 0.77 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:34 PM PDT 24
Peak memory 206968 kb
Host smart-0abc5f27-f6d0-4d0c-9e41-1785815bea2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001069057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4001069057
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2979285159
Short name T190
Test name
Test status
Simulation time 35037114575 ps
CPU time 261.19 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:41:07 PM PDT 24
Peak memory 262456 kb
Host smart-0d932ba4-194b-4061-9308-6e7f77834800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979285159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2979285159
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4162506893
Short name T160
Test name
Test status
Simulation time 50202821108 ps
CPU time 80.68 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:37:54 PM PDT 24
Peak memory 241488 kb
Host smart-f75e82b4-29ab-4b4b-91ef-626335a8ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162506893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4162506893
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2170493957
Short name T681
Test name
Test status
Simulation time 1642754383 ps
CPU time 19.16 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:36:48 PM PDT 24
Peak memory 224928 kb
Host smart-72342b5f-ddbf-4d64-9fbd-c18036fa2746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170493957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2170493957
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3402159445
Short name T291
Test name
Test status
Simulation time 4476657321 ps
CPU time 19.42 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 233224 kb
Host smart-a4d4539f-e4c7-4a47-9b44-dc70c905708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402159445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3402159445
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3073001616
Short name T426
Test name
Test status
Simulation time 3259220736 ps
CPU time 24.29 seconds
Started Jul 31 07:36:28 PM PDT 24
Finished Jul 31 07:36:53 PM PDT 24
Peak memory 241356 kb
Host smart-a7cef784-5c4e-44ac-81f1-b4faec66f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073001616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3073001616
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2244475891
Short name T635
Test name
Test status
Simulation time 6723813608 ps
CPU time 19.17 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 233100 kb
Host smart-a022ec8c-946e-4ab3-a1e8-b0b130b56615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244475891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2244475891
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1200751631
Short name T543
Test name
Test status
Simulation time 1720053749 ps
CPU time 23.58 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:54 PM PDT 24
Peak memory 233120 kb
Host smart-bbc2555b-71f1-41f8-9950-19b8ad6ce735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200751631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1200751631
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3339407548
Short name T806
Test name
Test status
Simulation time 1109039859 ps
CPU time 7.66 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 233240 kb
Host smart-c8c70612-39dd-4a82-a50d-8e37698e227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339407548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3339407548
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1286530967
Short name T222
Test name
Test status
Simulation time 825876610 ps
CPU time 3.71 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:36:48 PM PDT 24
Peak memory 233172 kb
Host smart-7bef0878-16e7-4270-aefd-140be9401227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286530967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1286530967
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2620654261
Short name T500
Test name
Test status
Simulation time 66267399 ps
CPU time 3.41 seconds
Started Jul 31 07:36:34 PM PDT 24
Finished Jul 31 07:36:37 PM PDT 24
Peak memory 223468 kb
Host smart-e4f031df-b372-4483-9d0e-c746fbe40d90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2620654261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2620654261
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.82375139
Short name T916
Test name
Test status
Simulation time 2559898242 ps
CPU time 40.31 seconds
Started Jul 31 07:36:29 PM PDT 24
Finished Jul 31 07:37:09 PM PDT 24
Peak memory 237420 kb
Host smart-3962f73f-faf9-4cb5-b17d-61ec8353e5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82375139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.82375139
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2699567975
Short name T816
Test name
Test status
Simulation time 36903483749 ps
CPU time 29.21 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:37:13 PM PDT 24
Peak memory 216788 kb
Host smart-0e1f6732-8b11-4061-a4d4-73ac5b078c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699567975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2699567975
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3437520665
Short name T419
Test name
Test status
Simulation time 144571898 ps
CPU time 1.42 seconds
Started Jul 31 07:36:38 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 208264 kb
Host smart-c70e2441-a7d8-40d5-8871-06d610a2c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437520665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3437520665
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1155182763
Short name T889
Test name
Test status
Simulation time 19971208 ps
CPU time 0.98 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:34 PM PDT 24
Peak memory 207872 kb
Host smart-0f613203-f376-43e8-8b8a-6eced8d4af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155182763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1155182763
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.80202065
Short name T460
Test name
Test status
Simulation time 23205288 ps
CPU time 0.68 seconds
Started Jul 31 07:36:30 PM PDT 24
Finished Jul 31 07:36:31 PM PDT 24
Peak memory 206000 kb
Host smart-6f9a06e2-fc6d-4e31-a266-46fe2a12d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80202065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.80202065
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3254494828
Short name T719
Test name
Test status
Simulation time 455425129 ps
CPU time 2.34 seconds
Started Jul 31 07:36:31 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 223172 kb
Host smart-eec85c34-e467-46b3-a209-9bd2d0d7464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254494828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3254494828
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3803895157
Short name T593
Test name
Test status
Simulation time 60865704 ps
CPU time 0.72 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:36:47 PM PDT 24
Peak memory 205352 kb
Host smart-748956b1-f8c5-4068-827b-caa971ccdda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803895157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3803895157
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3676330950
Short name T533
Test name
Test status
Simulation time 1714970758 ps
CPU time 9.3 seconds
Started Jul 31 07:36:34 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 233108 kb
Host smart-d04fb420-05db-4655-bdcb-a427cdbd6264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676330950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3676330950
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3650827243
Short name T394
Test name
Test status
Simulation time 61209211 ps
CPU time 0.74 seconds
Started Jul 31 07:36:43 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 207340 kb
Host smart-a31de6a5-4d55-4ed5-ab09-6eb8cb886c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650827243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3650827243
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.121742163
Short name T861
Test name
Test status
Simulation time 12546937163 ps
CPU time 20.78 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 225056 kb
Host smart-ae2708d7-cde4-4c60-8463-7a1225e9a3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121742163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.121742163
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.56411706
Short name T891
Test name
Test status
Simulation time 1564263378 ps
CPU time 36.75 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:37:21 PM PDT 24
Peak memory 249564 kb
Host smart-d096ba46-0603-4926-a611-68bebf9da001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56411706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.56411706
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1001032637
Short name T471
Test name
Test status
Simulation time 3660666060 ps
CPU time 59.77 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:37:32 PM PDT 24
Peak memory 249588 kb
Host smart-548d7010-f982-42d9-8eda-9540a62300b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001032637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1001032637
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3595023420
Short name T264
Test name
Test status
Simulation time 42377082837 ps
CPU time 277.48 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:41:11 PM PDT 24
Peak memory 256380 kb
Host smart-57d00964-dd1c-4732-94f2-fd6b4cccac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595023420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3595023420
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1160948826
Short name T529
Test name
Test status
Simulation time 1139753721 ps
CPU time 10.44 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:44 PM PDT 24
Peak memory 224872 kb
Host smart-28e8b00c-df9f-41c6-8a08-0ded0b2bad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160948826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1160948826
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1665963680
Short name T930
Test name
Test status
Simulation time 422431145 ps
CPU time 5.41 seconds
Started Jul 31 07:36:34 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 224920 kb
Host smart-4f5c046d-9b10-4708-a96d-29b10a3b3d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665963680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1665963680
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.622478562
Short name T274
Test name
Test status
Simulation time 858335809 ps
CPU time 8.59 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:36:54 PM PDT 24
Peak memory 233080 kb
Host smart-8f2ca22b-e288-4004-a28b-2f36cc16ff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622478562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.622478562
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.779553772
Short name T508
Test name
Test status
Simulation time 693753193 ps
CPU time 8.2 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:36:40 PM PDT 24
Peak memory 224896 kb
Host smart-b247fa28-132d-4416-92b9-8c9942984cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779553772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.779553772
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.275038100
Short name T385
Test name
Test status
Simulation time 678981288 ps
CPU time 9.59 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:36:56 PM PDT 24
Peak memory 223104 kb
Host smart-acb0ebe7-b609-4a89-b845-e04561979c72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275038100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.275038100
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.90264605
Short name T797
Test name
Test status
Simulation time 276546706 ps
CPU time 1.2 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 207436 kb
Host smart-94d952e7-bcb3-4f11-bb58-f3a11e9e917e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90264605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress
_all.90264605
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2637513481
Short name T583
Test name
Test status
Simulation time 4596344396 ps
CPU time 26.54 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:37:00 PM PDT 24
Peak memory 216916 kb
Host smart-e732fb8e-63ea-4109-8f03-b89e6ac309b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637513481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2637513481
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1212639138
Short name T888
Test name
Test status
Simulation time 5494947219 ps
CPU time 14.94 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:48 PM PDT 24
Peak memory 216692 kb
Host smart-dd4bb5e4-4d96-48a7-a508-ea5434f5efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212639138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1212639138
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1245731300
Short name T887
Test name
Test status
Simulation time 133279280 ps
CPU time 1.54 seconds
Started Jul 31 07:36:33 PM PDT 24
Finished Jul 31 07:36:35 PM PDT 24
Peak memory 216764 kb
Host smart-a0464c0b-a8f7-48ae-a1e3-10c12e691eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245731300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1245731300
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3392504060
Short name T976
Test name
Test status
Simulation time 133853617 ps
CPU time 0.86 seconds
Started Jul 31 07:36:32 PM PDT 24
Finished Jul 31 07:36:33 PM PDT 24
Peak memory 206376 kb
Host smart-2b298367-dd34-45e5-9fc5-0439a070aa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392504060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3392504060
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3376010958
Short name T206
Test name
Test status
Simulation time 36200799835 ps
CPU time 30.2 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:37:16 PM PDT 24
Peak memory 249632 kb
Host smart-7006aee8-6a75-4483-b4ed-3ac768699e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376010958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3376010958
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3020570855
Short name T443
Test name
Test status
Simulation time 23209508 ps
CPU time 0.73 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 206128 kb
Host smart-e303e0c5-64c1-4451-aedb-1cb518e9f789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020570855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3020570855
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2351050872
Short name T906
Test name
Test status
Simulation time 496245550 ps
CPU time 9.21 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:36:56 PM PDT 24
Peak memory 224872 kb
Host smart-4c0ecc90-45da-49a3-be3e-4e6da91908e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351050872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2351050872
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.887724104
Short name T130
Test name
Test status
Simulation time 20880464 ps
CPU time 0.78 seconds
Started Jul 31 07:36:41 PM PDT 24
Finished Jul 31 07:36:42 PM PDT 24
Peak memory 206988 kb
Host smart-35cd3112-43fe-406c-96b1-690e74e6331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887724104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.887724104
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2192115483
Short name T661
Test name
Test status
Simulation time 575209510 ps
CPU time 8.44 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:36:53 PM PDT 24
Peak memory 235556 kb
Host smart-18b7b0ba-e58a-4446-9336-27dc2dbeba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192115483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2192115483
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.505374134
Short name T279
Test name
Test status
Simulation time 47986146801 ps
CPU time 434.54 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:43:56 PM PDT 24
Peak memory 273980 kb
Host smart-60f78852-066a-4f26-9e79-4eead0d9cf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505374134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.505374134
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4140086975
Short name T295
Test name
Test status
Simulation time 340768639 ps
CPU time 8.21 seconds
Started Jul 31 07:36:39 PM PDT 24
Finished Jul 31 07:36:47 PM PDT 24
Peak memory 224956 kb
Host smart-c1f0b853-6423-4d7d-bdec-a1494da24c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140086975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4140086975
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2938504035
Short name T219
Test name
Test status
Simulation time 26964297609 ps
CPU time 194.86 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:39:59 PM PDT 24
Peak memory 249532 kb
Host smart-ec17935a-0dde-479d-8f42-b634e5c54c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938504035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2938504035
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.599488807
Short name T856
Test name
Test status
Simulation time 6934522675 ps
CPU time 12.75 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:37:00 PM PDT 24
Peak memory 224876 kb
Host smart-7a7243fd-d5e7-49e9-b7f3-c53e8afac1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599488807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.599488807
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2777376086
Short name T721
Test name
Test status
Simulation time 148453285 ps
CPU time 5.52 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 224872 kb
Host smart-c57c8c45-fb9f-4ab1-af90-fe0465c4d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777376086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2777376086
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3721487532
Short name T542
Test name
Test status
Simulation time 20259670958 ps
CPU time 23.85 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 225012 kb
Host smart-1014c171-f1f7-446c-8189-ac4edfb4dd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721487532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3721487532
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2997103926
Short name T229
Test name
Test status
Simulation time 833877347 ps
CPU time 3.1 seconds
Started Jul 31 07:36:40 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 224844 kb
Host smart-f3b074b0-ecb5-435d-ad11-d8f26c63bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997103926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2997103926
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3961258214
Short name T342
Test name
Test status
Simulation time 886359451 ps
CPU time 9.6 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:36:58 PM PDT 24
Peak memory 220956 kb
Host smart-98c9b3d8-ce60-4b0e-b7c1-b1aef3e7229d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3961258214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3961258214
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.657373869
Short name T18
Test name
Test status
Simulation time 3914091509 ps
CPU time 50.81 seconds
Started Jul 31 07:36:39 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 255388 kb
Host smart-da1b546a-75b6-479e-aca4-a8a2162626a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657373869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.657373869
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1038938679
Short name T574
Test name
Test status
Simulation time 8383795681 ps
CPU time 30.19 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:37:14 PM PDT 24
Peak memory 216808 kb
Host smart-db61b518-00ef-4365-ac94-7ffd0017a366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038938679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1038938679
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.102424705
Short name T658
Test name
Test status
Simulation time 1973799686 ps
CPU time 5.81 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 216628 kb
Host smart-c1971878-7f3c-43ae-91bd-b43a1aea1a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102424705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.102424705
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4215989045
Short name T534
Test name
Test status
Simulation time 223148875 ps
CPU time 1.97 seconds
Started Jul 31 07:36:41 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 216684 kb
Host smart-ca890daa-463b-4a14-84c8-1b1f4365971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215989045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4215989045
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1950432785
Short name T592
Test name
Test status
Simulation time 21265010 ps
CPU time 0.75 seconds
Started Jul 31 07:36:44 PM PDT 24
Finished Jul 31 07:36:45 PM PDT 24
Peak memory 206424 kb
Host smart-5516339e-260b-4d6c-9224-42ab7a94bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950432785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1950432785
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2147475155
Short name T979
Test name
Test status
Simulation time 2690110720 ps
CPU time 9.63 seconds
Started Jul 31 07:36:43 PM PDT 24
Finished Jul 31 07:36:53 PM PDT 24
Peak memory 219048 kb
Host smart-e3e9b8fd-0db6-4672-8eb3-e7291a52cee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147475155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2147475155
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1049161258
Short name T71
Test name
Test status
Simulation time 15382435 ps
CPU time 0.72 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 205260 kb
Host smart-4cf43d5a-21ee-4efe-935e-566840992121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049161258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1049161258
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2546523998
Short name T231
Test name
Test status
Simulation time 427645270 ps
CPU time 3.01 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:46 PM PDT 24
Peak memory 233048 kb
Host smart-299932ef-0a69-4096-87bc-b3a9e10337a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546523998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2546523998
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3810270513
Short name T344
Test name
Test status
Simulation time 118106504 ps
CPU time 0.73 seconds
Started Jul 31 07:36:41 PM PDT 24
Finished Jul 31 07:36:42 PM PDT 24
Peak memory 205908 kb
Host smart-496940ed-213b-418a-b45e-9361ce01a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810270513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3810270513
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1045321027
Short name T265
Test name
Test status
Simulation time 51575592789 ps
CPU time 141.82 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:39:10 PM PDT 24
Peak memory 253060 kb
Host smart-25ba0329-023c-40b4-a8cb-f6a89aed30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045321027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1045321027
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1232797974
Short name T833
Test name
Test status
Simulation time 21807778130 ps
CPU time 199.89 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:40:06 PM PDT 24
Peak memory 249648 kb
Host smart-6eb332c4-b33c-4710-9fb5-d83e870bd2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232797974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1232797974
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1562361538
Short name T759
Test name
Test status
Simulation time 2813307574 ps
CPU time 12.6 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:36:59 PM PDT 24
Peak memory 233960 kb
Host smart-2e7bb73d-06c3-4731-858b-234be74769d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562361538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1562361538
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3940233959
Short name T288
Test name
Test status
Simulation time 3762467029 ps
CPU time 15.12 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:57 PM PDT 24
Peak memory 238996 kb
Host smart-3c680758-d961-41ab-99d1-a27cd5606e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940233959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3940233959
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.4108676621
Short name T672
Test name
Test status
Simulation time 60868705100 ps
CPU time 233.01 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:40:41 PM PDT 24
Peak memory 252976 kb
Host smart-3b264d10-1957-4437-b50f-8e677c346e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108676621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.4108676621
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4182712776
Short name T754
Test name
Test status
Simulation time 1355137417 ps
CPU time 3.72 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 224896 kb
Host smart-68774300-0df8-4e33-95de-6bcf3b918316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182712776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4182712776
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.236830229
Short name T358
Test name
Test status
Simulation time 6172354967 ps
CPU time 49.81 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:37:38 PM PDT 24
Peak memory 233200 kb
Host smart-41967aff-25ed-4faa-8811-d3b909fefb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236830229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.236830229
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4208445858
Short name T407
Test name
Test status
Simulation time 121622015225 ps
CPU time 38.85 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:37:27 PM PDT 24
Peak memory 241324 kb
Host smart-f3f9eace-6680-489e-a102-ba2e2d5703f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208445858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4208445858
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1270794152
Short name T250
Test name
Test status
Simulation time 253943277 ps
CPU time 3.14 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:36:50 PM PDT 24
Peak memory 224840 kb
Host smart-c53b2ba2-e1ff-4fec-a6bc-bc1450a3ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270794152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1270794152
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.235098054
Short name T917
Test name
Test status
Simulation time 234062166 ps
CPU time 5.3 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 222948 kb
Host smart-7b4f1b4f-11de-4a96-9aad-6c36ca0d9be6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=235098054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.235098054
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.42072965
Short name T477
Test name
Test status
Simulation time 5941429887 ps
CPU time 98.44 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 257816 kb
Host smart-da136be8-5a0d-4859-8f3e-a8dcf00e9bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress
_all.42072965
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1994207760
Short name T309
Test name
Test status
Simulation time 1044286322 ps
CPU time 6.65 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:49 PM PDT 24
Peak memory 216612 kb
Host smart-ffd5e3a6-038b-465d-b081-ce444217cc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994207760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1994207760
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1729513818
Short name T435
Test name
Test status
Simulation time 36661691 ps
CPU time 0.76 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:36:46 PM PDT 24
Peak memory 206164 kb
Host smart-c74f7c9b-4d14-428a-8666-46a44d7ceb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729513818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1729513818
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4172517405
Short name T383
Test name
Test status
Simulation time 14323059 ps
CPU time 0.7 seconds
Started Jul 31 07:36:42 PM PDT 24
Finished Jul 31 07:36:43 PM PDT 24
Peak memory 206016 kb
Host smart-1ec5ca98-3ab9-443c-9c6a-b5a67121b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172517405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4172517405
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3883193050
Short name T957
Test name
Test status
Simulation time 21287601 ps
CPU time 0.73 seconds
Started Jul 31 07:36:45 PM PDT 24
Finished Jul 31 07:36:46 PM PDT 24
Peak memory 206092 kb
Host smart-666aa89d-b8c1-44e0-85ac-b450c71b5f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883193050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3883193050
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2612862958
Short name T249
Test name
Test status
Simulation time 1803178102 ps
CPU time 10.15 seconds
Started Jul 31 07:36:46 PM PDT 24
Finished Jul 31 07:36:56 PM PDT 24
Peak memory 241196 kb
Host smart-bf92b2a3-404e-4b12-92e2-137e76283dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612862958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2612862958
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.694253709
Short name T940
Test name
Test status
Simulation time 14151781 ps
CPU time 0.72 seconds
Started Jul 31 07:36:54 PM PDT 24
Finished Jul 31 07:36:55 PM PDT 24
Peak memory 206216 kb
Host smart-99ea5b51-2131-4305-b876-76f3e8390977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694253709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.694253709
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1293930126
Short name T441
Test name
Test status
Simulation time 112456139 ps
CPU time 2.52 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:36:53 PM PDT 24
Peak memory 224876 kb
Host smart-24f9e833-3e21-4d59-9420-820c7b6603c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293930126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1293930126
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.636308943
Short name T401
Test name
Test status
Simulation time 49274800 ps
CPU time 0.75 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 207300 kb
Host smart-8dfc9581-bde6-445f-85de-1c78fabbd56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636308943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.636308943
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1232141001
Short name T928
Test name
Test status
Simulation time 94110279151 ps
CPU time 168.68 seconds
Started Jul 31 07:36:49 PM PDT 24
Finished Jul 31 07:39:38 PM PDT 24
Peak memory 265352 kb
Host smart-f81b1d3b-dc31-4f29-943c-15864c0ba10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232141001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1232141001
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2544899735
Short name T745
Test name
Test status
Simulation time 4776809878 ps
CPU time 110.39 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:38:42 PM PDT 24
Peak memory 253352 kb
Host smart-0323b99d-9fd2-4807-a36f-2c710869f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544899735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2544899735
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1258147719
Short name T523
Test name
Test status
Simulation time 7977966727 ps
CPU time 18.47 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:37:47 PM PDT 24
Peak memory 219800 kb
Host smart-ef456788-c524-4800-a6e5-47418686baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258147719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1258147719
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2810820055
Short name T936
Test name
Test status
Simulation time 160930382 ps
CPU time 3.99 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 224940 kb
Host smart-2ef6de20-4f5b-4c89-a23d-6dccfc5a7f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810820055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2810820055
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.680953370
Short name T831
Test name
Test status
Simulation time 45780927289 ps
CPU time 116.74 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:39:25 PM PDT 24
Peak memory 256880 kb
Host smart-1e3191b0-3822-427f-8ec7-166d57b9947e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680953370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.680953370
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2527852843
Short name T45
Test name
Test status
Simulation time 856188301 ps
CPU time 6.57 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:37:39 PM PDT 24
Peak memory 233144 kb
Host smart-5d45cd9d-c18b-4864-9263-b1060f5ec511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527852843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2527852843
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3184289002
Short name T781
Test name
Test status
Simulation time 157848931 ps
CPU time 4.79 seconds
Started Jul 31 07:37:11 PM PDT 24
Finished Jul 31 07:37:16 PM PDT 24
Peak memory 234456 kb
Host smart-040ddad3-6c48-4946-b8dd-2f3646d5a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184289002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3184289002
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1565987892
Short name T918
Test name
Test status
Simulation time 784419961 ps
CPU time 5.01 seconds
Started Jul 31 07:36:52 PM PDT 24
Finished Jul 31 07:36:57 PM PDT 24
Peak memory 224800 kb
Host smart-9803bf0d-6826-4f13-854b-8cb4f29589f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565987892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1565987892
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.383617863
Short name T459
Test name
Test status
Simulation time 2386002018 ps
CPU time 3.45 seconds
Started Jul 31 07:36:48 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 233160 kb
Host smart-16718478-1ec0-4889-a7b6-83a66092e2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383617863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.383617863
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2172083761
Short name T42
Test name
Test status
Simulation time 81734516 ps
CPU time 3.94 seconds
Started Jul 31 07:36:52 PM PDT 24
Finished Jul 31 07:36:56 PM PDT 24
Peak memory 223416 kb
Host smart-8c603998-dd18-461b-8396-b4734df4363e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2172083761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2172083761
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2338018137
Short name T135
Test name
Test status
Simulation time 58198381 ps
CPU time 1.09 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 207600 kb
Host smart-36481246-bad6-4a90-b7de-2547b00a62e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338018137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2338018137
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3401351780
Short name T904
Test name
Test status
Simulation time 1586636160 ps
CPU time 4.49 seconds
Started Jul 31 07:36:41 PM PDT 24
Finished Jul 31 07:36:46 PM PDT 24
Peak memory 216600 kb
Host smart-50545d38-4ff3-4f7e-a468-ea47901a2ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401351780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3401351780
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.182765916
Short name T540
Test name
Test status
Simulation time 1155957530 ps
CPU time 5.07 seconds
Started Jul 31 07:36:47 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 216560 kb
Host smart-a00df2ee-f72a-45c8-9e1d-a57fb25c9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182765916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.182765916
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1520605805
Short name T687
Test name
Test status
Simulation time 444341112 ps
CPU time 1.87 seconds
Started Jul 31 07:36:49 PM PDT 24
Finished Jul 31 07:36:51 PM PDT 24
Peak memory 216616 kb
Host smart-773cbb64-1036-4d12-8ada-bac689d1dc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520605805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1520605805
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.915052221
Short name T614
Test name
Test status
Simulation time 286325344 ps
CPU time 0.92 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 206312 kb
Host smart-3b92b075-4d36-4800-b0b0-9c0e050d16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915052221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.915052221
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1143648220
Short name T828
Test name
Test status
Simulation time 8704230454 ps
CPU time 28.84 seconds
Started Jul 31 07:36:52 PM PDT 24
Finished Jul 31 07:37:20 PM PDT 24
Peak memory 225040 kb
Host smart-e40ffe39-bb4b-4a49-8ebe-b91d68b977d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143648220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1143648220
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3701306503
Short name T880
Test name
Test status
Simulation time 16469477 ps
CPU time 0.74 seconds
Started Jul 31 07:37:01 PM PDT 24
Finished Jul 31 07:37:02 PM PDT 24
Peak memory 205808 kb
Host smart-dd904886-3671-4546-bf13-b511be59ec35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701306503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3701306503
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.554206850
Short name T365
Test name
Test status
Simulation time 868475949 ps
CPU time 4.38 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:37:34 PM PDT 24
Peak memory 224888 kb
Host smart-409f7d30-2f84-4ece-a10a-4e47ceb51937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554206850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.554206850
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3137114250
Short name T417
Test name
Test status
Simulation time 49013604 ps
CPU time 0.76 seconds
Started Jul 31 07:36:54 PM PDT 24
Finished Jul 31 07:36:55 PM PDT 24
Peak memory 206972 kb
Host smart-bc748938-d730-446d-a67d-f888e8249484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137114250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3137114250
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3027296198
Short name T357
Test name
Test status
Simulation time 2827358898 ps
CPU time 13.73 seconds
Started Jul 31 07:36:56 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 239404 kb
Host smart-3772c9a2-6ef2-41da-bbd5-52978f26c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027296198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3027296198
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3728453583
Short name T678
Test name
Test status
Simulation time 71068451466 ps
CPU time 343.93 seconds
Started Jul 31 07:37:27 PM PDT 24
Finished Jul 31 07:43:11 PM PDT 24
Peak memory 249588 kb
Host smart-1ceb1b76-ba6f-44b3-9a68-04fcbbfd43a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728453583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3728453583
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1274085121
Short name T30
Test name
Test status
Simulation time 40505132306 ps
CPU time 370.81 seconds
Started Jul 31 07:37:00 PM PDT 24
Finished Jul 31 07:43:11 PM PDT 24
Peak memory 254712 kb
Host smart-4857134d-f3a6-44ca-b3e8-6a17d3136e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274085121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1274085121
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.547925361
Short name T380
Test name
Test status
Simulation time 420217000 ps
CPU time 5.14 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:02 PM PDT 24
Peak memory 249448 kb
Host smart-021fdf7d-8831-44e7-bb8d-91184508e7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547925361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.547925361
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.372852695
Short name T186
Test name
Test status
Simulation time 3342654311 ps
CPU time 42.75 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:38:11 PM PDT 24
Peak memory 233156 kb
Host smart-9eafad94-0938-43b7-9a4a-9edd25b9fbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372852695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.372852695
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2709366411
Short name T869
Test name
Test status
Simulation time 2805233927 ps
CPU time 9.89 seconds
Started Jul 31 07:37:27 PM PDT 24
Finished Jul 31 07:37:37 PM PDT 24
Peak memory 233216 kb
Host smart-6b8eddc2-9afc-4693-8513-9dc03e690880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709366411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2709366411
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2679841838
Short name T235
Test name
Test status
Simulation time 42510063296 ps
CPU time 63.85 seconds
Started Jul 31 07:36:55 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 233160 kb
Host smart-9abccbb4-5a4f-4332-ad8b-0312a7589b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679841838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2679841838
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2236757196
Short name T587
Test name
Test status
Simulation time 17318948738 ps
CPU time 22.28 seconds
Started Jul 31 07:36:56 PM PDT 24
Finished Jul 31 07:37:19 PM PDT 24
Peak memory 233144 kb
Host smart-5e518813-987f-4a4d-a654-8986d2817ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236757196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2236757196
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3637523196
Short name T978
Test name
Test status
Simulation time 6490694731 ps
CPU time 24.04 seconds
Started Jul 31 07:36:53 PM PDT 24
Finished Jul 31 07:37:17 PM PDT 24
Peak memory 233140 kb
Host smart-5169a3cb-0c44-4cef-bd79-753dc2ca6524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637523196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3637523196
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2659766645
Short name T61
Test name
Test status
Simulation time 432784473 ps
CPU time 8.72 seconds
Started Jul 31 07:37:00 PM PDT 24
Finished Jul 31 07:37:08 PM PDT 24
Peak memory 220660 kb
Host smart-aa522f71-84ce-40e6-b224-1ba2feb43bd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2659766645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2659766645
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2394501954
Short name T21
Test name
Test status
Simulation time 72828581 ps
CPU time 0.89 seconds
Started Jul 31 07:36:58 PM PDT 24
Finished Jul 31 07:36:59 PM PDT 24
Peak memory 207260 kb
Host smart-3b5048d7-0200-4d81-8541-7cde52db2b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394501954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2394501954
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3925972716
Short name T317
Test name
Test status
Simulation time 7988561259 ps
CPU time 22.09 seconds
Started Jul 31 07:36:53 PM PDT 24
Finished Jul 31 07:37:15 PM PDT 24
Peak memory 216772 kb
Host smart-7fc8b8e7-89be-4946-b7c0-0a7f07537447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925972716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3925972716
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3482108094
Short name T626
Test name
Test status
Simulation time 2504792940 ps
CPU time 6.3 seconds
Started Jul 31 07:36:54 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 216636 kb
Host smart-a16081d4-c00d-43d8-9c25-4d46f00d7f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482108094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3482108094
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3500926217
Short name T345
Test name
Test status
Simulation time 47273151 ps
CPU time 0.9 seconds
Started Jul 31 07:36:56 PM PDT 24
Finished Jul 31 07:36:58 PM PDT 24
Peak memory 207424 kb
Host smart-9ff0e018-9fcb-4f12-a2c2-df2dad2ef51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500926217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3500926217
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1868448576
Short name T864
Test name
Test status
Simulation time 96855330 ps
CPU time 0.76 seconds
Started Jul 31 07:36:51 PM PDT 24
Finished Jul 31 07:36:52 PM PDT 24
Peak memory 206364 kb
Host smart-9634b961-a4ba-4cde-9a66-5b288900b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868448576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1868448576
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.337851589
Short name T651
Test name
Test status
Simulation time 21069562718 ps
CPU time 27.03 seconds
Started Jul 31 07:36:53 PM PDT 24
Finished Jul 31 07:37:20 PM PDT 24
Peak memory 233220 kb
Host smart-1449c0bf-30a3-4714-9774-060eb4cb3c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337851589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.337851589
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2835310055
Short name T413
Test name
Test status
Simulation time 125018515 ps
CPU time 0.7 seconds
Started Jul 31 07:36:59 PM PDT 24
Finished Jul 31 07:36:59 PM PDT 24
Peak memory 205216 kb
Host smart-68a27376-3104-4fdf-b39f-0de0bb3e3756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835310055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2835310055
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1106360307
Short name T128
Test name
Test status
Simulation time 56692070 ps
CPU time 0.77 seconds
Started Jul 31 07:37:02 PM PDT 24
Finished Jul 31 07:37:03 PM PDT 24
Peak memory 206956 kb
Host smart-f2b97817-35d5-4ec0-8d4c-334acb4a78ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106360307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1106360307
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.670844226
Short name T623
Test name
Test status
Simulation time 20060509486 ps
CPU time 173.57 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:40:24 PM PDT 24
Peak memory 241440 kb
Host smart-8cb04a84-7ce4-47bc-b96a-b3415c1f6b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670844226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.670844226
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2453751531
Short name T969
Test name
Test status
Simulation time 14308734681 ps
CPU time 23.7 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:21 PM PDT 24
Peak memory 234248 kb
Host smart-f119f375-17db-4ed5-90d7-5f4767a5d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453751531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2453751531
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3587158827
Short name T294
Test name
Test status
Simulation time 1640755974 ps
CPU time 10.26 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:37:38 PM PDT 24
Peak memory 233136 kb
Host smart-b500154f-f0b7-4ba3-b5f2-563776bd2de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587158827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3587158827
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3435531726
Short name T894
Test name
Test status
Simulation time 76158307133 ps
CPU time 169.97 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:39:48 PM PDT 24
Peak memory 261468 kb
Host smart-f3ee9ffa-4984-483c-b274-5f9e458c9a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435531726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3435531726
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.587739224
Short name T767
Test name
Test status
Simulation time 7043829547 ps
CPU time 15.41 seconds
Started Jul 31 07:36:58 PM PDT 24
Finished Jul 31 07:37:14 PM PDT 24
Peak memory 233152 kb
Host smart-ff33f744-365d-4f4d-95a5-a139197b470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587739224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.587739224
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2073238143
Short name T558
Test name
Test status
Simulation time 13177169614 ps
CPU time 21.81 seconds
Started Jul 31 07:36:56 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 241312 kb
Host smart-281854d6-a391-4509-a7dc-2696c6eebca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073238143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2073238143
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2681006269
Short name T695
Test name
Test status
Simulation time 377283814 ps
CPU time 2.32 seconds
Started Jul 31 07:36:58 PM PDT 24
Finished Jul 31 07:37:00 PM PDT 24
Peak memory 224836 kb
Host smart-18b12d11-38f5-47f6-bf4a-670531cc3f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681006269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2681006269
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3151103925
Short name T700
Test name
Test status
Simulation time 2483413509 ps
CPU time 7.37 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:39 PM PDT 24
Peak memory 224948 kb
Host smart-ffe9cf48-549b-467d-a430-8bef81f358e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151103925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3151103925
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3662838678
Short name T849
Test name
Test status
Simulation time 1752258445 ps
CPU time 5.39 seconds
Started Jul 31 07:37:00 PM PDT 24
Finished Jul 31 07:37:05 PM PDT 24
Peak memory 220200 kb
Host smart-7c608c85-8555-4564-a14c-eb7f3f6300e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3662838678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3662838678
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4198950788
Short name T764
Test name
Test status
Simulation time 6955084142 ps
CPU time 16.78 seconds
Started Jul 31 07:37:12 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 216888 kb
Host smart-03061c7f-2dec-4581-9488-3762f356e918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198950788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4198950788
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.475563234
Short name T480
Test name
Test status
Simulation time 11151310509 ps
CPU time 29.14 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:37:58 PM PDT 24
Peak memory 216780 kb
Host smart-cf4234c8-e790-4bd7-a661-5bf48f06ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475563234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.475563234
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4004812026
Short name T836
Test name
Test status
Simulation time 191752550 ps
CPU time 1.92 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:16 PM PDT 24
Peak memory 216688 kb
Host smart-3c0068ae-929c-4c23-8f37-ba31ea969b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004812026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4004812026
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2108316189
Short name T547
Test name
Test status
Simulation time 35953893 ps
CPU time 0.77 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:15 PM PDT 24
Peak memory 206424 kb
Host smart-57f956bd-c200-48ed-9383-8d799d92005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108316189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2108316189
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3569507925
Short name T402
Test name
Test status
Simulation time 689936699 ps
CPU time 3.15 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 233160 kb
Host smart-7fe661cc-515b-49ec-b244-68ad49aa52f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569507925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3569507925
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3610393933
Short name T931
Test name
Test status
Simulation time 10707376 ps
CPU time 0.72 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 205224 kb
Host smart-cec9ac80-67aa-4a67-911a-ceb7253610db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610393933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3610393933
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.589599562
Short name T967
Test name
Test status
Simulation time 1336852433 ps
CPU time 5.64 seconds
Started Jul 31 07:36:58 PM PDT 24
Finished Jul 31 07:37:04 PM PDT 24
Peak memory 224892 kb
Host smart-1525c73c-ffe1-4660-99f8-0456310a530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589599562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.589599562
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2378000723
Short name T514
Test name
Test status
Simulation time 54211359 ps
CPU time 0.79 seconds
Started Jul 31 07:37:00 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 207320 kb
Host smart-6b03c436-cd18-4276-8ded-fb9594956445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378000723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2378000723
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3268901573
Short name T284
Test name
Test status
Simulation time 11571322914 ps
CPU time 163.14 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:40:15 PM PDT 24
Peak memory 274164 kb
Host smart-2105e5ea-0316-4bfe-b9d3-bded73d69e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268901573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3268901573
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4202898651
Short name T633
Test name
Test status
Simulation time 3252538389 ps
CPU time 31.32 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 237504 kb
Host smart-09e10298-ff3b-423c-96bc-e533ab5fcace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202898651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4202898651
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.584138694
Short name T64
Test name
Test status
Simulation time 22218252641 ps
CPU time 132.39 seconds
Started Jul 31 07:36:56 PM PDT 24
Finished Jul 31 07:39:08 PM PDT 24
Peak memory 257760 kb
Host smart-7f7648a7-9828-4565-9d76-e561fe089e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584138694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.584138694
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1853078393
Short name T548
Test name
Test status
Simulation time 6090771067 ps
CPU time 21.92 seconds
Started Jul 31 07:37:01 PM PDT 24
Finished Jul 31 07:37:23 PM PDT 24
Peak memory 224968 kb
Host smart-845aa9c9-530b-4752-be11-9b263ce5cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853078393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1853078393
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.603040519
Short name T517
Test name
Test status
Simulation time 10314478073 ps
CPU time 24.2 seconds
Started Jul 31 07:36:59 PM PDT 24
Finished Jul 31 07:37:23 PM PDT 24
Peak memory 233200 kb
Host smart-cc6d9d75-4452-4042-a044-1df582d54895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603040519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.603040519
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.812552548
Short name T173
Test name
Test status
Simulation time 1376343661 ps
CPU time 18.41 seconds
Started Jul 31 07:36:59 PM PDT 24
Finished Jul 31 07:37:17 PM PDT 24
Peak memory 235232 kb
Host smart-5cf1a141-1d37-43d8-9e84-af86d5083b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812552548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.812552548
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3161691259
Short name T429
Test name
Test status
Simulation time 3626542923 ps
CPU time 13.49 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 233320 kb
Host smart-27e9a4c9-a66b-4a52-97df-1961685738bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161691259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3161691259
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2750835847
Short name T241
Test name
Test status
Simulation time 15178145991 ps
CPU time 14.04 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 233084 kb
Host smart-1a0654a0-d6f3-4700-be3f-99eb92ddbadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750835847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2750835847
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.914533366
Short name T632
Test name
Test status
Simulation time 2775180140 ps
CPU time 8.86 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 223612 kb
Host smart-1d986ac4-ab98-4a70-88ba-491116a8f885
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=914533366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.914533366
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1166351589
Short name T158
Test name
Test status
Simulation time 4661052131 ps
CPU time 49.76 seconds
Started Jul 31 07:36:58 PM PDT 24
Finished Jul 31 07:37:48 PM PDT 24
Peak memory 239832 kb
Host smart-496b59e6-3c18-4c5c-8181-89fff868d49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166351589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1166351589
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1182572579
Short name T92
Test name
Test status
Simulation time 3929444921 ps
CPU time 20.75 seconds
Started Jul 31 07:36:57 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 216872 kb
Host smart-fa7b947b-5800-432c-9116-3eded9f9261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182572579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1182572579
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.703530369
Short name T366
Test name
Test status
Simulation time 1132940186 ps
CPU time 5.17 seconds
Started Jul 31 07:37:00 PM PDT 24
Finished Jul 31 07:37:05 PM PDT 24
Peak memory 216676 kb
Host smart-7858b18d-0116-4a05-93f6-3845970bd0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703530369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.703530369
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.190158468
Short name T397
Test name
Test status
Simulation time 144796122 ps
CPU time 2.41 seconds
Started Jul 31 07:36:59 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 216636 kb
Host smart-1551efee-c501-4e63-b27d-2adf866c6f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190158468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.190158468
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3355750016
Short name T820
Test name
Test status
Simulation time 156051860 ps
CPU time 0.85 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:37:31 PM PDT 24
Peak memory 206348 kb
Host smart-8ef3eeb5-6377-4b44-b646-8d605a5fde50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355750016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3355750016
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3654754353
Short name T573
Test name
Test status
Simulation time 1917597905 ps
CPU time 9.42 seconds
Started Jul 31 07:36:59 PM PDT 24
Finished Jul 31 07:37:08 PM PDT 24
Peak memory 241280 kb
Host smart-19c15705-6fe6-4bd9-872a-5104e7f1cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654754353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3654754353
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.94252732
Short name T961
Test name
Test status
Simulation time 32051172 ps
CPU time 0.76 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:32 PM PDT 24
Peak memory 205320 kb
Host smart-84ec83dd-77e9-422c-b603-a8037880c762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94252732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.94252732
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2545105790
Short name T753
Test name
Test status
Simulation time 2340456501 ps
CPU time 22.28 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 233192 kb
Host smart-b3430f89-c706-40d4-85f7-1136c502c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545105790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2545105790
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.574553980
Short name T363
Test name
Test status
Simulation time 43862442 ps
CPU time 0.74 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 206932 kb
Host smart-4101dc87-9477-4e73-94b5-1cbcbab9e4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574553980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.574553980
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3753198998
Short name T811
Test name
Test status
Simulation time 48672398726 ps
CPU time 89.12 seconds
Started Jul 31 07:37:06 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 252524 kb
Host smart-ec7ad172-8628-472a-94f2-82e72643f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753198998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3753198998
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1333132597
Short name T307
Test name
Test status
Simulation time 27783853761 ps
CPU time 60.82 seconds
Started Jul 31 07:37:09 PM PDT 24
Finished Jul 31 07:38:10 PM PDT 24
Peak memory 249772 kb
Host smart-0bfeb0db-46ca-47c4-bb87-4ce83ff058a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333132597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1333132597
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4062828933
Short name T1
Test name
Test status
Simulation time 3022912885 ps
CPU time 20.61 seconds
Started Jul 31 07:37:06 PM PDT 24
Finished Jul 31 07:37:27 PM PDT 24
Peak memory 239732 kb
Host smart-f1a9ef9b-2f06-48db-a6b6-cb924a1eba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062828933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4062828933
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2350051930
Short name T423
Test name
Test status
Simulation time 2998846236 ps
CPU time 29.48 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:37:36 PM PDT 24
Peak memory 224960 kb
Host smart-b70bbf07-ed6c-4d1a-9b57-61040f407037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350051930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2350051930
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3562968148
Short name T193
Test name
Test status
Simulation time 523651486 ps
CPU time 11.24 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:37:19 PM PDT 24
Peak memory 224936 kb
Host smart-0997a627-ca9f-416b-afdd-ab9569d5f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562968148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3562968148
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.33574915
Short name T640
Test name
Test status
Simulation time 577754587 ps
CPU time 5.11 seconds
Started Jul 31 07:37:27 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 224840 kb
Host smart-fd0e6d0a-7fa3-4e85-9871-60acbdcd304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33574915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.33574915
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3668957392
Short name T424
Test name
Test status
Simulation time 335243837 ps
CPU time 5.65 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:11 PM PDT 24
Peak memory 233040 kb
Host smart-0e98bae5-b616-494d-bd3b-76a4edb75da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668957392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3668957392
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3027615513
Short name T374
Test name
Test status
Simulation time 1052013104 ps
CPU time 4.34 seconds
Started Jul 31 07:37:06 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 223632 kb
Host smart-9c14c979-402c-4a94-855c-f1f7b2d5e88b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3027615513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3027615513
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1657319512
Short name T829
Test name
Test status
Simulation time 7833796286 ps
CPU time 125.72 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:39:11 PM PDT 24
Peak memory 255248 kb
Host smart-f81c0514-facf-4ca1-a6ba-45e5d92ed97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657319512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1657319512
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1640893861
Short name T949
Test name
Test status
Simulation time 5489772308 ps
CPU time 24.65 seconds
Started Jul 31 07:37:09 PM PDT 24
Finished Jul 31 07:37:34 PM PDT 24
Peak memory 216696 kb
Host smart-58fae6dc-dbd6-4376-b507-9d032bc92335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640893861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1640893861
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.299543317
Short name T919
Test name
Test status
Simulation time 5565213060 ps
CPU time 16.28 seconds
Started Jul 31 07:37:07 PM PDT 24
Finished Jul 31 07:37:23 PM PDT 24
Peak memory 216760 kb
Host smart-cf1edc49-b6b0-47c8-88a2-c484170fbc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299543317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.299543317
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1280237169
Short name T886
Test name
Test status
Simulation time 59153175 ps
CPU time 0.9 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 207484 kb
Host smart-08d32110-6674-4e32-834f-42de5528aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280237169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1280237169
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.928750612
Short name T440
Test name
Test status
Simulation time 51140938 ps
CPU time 0.73 seconds
Started Jul 31 07:37:12 PM PDT 24
Finished Jul 31 07:37:12 PM PDT 24
Peak memory 206336 kb
Host smart-f474c5da-71fb-4e0b-bb59-6a258f3ec2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928750612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.928750612
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.17353604
Short name T65
Test name
Test status
Simulation time 9446802132 ps
CPU time 11.27 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 225112 kb
Host smart-4670fae0-67af-4471-84cd-710788953a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17353604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.17353604
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3210604540
Short name T708
Test name
Test status
Simulation time 56537489 ps
CPU time 0.74 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:15 PM PDT 24
Peak memory 205352 kb
Host smart-42ed4e08-9e0a-4290-aec1-d235f0ef0ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210604540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
210604540
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1804350237
Short name T221
Test name
Test status
Simulation time 1663077042 ps
CPU time 4.3 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 233056 kb
Host smart-c23fad3a-8e23-4de7-bb73-9de4cfc6ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804350237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1804350237
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1168820440
Short name T616
Test name
Test status
Simulation time 36455307 ps
CPU time 0.78 seconds
Started Jul 31 07:35:07 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 206952 kb
Host smart-b1e38d06-cb17-4dcd-9e53-9f3e2b1dbb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168820440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1168820440
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.321560782
Short name T267
Test name
Test status
Simulation time 28633764795 ps
CPU time 75.69 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:36:30 PM PDT 24
Peak memory 266220 kb
Host smart-d798a43c-d003-481b-ba45-44de6fe89ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321560782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.321560782
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.560532011
Short name T214
Test name
Test status
Simulation time 4550685794 ps
CPU time 43.21 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:36:00 PM PDT 24
Peak memory 248364 kb
Host smart-e37d739e-9100-4bba-aed8-67fbcdb6615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560532011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.560532011
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.836666426
Short name T893
Test name
Test status
Simulation time 17117093116 ps
CPU time 98.02 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:36:54 PM PDT 24
Peak memory 265716 kb
Host smart-c35f6038-b684-495d-ba84-6e3596f5bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836666426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
836666426
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.102020173
Short name T386
Test name
Test status
Simulation time 1607452960 ps
CPU time 23.68 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 233120 kb
Host smart-a2dd5e94-1687-4831-b26d-224c1b9f16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102020173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.102020173
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2579038810
Short name T395
Test name
Test status
Simulation time 28324596626 ps
CPU time 207.63 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:38:41 PM PDT 24
Peak memory 269420 kb
Host smart-e9ecefb5-437f-4e4d-a3ad-e4f4d4440b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579038810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2579038810
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.706203799
Short name T742
Test name
Test status
Simulation time 969670116 ps
CPU time 11.43 seconds
Started Jul 31 07:35:17 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 233132 kb
Host smart-0e0c63ea-a6a8-4c8c-bb06-dccb1ff72653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706203799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.706203799
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.682349673
Short name T532
Test name
Test status
Simulation time 2331604012 ps
CPU time 16.47 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:30 PM PDT 24
Peak memory 253328 kb
Host smart-f3ab1366-7e80-4e26-8dc3-edb784326966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682349673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.682349673
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.556853378
Short name T801
Test name
Test status
Simulation time 4291088171 ps
CPU time 8.39 seconds
Started Jul 31 07:35:12 PM PDT 24
Finished Jul 31 07:35:21 PM PDT 24
Peak memory 224896 kb
Host smart-bd19b65d-6406-4801-8016-4f92fb806255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556853378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
556853378
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3022842596
Short name T756
Test name
Test status
Simulation time 12066015334 ps
CPU time 11.95 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:26 PM PDT 24
Peak memory 225004 kb
Host smart-33978486-c6fb-4578-8f75-caf7be567cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022842596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3022842596
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2003730957
Short name T690
Test name
Test status
Simulation time 339824750 ps
CPU time 4.21 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:35:21 PM PDT 24
Peak memory 223556 kb
Host smart-eb9af836-0d67-4ca5-b31e-237a021622bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2003730957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2003730957
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1834792071
Short name T80
Test name
Test status
Simulation time 127337345 ps
CPU time 1.12 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 235900 kb
Host smart-51390cee-8d09-4e95-9fe1-dbe78ad10685
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834792071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1834792071
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4246727441
Short name T60
Test name
Test status
Simulation time 16063999548 ps
CPU time 84.47 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:36:38 PM PDT 24
Peak memory 253504 kb
Host smart-4a2db696-1269-4073-a08a-f58c494da125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246727441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4246727441
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4153712577
Short name T648
Test name
Test status
Simulation time 5787675360 ps
CPU time 17.75 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:24 PM PDT 24
Peak memory 220396 kb
Host smart-2b95feff-1a65-402d-ba88-b37218da8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153712577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4153712577
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4287361260
Short name T364
Test name
Test status
Simulation time 67960019 ps
CPU time 0.73 seconds
Started Jul 31 07:35:07 PM PDT 24
Finished Jul 31 07:35:08 PM PDT 24
Peak memory 206152 kb
Host smart-4d195bed-95b2-4939-af83-ef4169b75aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287361260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4287361260
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4231030459
Short name T879
Test name
Test status
Simulation time 24881878 ps
CPU time 1.43 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 216712 kb
Host smart-d99cedf2-faf5-42e1-bb3c-ba12090cb5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231030459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4231030459
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1856467679
Short name T526
Test name
Test status
Simulation time 86806405 ps
CPU time 0.96 seconds
Started Jul 31 07:35:06 PM PDT 24
Finished Jul 31 07:35:07 PM PDT 24
Peak memory 206336 kb
Host smart-7b1af9d6-5cf1-406c-b72f-1fdd93857112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856467679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1856467679
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1562519427
Short name T253
Test name
Test status
Simulation time 655815477 ps
CPU time 8.13 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:23 PM PDT 24
Peak memory 233164 kb
Host smart-2c6362db-9058-43f1-b7ef-4b04c6bee3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562519427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1562519427
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3616122260
Short name T862
Test name
Test status
Simulation time 36887222 ps
CPU time 0.76 seconds
Started Jul 31 07:37:17 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 205272 kb
Host smart-225c3753-bdf9-4064-920e-822a680acb2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616122260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3616122260
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.24637798
Short name T95
Test name
Test status
Simulation time 208802949 ps
CPU time 3.25 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 224924 kb
Host smart-d2829056-73ac-4085-81a7-de8990e80775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24637798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.24637798
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3572262323
Short name T992
Test name
Test status
Simulation time 322656885 ps
CPU time 0.81 seconds
Started Jul 31 07:37:06 PM PDT 24
Finished Jul 31 07:37:07 PM PDT 24
Peak memory 207256 kb
Host smart-edb59fcf-012a-4c74-90d3-33cc5edf2736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572262323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3572262323
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2695268677
Short name T38
Test name
Test status
Simulation time 28091357448 ps
CPU time 188.07 seconds
Started Jul 31 07:37:13 PM PDT 24
Finished Jul 31 07:40:22 PM PDT 24
Peak memory 249552 kb
Host smart-b1ba9d77-358a-47a7-ad86-0b9e3e2fc1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695268677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2695268677
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.872885267
Short name T189
Test name
Test status
Simulation time 48744386291 ps
CPU time 495.3 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:45:30 PM PDT 24
Peak memory 269092 kb
Host smart-5c6e8c94-1a84-4489-841f-258183c9cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872885267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.872885267
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.863447415
Short name T927
Test name
Test status
Simulation time 42339044133 ps
CPU time 211.32 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:41:00 PM PDT 24
Peak memory 249660 kb
Host smart-813d6175-2eb4-425e-9f99-734a275921c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863447415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.863447415
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.261543419
Short name T913
Test name
Test status
Simulation time 6017108570 ps
CPU time 28.79 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 233096 kb
Host smart-917520cd-b9b0-414d-ad2f-3caa2f76c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261543419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.261543419
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1860319297
Short name T63
Test name
Test status
Simulation time 9262104543 ps
CPU time 66.93 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 250620 kb
Host smart-dd73d67a-aa18-4708-af86-512e411a7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860319297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1860319297
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2795872692
Short name T228
Test name
Test status
Simulation time 312272044 ps
CPU time 7.52 seconds
Started Jul 31 07:37:10 PM PDT 24
Finished Jul 31 07:37:17 PM PDT 24
Peak memory 224932 kb
Host smart-4677cdf8-2080-4cf9-b17f-ad1d65cb1ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795872692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2795872692
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4222776211
Short name T227
Test name
Test status
Simulation time 1392890192 ps
CPU time 11.05 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:37:40 PM PDT 24
Peak memory 224936 kb
Host smart-f63660da-d695-4b59-a889-45cfba7fc1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222776211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4222776211
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1086397831
Short name T23
Test name
Test status
Simulation time 4273499110 ps
CPU time 7.84 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:13 PM PDT 24
Peak memory 224976 kb
Host smart-f5254eed-f6b4-432e-8067-2f699ba1f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086397831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1086397831
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3385314702
Short name T191
Test name
Test status
Simulation time 5517257769 ps
CPU time 4.95 seconds
Started Jul 31 07:37:05 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 224928 kb
Host smart-320c5d99-499a-4f4e-8db0-3abcd068af23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385314702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3385314702
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2296309071
Short name T747
Test name
Test status
Simulation time 620585532 ps
CPU time 3.74 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 219208 kb
Host smart-6a7ae0de-7b2f-4500-9783-0208861b8d95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2296309071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2296309071
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2746350773
Short name T993
Test name
Test status
Simulation time 392837631716 ps
CPU time 980.35 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:53:36 PM PDT 24
Peak memory 286668 kb
Host smart-fd6a7793-7c72-424e-8efc-38d445274439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746350773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2746350773
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.552175680
Short name T299
Test name
Test status
Simulation time 5756547498 ps
CPU time 20.88 seconds
Started Jul 31 07:37:08 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 216952 kb
Host smart-8ce6b691-5ed7-425d-929b-387c1a3d9a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552175680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.552175680
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1727771125
Short name T874
Test name
Test status
Simulation time 260362118 ps
CPU time 1.96 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 216384 kb
Host smart-2157a1c9-731c-4050-a084-288221f7174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727771125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1727771125
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3819906920
Short name T454
Test name
Test status
Simulation time 475459610 ps
CPU time 2.12 seconds
Started Jul 31 07:37:08 PM PDT 24
Finished Jul 31 07:37:10 PM PDT 24
Peak memory 216656 kb
Host smart-97ed8d6d-8988-4c7e-a4c2-870cad3d2d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819906920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3819906920
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1094746062
Short name T964
Test name
Test status
Simulation time 85275510 ps
CPU time 0.79 seconds
Started Jul 31 07:37:08 PM PDT 24
Finished Jul 31 07:37:09 PM PDT 24
Peak memory 206308 kb
Host smart-0c843990-58f4-49d1-98d4-30d59263fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094746062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1094746062
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1103265264
Short name T453
Test name
Test status
Simulation time 167842783 ps
CPU time 2.89 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:17 PM PDT 24
Peak memory 233228 kb
Host smart-654bfbbb-4271-49cc-9148-af11df2a9a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103265264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1103265264
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2802676030
Short name T736
Test name
Test status
Simulation time 14138655 ps
CPU time 0.7 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:23 PM PDT 24
Peak memory 206140 kb
Host smart-ef52e254-9a1c-44c7-8cb5-f824e357562b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802676030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2802676030
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.345352829
Short name T431
Test name
Test status
Simulation time 105933817 ps
CPU time 2.8 seconds
Started Jul 31 07:37:28 PM PDT 24
Finished Jul 31 07:37:31 PM PDT 24
Peak memory 233124 kb
Host smart-329506ee-488a-406b-800a-2dea73bc61c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345352829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.345352829
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3011835829
Short name T679
Test name
Test status
Simulation time 21299837 ps
CPU time 0.83 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:16 PM PDT 24
Peak memory 206980 kb
Host smart-814716ff-b4cd-42fc-8d77-ede6a76612cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011835829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3011835829
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3212476687
Short name T258
Test name
Test status
Simulation time 13592702061 ps
CPU time 115.78 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:39:10 PM PDT 24
Peak memory 265692 kb
Host smart-77a2c2df-f923-4e49-8fe4-d214c90d7993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212476687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3212476687
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.595937417
Short name T734
Test name
Test status
Simulation time 7948206000 ps
CPU time 30.35 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 241412 kb
Host smart-5298be75-0248-4064-9d83-77bb59aa7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595937417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.595937417
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.410630586
Short name T506
Test name
Test status
Simulation time 92286112634 ps
CPU time 327.44 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:42:42 PM PDT 24
Peak memory 270668 kb
Host smart-d4e21ba6-88df-40b3-a91d-7b0743a1bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410630586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.410630586
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3284351179
Short name T40
Test name
Test status
Simulation time 89701044306 ps
CPU time 117.63 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:39:13 PM PDT 24
Peak memory 241436 kb
Host smart-965b9ee1-b2a7-4d2e-8783-c1d23f638548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284351179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3284351179
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1005650741
Short name T723
Test name
Test status
Simulation time 3582777707 ps
CPU time 8.98 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:24 PM PDT 24
Peak memory 224984 kb
Host smart-958a80bf-a9de-4ae0-a0bb-d20b98b4bdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005650741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1005650741
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.97515122
Short name T448
Test name
Test status
Simulation time 1746367225 ps
CPU time 5.05 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:19 PM PDT 24
Peak memory 224808 kb
Host smart-6563128a-3329-4436-8502-bed2eb4f32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97515122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.97515122
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.169128471
Short name T943
Test name
Test status
Simulation time 2983110967 ps
CPU time 10.79 seconds
Started Jul 31 07:37:14 PM PDT 24
Finished Jul 31 07:37:25 PM PDT 24
Peak memory 225004 kb
Host smart-b8a09343-644d-4711-a449-17f70834d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169128471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.169128471
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4169245567
Short name T196
Test name
Test status
Simulation time 928681160 ps
CPU time 4.7 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:20 PM PDT 24
Peak memory 224768 kb
Host smart-07242306-0c3d-4365-a51f-3bd1285e79c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169245567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4169245567
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1959420556
Short name T743
Test name
Test status
Simulation time 643889248 ps
CPU time 4.95 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:20 PM PDT 24
Peak memory 219548 kb
Host smart-d88a97fd-749e-4507-8c9e-4ad95cc61caa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1959420556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1959420556
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.582962906
Short name T7
Test name
Test status
Simulation time 19476005847 ps
CPU time 72.26 seconds
Started Jul 31 07:37:16 PM PDT 24
Finished Jul 31 07:38:28 PM PDT 24
Peak memory 249668 kb
Host smart-a10b0c3b-0224-42dc-ad58-6dab7a1e7bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582962906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.582962906
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1631636244
Short name T581
Test name
Test status
Simulation time 160957775 ps
CPU time 2.5 seconds
Started Jul 31 07:37:16 PM PDT 24
Finished Jul 31 07:37:18 PM PDT 24
Peak memory 216740 kb
Host smart-781db756-d81b-4d7d-9d93-4e22a42561c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631636244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1631636244
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.667075245
Short name T882
Test name
Test status
Simulation time 786970175 ps
CPU time 5.93 seconds
Started Jul 31 07:37:16 PM PDT 24
Finished Jul 31 07:37:22 PM PDT 24
Peak memory 216756 kb
Host smart-94f7615a-80ee-4b73-9f72-ac93712462c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667075245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.667075245
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3780074013
Short name T511
Test name
Test status
Simulation time 491425071 ps
CPU time 5.88 seconds
Started Jul 31 07:37:16 PM PDT 24
Finished Jul 31 07:37:22 PM PDT 24
Peak memory 216688 kb
Host smart-d7f199d4-1ac0-4015-9416-0fa9a059a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780074013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3780074013
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.959357893
Short name T873
Test name
Test status
Simulation time 96282982 ps
CPU time 0.8 seconds
Started Jul 31 07:37:16 PM PDT 24
Finished Jul 31 07:37:16 PM PDT 24
Peak memory 206352 kb
Host smart-151784b5-0051-4d07-850a-0224848a09b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959357893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.959357893
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2254753177
Short name T504
Test name
Test status
Simulation time 130987795 ps
CPU time 2.32 seconds
Started Jul 31 07:37:15 PM PDT 24
Finished Jul 31 07:37:17 PM PDT 24
Peak memory 224612 kb
Host smart-c8ef32eb-604e-46c2-a062-7ea7b646bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254753177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2254753177
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.211987384
Short name T611
Test name
Test status
Simulation time 12947395 ps
CPU time 0.7 seconds
Started Jul 31 07:37:21 PM PDT 24
Finished Jul 31 07:37:22 PM PDT 24
Peak memory 205180 kb
Host smart-70f80b5e-b99d-462b-8fd5-e4928484a189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211987384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.211987384
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.327911809
Short name T559
Test name
Test status
Simulation time 1077142947 ps
CPU time 4 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:27 PM PDT 24
Peak memory 224880 kb
Host smart-c9e89206-067b-46c7-a6ef-4b15750a0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327911809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.327911809
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2913544332
Short name T83
Test name
Test status
Simulation time 42416996 ps
CPU time 0.75 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:25 PM PDT 24
Peak memory 206924 kb
Host smart-eddd1a86-553c-4453-879d-a1f3a93f4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913544332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2913544332
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2270380619
Short name T680
Test name
Test status
Simulation time 11581755420 ps
CPU time 79.24 seconds
Started Jul 31 07:37:26 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 254936 kb
Host smart-e3daf6a5-df43-4399-ab35-688ef3422f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270380619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2270380619
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1750348767
Short name T664
Test name
Test status
Simulation time 59001594404 ps
CPU time 55.22 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:38:18 PM PDT 24
Peak memory 233260 kb
Host smart-d6d9610f-cb01-4d6c-b400-1a572dbe7293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750348767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1750348767
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.501628399
Short name T84
Test name
Test status
Simulation time 20192481991 ps
CPU time 218.81 seconds
Started Jul 31 07:37:22 PM PDT 24
Finished Jul 31 07:41:01 PM PDT 24
Peak memory 257612 kb
Host smart-59f9317b-5a10-4c80-8c9e-3f074c9d7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501628399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.501628399
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3001360998
Short name T147
Test name
Test status
Simulation time 4936858591 ps
CPU time 21.07 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:46 PM PDT 24
Peak memory 233220 kb
Host smart-5686b7c9-8b11-4a39-900d-f01ab6eef074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001360998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3001360998
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1883748055
Short name T97
Test name
Test status
Simulation time 112665963971 ps
CPU time 169.94 seconds
Started Jul 31 07:37:26 PM PDT 24
Finished Jul 31 07:40:16 PM PDT 24
Peak memory 257848 kb
Host smart-cf1a57fb-e769-4982-bea8-c6178705c678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883748055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1883748055
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.818218229
Short name T474
Test name
Test status
Simulation time 127178413 ps
CPU time 3.27 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:28 PM PDT 24
Peak memory 233172 kb
Host smart-c4aab4d8-9526-49fb-abeb-eae641041b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818218229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.818218229
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2484145522
Short name T929
Test name
Test status
Simulation time 2802959385 ps
CPU time 29.61 seconds
Started Jul 31 07:37:21 PM PDT 24
Finished Jul 31 07:37:51 PM PDT 24
Peak memory 224976 kb
Host smart-90d1dec5-6871-4a81-8dc9-6db5b90ec79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484145522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2484145522
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3444739399
Short name T912
Test name
Test status
Simulation time 135524313 ps
CPU time 2.42 seconds
Started Jul 31 07:37:21 PM PDT 24
Finished Jul 31 07:37:24 PM PDT 24
Peak memory 232844 kb
Host smart-3285a486-bcec-4493-af9c-2d89d165a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444739399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3444739399
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3685047123
Short name T553
Test name
Test status
Simulation time 264312145 ps
CPU time 5.39 seconds
Started Jul 31 07:37:26 PM PDT 24
Finished Jul 31 07:37:31 PM PDT 24
Peak memory 233120 kb
Host smart-ba7817ca-23df-495c-9ea1-5051d542b724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685047123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3685047123
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2022305353
Short name T877
Test name
Test status
Simulation time 5372896156 ps
CPU time 10.2 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 219204 kb
Host smart-5aacc681-d33c-4861-b279-a06d32ddaefb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022305353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2022305353
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3636741261
Short name T541
Test name
Test status
Simulation time 67828789 ps
CPU time 1.15 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:26 PM PDT 24
Peak memory 207568 kb
Host smart-8ff90e74-751f-4eec-b22f-662b661a6a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636741261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3636741261
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2550863176
Short name T544
Test name
Test status
Simulation time 36494236464 ps
CPU time 46.65 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:38:12 PM PDT 24
Peak memory 216688 kb
Host smart-85cdbed1-ab90-46f5-89b0-868481f7163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550863176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2550863176
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2545228733
Short name T466
Test name
Test status
Simulation time 12879867850 ps
CPU time 10.99 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 216672 kb
Host smart-8b5dd9f2-6499-42d3-9fb4-5cbd92541d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545228733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2545228733
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2205439857
Short name T843
Test name
Test status
Simulation time 140714992 ps
CPU time 2.56 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:34 PM PDT 24
Peak memory 216768 kb
Host smart-8a9e539d-21b5-439f-9357-20902fa3ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205439857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2205439857
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3063248986
Short name T909
Test name
Test status
Simulation time 168745131 ps
CPU time 0.91 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 206384 kb
Host smart-68b5a40d-ee50-4f65-a991-2795de63f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063248986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3063248986
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3931053324
Short name T234
Test name
Test status
Simulation time 3243736830 ps
CPU time 13.59 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:37 PM PDT 24
Peak memory 233176 kb
Host smart-f9340ace-b10d-4da3-913d-07cfc1ea3a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931053324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3931053324
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2534934034
Short name T706
Test name
Test status
Simulation time 21262326 ps
CPU time 0.7 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:26 PM PDT 24
Peak memory 205772 kb
Host smart-3be3d8bd-60bf-42c1-af26-fb759cb46fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534934034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2534934034
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2952663096
Short name T493
Test name
Test status
Simulation time 2870475670 ps
CPU time 6.98 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:32 PM PDT 24
Peak memory 225016 kb
Host smart-a356bab2-07f8-4b2f-9a44-38bc3e700a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952663096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2952663096
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3526398833
Short name T464
Test name
Test status
Simulation time 156498988 ps
CPU time 0.75 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:24 PM PDT 24
Peak memory 205984 kb
Host smart-27e6172a-4968-4ed1-a62e-0e1113764534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526398833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3526398833
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.462136720
Short name T997
Test name
Test status
Simulation time 2947461732 ps
CPU time 34.28 seconds
Started Jul 31 07:37:26 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 252480 kb
Host smart-eac62470-befd-4c13-b432-d579b26d1825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462136720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.462136720
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.548455215
Short name T867
Test name
Test status
Simulation time 4748478947 ps
CPU time 51.12 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 249664 kb
Host smart-4d5cc277-32f4-4c5f-a666-c8fd95cae96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548455215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.548455215
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2614267135
Short name T301
Test name
Test status
Simulation time 10098967988 ps
CPU time 75.35 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 257700 kb
Host smart-911a655a-3d8d-45b7-8a6e-10db867c823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614267135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2614267135
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.248612591
Short name T292
Test name
Test status
Simulation time 4027923469 ps
CPU time 22.09 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:53 PM PDT 24
Peak memory 225072 kb
Host smart-180043c6-9a26-40f3-bbbe-cd97389ab47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248612591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.248612591
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1896088756
Short name T546
Test name
Test status
Simulation time 23921122955 ps
CPU time 40.85 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 239884 kb
Host smart-56285c8f-b703-4b35-9652-25a7c6962a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896088756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1896088756
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3595595944
Short name T205
Test name
Test status
Simulation time 1983631759 ps
CPU time 16.45 seconds
Started Jul 31 07:37:19 PM PDT 24
Finished Jul 31 07:37:36 PM PDT 24
Peak memory 233076 kb
Host smart-9a277937-07db-4ee1-981b-4d302dd328b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595595944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3595595944
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.565637549
Short name T442
Test name
Test status
Simulation time 2113223391 ps
CPU time 5.3 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:29 PM PDT 24
Peak memory 233136 kb
Host smart-48f285ff-b765-4d29-851a-6407e3a0197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565637549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.565637549
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1063929286
Short name T933
Test name
Test status
Simulation time 4008513629 ps
CPU time 5.41 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:31 PM PDT 24
Peak memory 224928 kb
Host smart-eb5d2fb4-4d52-4536-b42d-6c475d4a3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063929286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1063929286
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1207411641
Short name T789
Test name
Test status
Simulation time 3642656360 ps
CPU time 7.56 seconds
Started Jul 31 07:37:23 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 233176 kb
Host smart-1d02c1ed-c955-4498-8e3d-88074ecd1c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207411641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1207411641
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4044811595
Short name T332
Test name
Test status
Simulation time 128503235 ps
CPU time 3.46 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:28 PM PDT 24
Peak memory 219372 kb
Host smart-fb64639a-ee93-4ac6-afb8-296e8f3d0b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044811595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4044811595
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2820124870
Short name T1005
Test name
Test status
Simulation time 101254964 ps
CPU time 1.03 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:27 PM PDT 24
Peak memory 207556 kb
Host smart-34b46425-e86f-4faf-9827-f468227a2459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820124870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2820124870
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.898718945
Short name T545
Test name
Test status
Simulation time 561552157 ps
CPU time 5.29 seconds
Started Jul 31 07:37:25 PM PDT 24
Finished Jul 31 07:37:30 PM PDT 24
Peak memory 216672 kb
Host smart-09175d8e-b72f-47bd-b156-c4077946c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898718945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.898718945
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3240686046
Short name T515
Test name
Test status
Simulation time 4448001048 ps
CPU time 13.1 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:37 PM PDT 24
Peak memory 216616 kb
Host smart-16fa565c-4d83-4552-82d4-88abb7dcc0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240686046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3240686046
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.646900767
Short name T29
Test name
Test status
Simulation time 105499909 ps
CPU time 1.05 seconds
Started Jul 31 07:37:22 PM PDT 24
Finished Jul 31 07:37:24 PM PDT 24
Peak memory 208236 kb
Host smart-6e76c20d-2aa0-4612-889f-2d92c883fe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646900767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.646900767
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4098147082
Short name T660
Test name
Test status
Simulation time 101579727 ps
CPU time 0.87 seconds
Started Jul 31 07:37:24 PM PDT 24
Finished Jul 31 07:37:26 PM PDT 24
Peak memory 206428 kb
Host smart-1873d3ce-3f91-4372-9db4-b35e49c01413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098147082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4098147082
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.223616507
Short name T554
Test name
Test status
Simulation time 390646542 ps
CPU time 4.29 seconds
Started Jul 31 07:37:22 PM PDT 24
Finished Jul 31 07:37:27 PM PDT 24
Peak memory 233080 kb
Host smart-33e066f0-18a0-4cf3-a36a-3773c74f94f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223616507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.223616507
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.870657351
Short name T953
Test name
Test status
Simulation time 26324267 ps
CPU time 0.71 seconds
Started Jul 31 07:37:33 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 206188 kb
Host smart-dc78df4c-8f33-4a1c-8fc7-2d7c103b9acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870657351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.870657351
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3235233815
Short name T984
Test name
Test status
Simulation time 88341738 ps
CPU time 2.31 seconds
Started Jul 31 07:37:35 PM PDT 24
Finished Jul 31 07:37:38 PM PDT 24
Peak memory 224868 kb
Host smart-ced22de7-adb6-4dc9-96f5-5fd2f77bd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235233815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3235233815
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.545245951
Short name T838
Test name
Test status
Simulation time 53368166 ps
CPU time 0.75 seconds
Started Jul 31 07:37:34 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 205976 kb
Host smart-cdcd37a4-a4ab-4d3d-96b0-61c5c298ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545245951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.545245951
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2788430303
Short name T589
Test name
Test status
Simulation time 7416704501 ps
CPU time 29.08 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:38:01 PM PDT 24
Peak memory 241536 kb
Host smart-5a62f301-5b9a-4c9a-88d2-9f9e4b2fd425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788430303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2788430303
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3196041028
Short name T479
Test name
Test status
Simulation time 18508957341 ps
CPU time 157.01 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:40:07 PM PDT 24
Peak memory 254220 kb
Host smart-fb10fa00-9616-4105-b04e-1c3caa922bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196041028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3196041028
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3911081406
Short name T900
Test name
Test status
Simulation time 27369101013 ps
CPU time 237.29 seconds
Started Jul 31 07:37:33 PM PDT 24
Finished Jul 31 07:41:30 PM PDT 24
Peak memory 254316 kb
Host smart-9b460a1d-1b4e-4fd5-9e91-80ff4ee878e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911081406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3911081406
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2610543489
Short name T896
Test name
Test status
Simulation time 3347709315 ps
CPU time 39.01 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:38:10 PM PDT 24
Peak memory 225004 kb
Host smart-07665dec-7a67-4630-82cc-7c439bff4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610543489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2610543489
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2535943380
Short name T855
Test name
Test status
Simulation time 86116189289 ps
CPU time 139.5 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:39:56 PM PDT 24
Peak memory 238928 kb
Host smart-8aea77b7-3561-4dc7-8938-d58535ed382b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535943380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2535943380
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2076450608
Short name T94
Test name
Test status
Simulation time 937857452 ps
CPU time 3.84 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:37:40 PM PDT 24
Peak memory 224880 kb
Host smart-bd11d6a6-d546-4e1b-977f-bf067d3c71df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076450608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2076450608
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.96681947
Short name T70
Test name
Test status
Simulation time 8056599543 ps
CPU time 24.59 seconds
Started Jul 31 07:37:37 PM PDT 24
Finished Jul 31 07:38:02 PM PDT 24
Peak memory 224964 kb
Host smart-4f35853b-ccc2-4c33-a1ca-f7c23da394bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96681947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.96681947
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1940391575
Short name T254
Test name
Test status
Simulation time 2691259339 ps
CPU time 9.79 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 233196 kb
Host smart-5a2a4216-d82f-4c27-83df-d2f2eaa89ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940391575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1940391575
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4182294281
Short name T922
Test name
Test status
Simulation time 411013837 ps
CPU time 4.58 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 224852 kb
Host smart-0ddb8756-8b0e-4c79-b90d-590234a398b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182294281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4182294281
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1573335427
Short name T977
Test name
Test status
Simulation time 135975416 ps
CPU time 3.89 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:37:36 PM PDT 24
Peak memory 220840 kb
Host smart-518fd703-520b-4389-8556-a5bdc4629273
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573335427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1573335427
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.392110693
Short name T590
Test name
Test status
Simulation time 114231203608 ps
CPU time 511.53 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:46:04 PM PDT 24
Peak memory 264536 kb
Host smart-f6e333be-0b91-4795-bb46-dec3e5e39edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392110693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.392110693
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.965425253
Short name T308
Test name
Test status
Simulation time 26877284271 ps
CPU time 36.91 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 216724 kb
Host smart-f4c29831-10f4-4bb7-a46f-983bf044d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965425253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.965425253
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1756930404
Short name T966
Test name
Test status
Simulation time 192539416 ps
CPU time 1.15 seconds
Started Jul 31 07:37:37 PM PDT 24
Finished Jul 31 07:37:39 PM PDT 24
Peak memory 208208 kb
Host smart-c680d5dd-3df4-4a16-8ebf-98ace585c2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756930404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1756930404
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1864233369
Short name T870
Test name
Test status
Simulation time 151239634 ps
CPU time 1.62 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 216640 kb
Host smart-8acb33cb-b3a5-4e72-a828-b3a8c1963beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864233369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1864233369
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2860633612
Short name T710
Test name
Test status
Simulation time 221077880 ps
CPU time 0.89 seconds
Started Jul 31 07:37:34 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 206320 kb
Host smart-e627ce7e-a135-48fb-9a15-3659179719ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860633612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2860633612
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3116268905
Short name T584
Test name
Test status
Simulation time 2937040666 ps
CPU time 6.01 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 224992 kb
Host smart-91718db7-7343-4bcc-959f-f400f09f6f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116268905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3116268905
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3466310663
Short name T323
Test name
Test status
Simulation time 13457734 ps
CPU time 0.7 seconds
Started Jul 31 07:37:34 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 206212 kb
Host smart-c0f3df6d-c36a-4555-977a-8f0ff0395c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466310663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3466310663
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1654701655
Short name T996
Test name
Test status
Simulation time 929851474 ps
CPU time 6.68 seconds
Started Jul 31 07:37:37 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 224896 kb
Host smart-f96f9c6e-2741-4d6b-bd0f-5d3c2b13a08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654701655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1654701655
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1514302134
Short name T610
Test name
Test status
Simulation time 52543025 ps
CPU time 0.79 seconds
Started Jul 31 07:37:34 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 206972 kb
Host smart-adf81aff-9436-4e33-ba00-917becce2e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514302134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1514302134
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4074498906
Short name T266
Test name
Test status
Simulation time 276432458222 ps
CPU time 493.01 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:45:46 PM PDT 24
Peak memory 249688 kb
Host smart-0ecdc2b8-236b-42d7-aab7-56ccafb2f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074498906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4074498906
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3284466228
Short name T282
Test name
Test status
Simulation time 143640171373 ps
CPU time 659.77 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:48:31 PM PDT 24
Peak memory 265972 kb
Host smart-0a305b7b-b477-4757-a166-89721f868a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284466228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3284466228
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2009676341
Short name T947
Test name
Test status
Simulation time 16935875013 ps
CPU time 64.81 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 250652 kb
Host smart-c63d7804-5668-43fa-8b74-56f0f4ec29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009676341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2009676341
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1383023228
Short name T674
Test name
Test status
Simulation time 65990115 ps
CPU time 2.6 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 233048 kb
Host smart-18b7bd90-257a-4c5c-b779-73b4d8cba11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383023228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1383023228
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4171912431
Short name T184
Test name
Test status
Simulation time 26923816050 ps
CPU time 186.86 seconds
Started Jul 31 07:37:32 PM PDT 24
Finished Jul 31 07:40:39 PM PDT 24
Peak memory 254740 kb
Host smart-cf3d682d-c243-4a2a-b8c8-44d3dbe2d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171912431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4171912431
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.724511306
Short name T51
Test name
Test status
Simulation time 284589442 ps
CPU time 3.77 seconds
Started Jul 31 07:37:29 PM PDT 24
Finished Jul 31 07:37:33 PM PDT 24
Peak memory 224876 kb
Host smart-99cff8a2-d9aa-4957-8f61-cd9ed3c8eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724511306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.724511306
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1813714906
Short name T98
Test name
Test status
Simulation time 11204443908 ps
CPU time 54.83 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:38:31 PM PDT 24
Peak memory 233128 kb
Host smart-5fcd88e8-5fa6-4d85-98f9-5af83fde8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813714906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1813714906
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2036137968
Short name T462
Test name
Test status
Simulation time 23124572609 ps
CPU time 10.76 seconds
Started Jul 31 07:37:33 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 224952 kb
Host smart-a31c484d-75b6-4b55-9889-8a92918ce87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036137968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2036137968
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.958912054
Short name T657
Test name
Test status
Simulation time 30639652283 ps
CPU time 8.95 seconds
Started Jul 31 07:37:33 PM PDT 24
Finished Jul 31 07:37:42 PM PDT 24
Peak memory 233176 kb
Host smart-9726e11d-0c50-42e2-bdea-b7c2167689ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958912054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.958912054
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2244358790
Short name T43
Test name
Test status
Simulation time 3013963467 ps
CPU time 7.69 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 219592 kb
Host smart-b320cbee-3cff-4b25-bedc-9fd76fbc3c9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244358790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2244358790
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3562896784
Short name T876
Test name
Test status
Simulation time 2851053402 ps
CPU time 20.72 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 233248 kb
Host smart-d4909b24-e4fb-49e0-8505-99826622dd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562896784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3562896784
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3788028975
Short name T956
Test name
Test status
Simulation time 13179283345 ps
CPU time 37.44 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:38:08 PM PDT 24
Peak memory 216724 kb
Host smart-2fe1be82-9e06-41fb-80d0-547c263d0e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788028975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3788028975
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.218214530
Short name T481
Test name
Test status
Simulation time 1926490798 ps
CPU time 5.11 seconds
Started Jul 31 07:37:30 PM PDT 24
Finished Jul 31 07:37:35 PM PDT 24
Peak memory 216592 kb
Host smart-4db4a08c-35f9-4866-9fa4-d8e6413a572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218214530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.218214530
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1398577549
Short name T566
Test name
Test status
Simulation time 37203788 ps
CPU time 1.18 seconds
Started Jul 31 07:37:35 PM PDT 24
Finished Jul 31 07:37:37 PM PDT 24
Peak memory 216692 kb
Host smart-edeed654-dafa-4d9c-91a9-8536ae9a04f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398577549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1398577549
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4078323868
Short name T998
Test name
Test status
Simulation time 40711236 ps
CPU time 0.83 seconds
Started Jul 31 07:37:39 PM PDT 24
Finished Jul 31 07:37:40 PM PDT 24
Peak memory 206300 kb
Host smart-87bca0f3-c12a-4b3a-9679-13a88d3377de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078323868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4078323868
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2283546122
Short name T439
Test name
Test status
Simulation time 11851609957 ps
CPU time 27.34 seconds
Started Jul 31 07:37:31 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 240200 kb
Host smart-402566fc-6059-459d-8ee1-32842113975c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283546122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2283546122
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.66007685
Short name T562
Test name
Test status
Simulation time 14453417 ps
CPU time 0.74 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 206180 kb
Host smart-12573a7a-b254-4236-8398-cc3fda455a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66007685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.66007685
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.466627452
Short name T361
Test name
Test status
Simulation time 2016835133 ps
CPU time 18.91 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 233060 kb
Host smart-509295e9-c3ad-472d-8211-c896e572918f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466627452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.466627452
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2900588556
Short name T847
Test name
Test status
Simulation time 15135657 ps
CPU time 0.75 seconds
Started Jul 31 07:37:37 PM PDT 24
Finished Jul 31 07:37:38 PM PDT 24
Peak memory 206312 kb
Host smart-fb0fdb11-d7bc-4b20-8f24-9c4773d6c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900588556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2900588556
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4234555481
Short name T792
Test name
Test status
Simulation time 23472716219 ps
CPU time 50.34 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:38:29 PM PDT 24
Peak memory 254120 kb
Host smart-e068208e-5ac7-4932-9371-ee176b3ab016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234555481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4234555481
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3628705063
Short name T536
Test name
Test status
Simulation time 50145840053 ps
CPU time 56.56 seconds
Started Jul 31 07:37:39 PM PDT 24
Finished Jul 31 07:38:36 PM PDT 24
Peak memory 224624 kb
Host smart-4acf602e-a975-43cf-92d5-ed56cb2400d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628705063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3628705063
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.76162996
Short name T518
Test name
Test status
Simulation time 149403292 ps
CPU time 3.18 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 224928 kb
Host smart-6f6c9900-c8d4-4711-89d6-510fb60ec63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76162996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.76162996
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1472040001
Short name T220
Test name
Test status
Simulation time 59911070481 ps
CPU time 146.71 seconds
Started Jul 31 07:37:39 PM PDT 24
Finished Jul 31 07:40:05 PM PDT 24
Peak memory 257748 kb
Host smart-28fc3f19-c88f-4756-b0d4-b9319b345cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472040001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1472040001
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1875279932
Short name T41
Test name
Test status
Simulation time 1852084055 ps
CPU time 17.57 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:58 PM PDT 24
Peak memory 224880 kb
Host smart-71d7eda4-73a1-4348-a304-1880dcfca2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875279932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1875279932
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4237574906
Short name T201
Test name
Test status
Simulation time 3498366679 ps
CPU time 18.39 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 233096 kb
Host smart-dee49289-5f59-4cfb-ac82-ded7d13cfc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237574906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4237574906
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4244954807
Short name T501
Test name
Test status
Simulation time 8203265918 ps
CPU time 15.75 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:37:57 PM PDT 24
Peak memory 224824 kb
Host smart-a64b5c86-76f3-45f6-9b73-17819abdd245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244954807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4244954807
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1218330120
Short name T499
Test name
Test status
Simulation time 1228961235 ps
CPU time 3.89 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 233108 kb
Host smart-18eeb181-bc01-4cb7-8ad3-9f293d3a27df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218330120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1218330120
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3446949410
Short name T752
Test name
Test status
Simulation time 763365360 ps
CPU time 10.25 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:37:51 PM PDT 24
Peak memory 222160 kb
Host smart-b168bc9f-55bc-43c9-8e32-430b0e677244
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3446949410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3446949410
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.254953205
Short name T136
Test name
Test status
Simulation time 145611998834 ps
CPU time 429 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:44:47 PM PDT 24
Peak memory 281476 kb
Host smart-bec90286-e7a4-430c-b97b-a6a174f261d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254953205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.254953205
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3179423547
Short name T318
Test name
Test status
Simulation time 4280179636 ps
CPU time 17.11 seconds
Started Jul 31 07:37:36 PM PDT 24
Finished Jul 31 07:37:53 PM PDT 24
Peak memory 216652 kb
Host smart-00c0ae9c-cdcc-4bc2-a306-2d8f468fdfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179423547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3179423547
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1686326629
Short name T324
Test name
Test status
Simulation time 62772360 ps
CPU time 0.7 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:37:39 PM PDT 24
Peak memory 206056 kb
Host smart-bd863861-a3a2-4f7c-8114-2490173009ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686326629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1686326629
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2417512422
Short name T582
Test name
Test status
Simulation time 220515317 ps
CPU time 1.75 seconds
Started Jul 31 07:37:43 PM PDT 24
Finished Jul 31 07:37:45 PM PDT 24
Peak memory 216572 kb
Host smart-8e02eec7-d09c-4133-9949-f2be880eaaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417512422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2417512422
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.190151374
Short name T414
Test name
Test status
Simulation time 54502021 ps
CPU time 0.85 seconds
Started Jul 31 07:37:38 PM PDT 24
Finished Jul 31 07:37:39 PM PDT 24
Peak memory 206320 kb
Host smart-a312f2e8-0b63-474d-8b1f-d976ee9b19d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190151374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.190151374
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1330159940
Short name T172
Test name
Test status
Simulation time 7478602520 ps
CPU time 25.36 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 239900 kb
Host smart-ed4dade3-9e39-4166-890b-d697346e6e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330159940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1330159940
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3531076933
Short name T449
Test name
Test status
Simulation time 21369532 ps
CPU time 0.77 seconds
Started Jul 31 07:37:47 PM PDT 24
Finished Jul 31 07:37:48 PM PDT 24
Peak memory 205808 kb
Host smart-c582f020-a880-43de-96e1-ff372dd28ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531076933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3531076933
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4071576137
Short name T399
Test name
Test status
Simulation time 227341831 ps
CPU time 2.75 seconds
Started Jul 31 07:37:46 PM PDT 24
Finished Jul 31 07:37:49 PM PDT 24
Peak memory 224972 kb
Host smart-75da571d-0dfa-47be-bb62-8dcf4c041937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071576137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4071576137
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4258322839
Short name T354
Test name
Test status
Simulation time 55900017 ps
CPU time 0.76 seconds
Started Jul 31 07:37:42 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 207012 kb
Host smart-48f02899-f900-4732-b772-392d5da6c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258322839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4258322839
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3332950244
Short name T447
Test name
Test status
Simulation time 34774831402 ps
CPU time 128.29 seconds
Started Jul 31 07:37:46 PM PDT 24
Finished Jul 31 07:39:55 PM PDT 24
Peak memory 250688 kb
Host smart-f1c22b0c-21a3-4803-89e5-b6c2ce2b1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332950244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3332950244
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3617538378
Short name T731
Test name
Test status
Simulation time 931347823 ps
CPU time 8.55 seconds
Started Jul 31 07:37:47 PM PDT 24
Finished Jul 31 07:37:56 PM PDT 24
Peak memory 234624 kb
Host smart-1bc53643-73b4-4802-be83-5700a84c32f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617538378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3617538378
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.784289322
Short name T765
Test name
Test status
Simulation time 198308847 ps
CPU time 5.1 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:45 PM PDT 24
Peak memory 224928 kb
Host smart-fcf6abf0-f64c-41f1-b951-73162ba5c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784289322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.784289322
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3812005786
Short name T192
Test name
Test status
Simulation time 7075836576 ps
CPU time 16.45 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:56 PM PDT 24
Peak memory 235832 kb
Host smart-3ed62dc9-dfec-4542-bea3-8184d968429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812005786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3812005786
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2199816935
Short name T668
Test name
Test status
Simulation time 4167313161 ps
CPU time 22.72 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:38:02 PM PDT 24
Peak memory 224936 kb
Host smart-41693c06-7266-493b-8bd1-ef9f21b08f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199816935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2199816935
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.379983275
Short name T934
Test name
Test status
Simulation time 35414429 ps
CPU time 2.62 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:43 PM PDT 24
Peak memory 232820 kb
Host smart-e06f0271-4834-4d5d-8097-c0d04d188ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379983275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.379983275
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2722389523
Short name T244
Test name
Test status
Simulation time 13769712795 ps
CPU time 38.28 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:38:19 PM PDT 24
Peak memory 233216 kb
Host smart-7c4ebfcb-71b5-4083-b17e-9e3ced23d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722389523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2722389523
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3698039868
Short name T713
Test name
Test status
Simulation time 114179820 ps
CPU time 2.13 seconds
Started Jul 31 07:37:39 PM PDT 24
Finished Jul 31 07:37:42 PM PDT 24
Peak memory 232812 kb
Host smart-55b9c7ac-ee0a-4a69-9585-421e84d364f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698039868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3698039868
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1622472787
Short name T492
Test name
Test status
Simulation time 3274864270 ps
CPU time 12.89 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:37:54 PM PDT 24
Peak memory 220744 kb
Host smart-e7e55b2a-e361-4f00-85bb-d79a0080da65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622472787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1622472787
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4121398971
Short name T188
Test name
Test status
Simulation time 8541604191 ps
CPU time 72.96 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:39:01 PM PDT 24
Peak memory 252496 kb
Host smart-22d52266-0203-44cd-b0ab-98f52108908b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121398971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4121398971
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.524466860
Short name T994
Test name
Test status
Simulation time 13830755668 ps
CPU time 17.43 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 220384 kb
Host smart-1b15004c-7e44-4773-86d9-1f778a1c4c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524466860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.524466860
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1246265709
Short name T729
Test name
Test status
Simulation time 18440633427 ps
CPU time 13.53 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:37:54 PM PDT 24
Peak memory 216992 kb
Host smart-84bae9d9-36cb-4003-8f8a-6937a752397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246265709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1246265709
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2405225635
Short name T837
Test name
Test status
Simulation time 49289647 ps
CPU time 0.76 seconds
Started Jul 31 07:37:40 PM PDT 24
Finished Jul 31 07:37:41 PM PDT 24
Peak memory 206288 kb
Host smart-9b59dd7a-ac6b-4cb1-8756-03e6dd666f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405225635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2405225635
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1933362389
Short name T761
Test name
Test status
Simulation time 33678153 ps
CPU time 0.91 seconds
Started Jul 31 07:37:43 PM PDT 24
Finished Jul 31 07:37:44 PM PDT 24
Peak memory 206296 kb
Host smart-4d3ccab9-0274-4f26-9450-eed8e504b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933362389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1933362389
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.864064962
Short name T233
Test name
Test status
Simulation time 21766613970 ps
CPU time 18.43 seconds
Started Jul 31 07:37:41 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 233064 kb
Host smart-e82197f3-3d1a-4151-b3ee-e481c59ed95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864064962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.864064962
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1812409467
Short name T72
Test name
Test status
Simulation time 23437082 ps
CPU time 0.73 seconds
Started Jul 31 07:37:59 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 205856 kb
Host smart-498aef84-906c-4381-868b-9c6e8f6a2478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812409467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1812409467
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2970010265
Short name T226
Test name
Test status
Simulation time 557051502 ps
CPU time 5.22 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:37:53 PM PDT 24
Peak memory 233056 kb
Host smart-112055da-2983-4780-b046-906a647244c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970010265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2970010265
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4047799597
Short name T613
Test name
Test status
Simulation time 49008150 ps
CPU time 0.8 seconds
Started Jul 31 07:37:50 PM PDT 24
Finished Jul 31 07:37:51 PM PDT 24
Peak memory 206992 kb
Host smart-7c38a0e2-505d-49bc-8c3a-853648ae1ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047799597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4047799597
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3936446109
Short name T66
Test name
Test status
Simulation time 47174737833 ps
CPU time 59.86 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:38:49 PM PDT 24
Peak memory 233040 kb
Host smart-1ff69058-c3f8-4f2a-9e9a-7692443dd7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936446109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3936446109
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.591026650
Short name T755
Test name
Test status
Simulation time 37496972486 ps
CPU time 355.12 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:43:44 PM PDT 24
Peak memory 254748 kb
Host smart-2befcce6-7509-4537-80ff-ddaeaecbb88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591026650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.591026650
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2189254749
Short name T563
Test name
Test status
Simulation time 3964617022 ps
CPU time 57.74 seconds
Started Jul 31 07:37:50 PM PDT 24
Finished Jul 31 07:38:48 PM PDT 24
Peak memory 249768 kb
Host smart-96f8d56d-73b8-4c97-b004-433d1943f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189254749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2189254749
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3840161013
Short name T677
Test name
Test status
Simulation time 3398592414 ps
CPU time 14.72 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:38:03 PM PDT 24
Peak memory 240332 kb
Host smart-75d71f9e-9540-47ce-b50d-a8b9d096e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840161013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3840161013
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1108164871
Short name T34
Test name
Test status
Simulation time 23471719189 ps
CPU time 88.4 seconds
Started Jul 31 07:37:53 PM PDT 24
Finished Jul 31 07:39:21 PM PDT 24
Peak memory 253732 kb
Host smart-84cb286b-ad4f-4c8c-be3f-38a49508cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108164871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1108164871
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1037908721
Short name T240
Test name
Test status
Simulation time 491413007 ps
CPU time 6.62 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:37:55 PM PDT 24
Peak memory 224836 kb
Host smart-d7362344-492f-4937-9fc7-179441f25361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037908721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1037908721
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1672557986
Short name T230
Test name
Test status
Simulation time 5316615707 ps
CPU time 13.6 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:38:02 PM PDT 24
Peak memory 223276 kb
Host smart-3b129ff0-2041-470f-80b0-eada358f7915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672557986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1672557986
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2231799275
Short name T600
Test name
Test status
Simulation time 167998320 ps
CPU time 2.77 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:37:52 PM PDT 24
Peak memory 233160 kb
Host smart-b3078382-ac09-4fb8-acc8-f763ff007586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231799275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2231799275
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2779978009
Short name T470
Test name
Test status
Simulation time 3601444067 ps
CPU time 14.01 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:38:03 PM PDT 24
Peak memory 233076 kb
Host smart-5be35f70-bb7f-45f2-99cd-b1c3bc3d04d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779978009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2779978009
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3890130274
Short name T846
Test name
Test status
Simulation time 166762182 ps
CPU time 3.52 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:37:53 PM PDT 24
Peak memory 223424 kb
Host smart-67eaac2a-fb12-4571-8c8c-754fffebc291
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3890130274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3890130274
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1555300221
Short name T312
Test name
Test status
Simulation time 12821699457 ps
CPU time 19.01 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:38:07 PM PDT 24
Peak memory 216636 kb
Host smart-7c8b595a-26c6-4659-9c2b-37bbad543407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555300221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1555300221
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4213865643
Short name T603
Test name
Test status
Simulation time 2715168352 ps
CPU time 9.34 seconds
Started Jul 31 07:37:52 PM PDT 24
Finished Jul 31 07:38:01 PM PDT 24
Peak memory 216716 kb
Host smart-a5daa142-3c2e-4cfd-bce6-d138bd72068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213865643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4213865643
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.21182503
Short name T490
Test name
Test status
Simulation time 1516117277 ps
CPU time 1.86 seconds
Started Jul 31 07:37:47 PM PDT 24
Finished Jul 31 07:37:49 PM PDT 24
Peak memory 216692 kb
Host smart-4a13e3a3-37fb-47ee-874a-5e88fd5c1244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21182503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.21182503
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.678460683
Short name T619
Test name
Test status
Simulation time 26574764 ps
CPU time 0.83 seconds
Started Jul 31 07:37:49 PM PDT 24
Finished Jul 31 07:37:50 PM PDT 24
Peak memory 206332 kb
Host smart-7dada161-4ec4-4f74-ad2a-f6fa6d892dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678460683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.678460683
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1582650646
Short name T521
Test name
Test status
Simulation time 5340305624 ps
CPU time 15.14 seconds
Started Jul 31 07:37:48 PM PDT 24
Finished Jul 31 07:38:03 PM PDT 24
Peak memory 224980 kb
Host smart-43ae9a65-4ad3-405c-94e7-8f83aacea2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582650646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1582650646
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1828284474
Short name T641
Test name
Test status
Simulation time 16037415 ps
CPU time 0.71 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:37:57 PM PDT 24
Peak memory 206028 kb
Host smart-a8489c79-68e2-4537-8f7d-709ec4586b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828284474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1828284474
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3277423758
Short name T725
Test name
Test status
Simulation time 173732466 ps
CPU time 2.12 seconds
Started Jul 31 07:37:54 PM PDT 24
Finished Jul 31 07:37:56 PM PDT 24
Peak memory 224408 kb
Host smart-5296b2d4-8467-404b-ab2f-c22b9d9b02d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277423758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3277423758
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2894125801
Short name T556
Test name
Test status
Simulation time 16228563 ps
CPU time 0.82 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:37:57 PM PDT 24
Peak memory 206996 kb
Host smart-e2487bf0-50a8-4a82-8f2c-99a308784470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894125801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2894125801
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1828831787
Short name T271
Test name
Test status
Simulation time 5899461077 ps
CPU time 104.48 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:39:43 PM PDT 24
Peak memory 266568 kb
Host smart-e9499922-4480-4732-9876-d1706ecbc086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828831787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1828831787
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1225378833
Short name T637
Test name
Test status
Simulation time 30511342808 ps
CPU time 33.1 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:38:30 PM PDT 24
Peak memory 217960 kb
Host smart-fda523b0-aa5a-4684-8b93-b82bdb655129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225378833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1225378833
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3665014745
Short name T813
Test name
Test status
Simulation time 3154175537 ps
CPU time 57.45 seconds
Started Jul 31 07:37:55 PM PDT 24
Finished Jul 31 07:38:52 PM PDT 24
Peak memory 249568 kb
Host smart-0b4b4109-30a4-47b2-ba26-650d2fb3f7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665014745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3665014745
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4027742433
Short name T596
Test name
Test status
Simulation time 8937352151 ps
CPU time 31.84 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:36 PM PDT 24
Peak memory 225144 kb
Host smart-4661ac80-39a4-4eb1-9e02-171ef3b40574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027742433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4027742433
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3992316387
Short name T281
Test name
Test status
Simulation time 15324957052 ps
CPU time 122.81 seconds
Started Jul 31 07:37:54 PM PDT 24
Finished Jul 31 07:39:57 PM PDT 24
Peak memory 253336 kb
Host smart-782b5d5e-3d8b-4336-ab5f-454ce5db71ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992316387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3992316387
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3067211165
Short name T427
Test name
Test status
Simulation time 1055421924 ps
CPU time 11.26 seconds
Started Jul 31 07:37:57 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 233076 kb
Host smart-b8929419-0fd5-4704-afde-ec764731fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067211165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3067211165
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.44841336
Short name T391
Test name
Test status
Simulation time 1118117385 ps
CPU time 17.37 seconds
Started Jul 31 07:37:55 PM PDT 24
Finished Jul 31 07:38:12 PM PDT 24
Peak memory 233116 kb
Host smart-9f6bad3d-41f5-4915-adf9-cebc9e0aa417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44841336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.44841336
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.842547379
Short name T926
Test name
Test status
Simulation time 7992921120 ps
CPU time 13.74 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:38:10 PM PDT 24
Peak memory 224984 kb
Host smart-8d79fda4-9680-480d-b90f-29395c915dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842547379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.842547379
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3735565728
Short name T895
Test name
Test status
Simulation time 990512603 ps
CPU time 9.32 seconds
Started Jul 31 07:37:57 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 233020 kb
Host smart-fdd0029f-d981-4185-8933-39e0eaa44439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735565728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3735565728
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2529161526
Short name T457
Test name
Test status
Simulation time 7087878723 ps
CPU time 12.28 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:38:11 PM PDT 24
Peak memory 222684 kb
Host smart-e02be582-c396-4186-8c53-187892aae0b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2529161526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2529161526
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3969311520
Short name T387
Test name
Test status
Simulation time 411411572 ps
CPU time 1.06 seconds
Started Jul 31 07:37:57 PM PDT 24
Finished Jul 31 07:37:59 PM PDT 24
Peak memory 216352 kb
Host smart-a69af430-341d-4360-ab58-5333276f2242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969311520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3969311520
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3994863279
Short name T315
Test name
Test status
Simulation time 60424115400 ps
CPU time 45.06 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:38:41 PM PDT 24
Peak memory 220968 kb
Host smart-b0f87817-5bc1-4c3a-9cf4-acb9647adf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994863279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3994863279
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.698769563
Short name T746
Test name
Test status
Simulation time 1672263380 ps
CPU time 6.42 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:38:05 PM PDT 24
Peak memory 216632 kb
Host smart-f9e4288d-84aa-47d0-9426-3dd8f84c6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698769563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.698769563
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3425360628
Short name T973
Test name
Test status
Simulation time 198243360 ps
CPU time 2.74 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:38:01 PM PDT 24
Peak memory 216688 kb
Host smart-e8420df3-6fc6-4b72-9e1f-45175cf8342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425360628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3425360628
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.405714090
Short name T131
Test name
Test status
Simulation time 15653151 ps
CPU time 0.7 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:05 PM PDT 24
Peak memory 205992 kb
Host smart-55c3e1a6-7e20-4af1-a052-0b4f930faa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405714090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.405714090
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3751209746
Short name T389
Test name
Test status
Simulation time 545062607 ps
CPU time 1.96 seconds
Started Jul 31 07:37:57 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 224520 kb
Host smart-12bcd04a-fa2e-4246-9653-34c43c463e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751209746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3751209746
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2524121939
Short name T329
Test name
Test status
Simulation time 18992508 ps
CPU time 0.76 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 205812 kb
Host smart-33dbdbfb-5fd3-4a88-a88d-95ec67b40531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524121939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
524121939
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2369446667
Short name T1007
Test name
Test status
Simulation time 93205591 ps
CPU time 3.66 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 233232 kb
Host smart-9b94c9c0-b0e7-4602-a19c-33937d7c748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369446667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2369446667
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.465357568
Short name T883
Test name
Test status
Simulation time 14920969 ps
CPU time 0.73 seconds
Started Jul 31 07:35:17 PM PDT 24
Finished Jul 31 07:35:18 PM PDT 24
Peak memory 205932 kb
Host smart-d288372e-e217-479f-9ae7-cc9d958da7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465357568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.465357568
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2791643655
Short name T370
Test name
Test status
Simulation time 13387522 ps
CPU time 0.77 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:35:14 PM PDT 24
Peak memory 216220 kb
Host smart-bea91527-15ab-44f6-a651-8564689a061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791643655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2791643655
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3039695681
Short name T483
Test name
Test status
Simulation time 50460390424 ps
CPU time 201.39 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:38:37 PM PDT 24
Peak memory 250080 kb
Host smart-cb7f3e77-7965-4bdd-95bd-6b5fcba11323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039695681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3039695681
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1488229008
Short name T824
Test name
Test status
Simulation time 14898363657 ps
CPU time 106.08 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:37:01 PM PDT 24
Peak memory 257512 kb
Host smart-530b46a3-67d4-41c7-86e7-cf432130fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488229008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1488229008
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3773702938
Short name T4
Test name
Test status
Simulation time 66786093 ps
CPU time 3.11 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 233104 kb
Host smart-8d9a66c0-6aed-4a36-b2c5-813c5b995154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773702938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3773702938
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2510263001
Short name T96
Test name
Test status
Simulation time 11244847376 ps
CPU time 30.32 seconds
Started Jul 31 07:35:18 PM PDT 24
Finished Jul 31 07:35:48 PM PDT 24
Peak memory 233208 kb
Host smart-4a73dcae-e369-478b-b61a-ecdb0c0f8d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510263001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2510263001
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1415521384
Short name T588
Test name
Test status
Simulation time 1633086274 ps
CPU time 8.27 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:35:21 PM PDT 24
Peak memory 224848 kb
Host smart-e2c3c6ea-10db-4e6d-9301-2c9a22e12d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415521384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1415521384
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.439147026
Short name T245
Test name
Test status
Simulation time 14754896942 ps
CPU time 12.11 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:27 PM PDT 24
Peak memory 233072 kb
Host smart-561f3c7b-adc1-4ec6-b54e-cfe6a0f7804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439147026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
439147026
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3906362723
Short name T662
Test name
Test status
Simulation time 4768943940 ps
CPU time 4.54 seconds
Started Jul 31 07:35:12 PM PDT 24
Finished Jul 31 07:35:17 PM PDT 24
Peak memory 224920 kb
Host smart-3c0b256e-d0ae-4508-b995-ef1d927b6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906362723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3906362723
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.973846034
Short name T9
Test name
Test status
Simulation time 2463847595 ps
CPU time 9.6 seconds
Started Jul 31 07:35:18 PM PDT 24
Finished Jul 31 07:35:28 PM PDT 24
Peak memory 223536 kb
Host smart-b954ea23-ee9b-44e7-a5d9-a9a0683de444
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=973846034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.973846034
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3641660201
Short name T77
Test name
Test status
Simulation time 63149685 ps
CPU time 1.04 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 236840 kb
Host smart-b0ef314a-9727-4345-bfda-8c3c041742cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641660201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3641660201
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3921531177
Short name T577
Test name
Test status
Simulation time 158504448 ps
CPU time 1.06 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:35:18 PM PDT 24
Peak memory 207536 kb
Host smart-ee6e22b6-efb8-4b6c-be1e-be10eb990922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921531177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3921531177
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2320310565
Short name T297
Test name
Test status
Simulation time 11551010549 ps
CPU time 35.09 seconds
Started Jul 31 07:35:12 PM PDT 24
Finished Jul 31 07:35:48 PM PDT 24
Peak memory 220744 kb
Host smart-2acc8fa4-a2ad-4dde-a81a-e3bbd4f8d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320310565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2320310565
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2526756818
Short name T484
Test name
Test status
Simulation time 1240206555 ps
CPU time 7.56 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:22 PM PDT 24
Peak memory 216676 kb
Host smart-c5705d34-8758-484b-b906-794c547f1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526756818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2526756818
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3047785090
Short name T991
Test name
Test status
Simulation time 401034234 ps
CPU time 3.8 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:18 PM PDT 24
Peak memory 216556 kb
Host smart-7f730965-bb8b-4fc4-a558-a7e3a8dd9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047785090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3047785090
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2019834583
Short name T67
Test name
Test status
Simulation time 175599830 ps
CPU time 0.76 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:16 PM PDT 24
Peak memory 206340 kb
Host smart-66172159-0767-4005-92d3-30c02980ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019834583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2019834583
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2710354155
Short name T878
Test name
Test status
Simulation time 1455465380 ps
CPU time 10.8 seconds
Started Jul 31 07:35:15 PM PDT 24
Finished Jul 31 07:35:26 PM PDT 24
Peak memory 233216 kb
Host smart-7d72ef1b-9590-4157-8424-b295d6ccbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710354155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2710354155
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3313799692
Short name T331
Test name
Test status
Simulation time 12470067 ps
CPU time 0.72 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:05 PM PDT 24
Peak memory 205780 kb
Host smart-1696fb34-1039-4c23-b7af-66520e477ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313799692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3313799692
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2608501047
Short name T751
Test name
Test status
Simulation time 596204042 ps
CPU time 6.52 seconds
Started Jul 31 07:37:55 PM PDT 24
Finished Jul 31 07:38:02 PM PDT 24
Peak memory 233044 kb
Host smart-af7e5c88-ac8a-4a93-a826-4ae2a9aa5e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608501047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2608501047
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4135633632
Short name T348
Test name
Test status
Simulation time 43485297 ps
CPU time 0.81 seconds
Started Jul 31 07:37:54 PM PDT 24
Finished Jul 31 07:37:55 PM PDT 24
Peak memory 207064 kb
Host smart-db18ff23-3f9a-4c42-8e4e-a08561dc3f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135633632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4135633632
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2562626460
Short name T643
Test name
Test status
Simulation time 15593962115 ps
CPU time 76.53 seconds
Started Jul 31 07:37:59 PM PDT 24
Finished Jul 31 07:39:16 PM PDT 24
Peak memory 249588 kb
Host smart-ce9e58ba-440f-4ab4-8f94-9a94c0d4d163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562626460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2562626460
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.960703460
Short name T655
Test name
Test status
Simulation time 40030180450 ps
CPU time 302.04 seconds
Started Jul 31 07:38:09 PM PDT 24
Finished Jul 31 07:43:12 PM PDT 24
Peak memory 256540 kb
Host smart-24ea4185-4c07-430f-92eb-144db3368fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960703460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.960703460
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2156911879
Short name T37
Test name
Test status
Simulation time 54598684994 ps
CPU time 276.19 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:42:57 PM PDT 24
Peak memory 250640 kb
Host smart-6d6706d4-4b3d-44f3-974e-2adec4e68626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156911879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2156911879
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3281241904
Short name T519
Test name
Test status
Simulation time 144521121 ps
CPU time 4.46 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:38:00 PM PDT 24
Peak memory 233144 kb
Host smart-971501b4-e4c1-46a8-a5ce-51775d33682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281241904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3281241904
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3535640361
Short name T594
Test name
Test status
Simulation time 10361535758 ps
CPU time 99.69 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:39:38 PM PDT 24
Peak memory 254564 kb
Host smart-031cc218-453d-4b98-a497-07c873f0f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535640361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3535640361
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3634881731
Short name T852
Test name
Test status
Simulation time 890980844 ps
CPU time 6.33 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:38:05 PM PDT 24
Peak memory 233224 kb
Host smart-27256b6d-c7cd-4006-9a42-0c4fa065464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634881731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3634881731
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3819139091
Short name T612
Test name
Test status
Simulation time 2014760498 ps
CPU time 27.61 seconds
Started Jul 31 07:37:57 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 233092 kb
Host smart-8a97dc2b-709b-49c1-b8bc-96c3ffa55443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819139091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3819139091
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2925465434
Short name T692
Test name
Test status
Simulation time 1700498504 ps
CPU time 3.56 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:10 PM PDT 24
Peak memory 233048 kb
Host smart-5223f687-f714-4385-ab02-02b761eb88f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925465434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2925465434
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1368614367
Short name T256
Test name
Test status
Simulation time 499411683 ps
CPU time 2.23 seconds
Started Jul 31 07:37:56 PM PDT 24
Finished Jul 31 07:37:58 PM PDT 24
Peak memory 224848 kb
Host smart-ec141158-13c5-49cc-94cc-e362643fd3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368614367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1368614367
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4060760845
Short name T522
Test name
Test status
Simulation time 1421249386 ps
CPU time 9.39 seconds
Started Jul 31 07:37:58 PM PDT 24
Finished Jul 31 07:38:08 PM PDT 24
Peak memory 223548 kb
Host smart-2ddd309c-8076-439d-8af5-14fdb27945ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4060760845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4060760845
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1054460757
Short name T304
Test name
Test status
Simulation time 3896595476 ps
CPU time 15.35 seconds
Started Jul 31 07:38:00 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 220440 kb
Host smart-d466f452-6c8c-493d-8ab5-af9478acac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054460757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1054460757
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2646809973
Short name T411
Test name
Test status
Simulation time 9184920776 ps
CPU time 23.53 seconds
Started Jul 31 07:37:54 PM PDT 24
Finished Jul 31 07:38:18 PM PDT 24
Peak memory 216616 kb
Host smart-2d3a0191-ed90-4b31-af55-1e7278ae7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646809973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2646809973
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3098153188
Short name T858
Test name
Test status
Simulation time 422251307 ps
CPU time 6.14 seconds
Started Jul 31 07:37:55 PM PDT 24
Finished Jul 31 07:38:01 PM PDT 24
Peak memory 216592 kb
Host smart-f1714bb7-9a54-4eea-91bf-a712be2c0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098153188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3098153188
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3029069222
Short name T629
Test name
Test status
Simulation time 59164027 ps
CPU time 0.88 seconds
Started Jul 31 07:37:55 PM PDT 24
Finished Jul 31 07:37:56 PM PDT 24
Peak memory 206272 kb
Host smart-4912a328-9de0-4249-a0be-e3e1aa4704a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029069222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3029069222
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2847514747
Short name T730
Test name
Test status
Simulation time 39086109843 ps
CPU time 18.29 seconds
Started Jul 31 07:37:54 PM PDT 24
Finished Jul 31 07:38:13 PM PDT 24
Peak memory 224968 kb
Host smart-46bf715c-f3ab-4743-82eb-6bd5c0f0cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847514747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2847514747
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3521231933
Short name T415
Test name
Test status
Simulation time 22011551 ps
CPU time 0.7 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 205304 kb
Host smart-d7eaa163-5e52-40ad-9a41-e7bba7fec764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521231933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3521231933
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2316212928
Short name T796
Test name
Test status
Simulation time 109641069 ps
CPU time 1.96 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 224904 kb
Host smart-daed9a80-e982-44ce-8c36-e11f3c991d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316212928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2316212928
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2180244757
Short name T28
Test name
Test status
Simulation time 15587916 ps
CPU time 0.8 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:07 PM PDT 24
Peak memory 207296 kb
Host smart-607adb08-945c-4be7-8e9a-5d2b3e6b89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180244757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2180244757
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2382159058
Short name T970
Test name
Test status
Simulation time 1699126838 ps
CPU time 24.84 seconds
Started Jul 31 07:38:10 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 239664 kb
Host smart-ff00b573-1705-4a5a-b023-27f0b1183d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382159058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2382159058
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2114165941
Short name T597
Test name
Test status
Simulation time 12173155109 ps
CPU time 113.24 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:39:57 PM PDT 24
Peak memory 251704 kb
Host smart-ea44cf5d-469f-4cef-906f-00b294dfc7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114165941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2114165941
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3516565967
Short name T591
Test name
Test status
Simulation time 1010752908 ps
CPU time 12.99 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:20 PM PDT 24
Peak memory 241296 kb
Host smart-9fdb5a30-f66e-4063-9500-3fc54b9cfc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516565967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3516565967
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3837472379
Short name T881
Test name
Test status
Simulation time 3509015452 ps
CPU time 12.21 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:19 PM PDT 24
Peak memory 236132 kb
Host smart-a06dc5a2-7f7b-495c-ab7c-c59a32f4117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837472379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3837472379
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1210332415
Short name T579
Test name
Test status
Simulation time 203815988 ps
CPU time 5.12 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:12 PM PDT 24
Peak memory 233100 kb
Host smart-9ecdaece-3e2b-4379-855e-2148a5bc223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210332415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1210332415
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.686451988
Short name T549
Test name
Test status
Simulation time 1345911392 ps
CPU time 19.45 seconds
Started Jul 31 07:38:18 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 241364 kb
Host smart-e2d09fa6-ebd6-4e28-9312-38aa04f83dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686451988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.686451988
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2920968542
Short name T946
Test name
Test status
Simulation time 104297280 ps
CPU time 2.43 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:06 PM PDT 24
Peak memory 232796 kb
Host smart-1018d375-cd3a-4eb6-84c9-b4af44ede576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920968542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2920968542
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3210894129
Short name T689
Test name
Test status
Simulation time 1802831809 ps
CPU time 6.11 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:12 PM PDT 24
Peak memory 233052 kb
Host smart-24e1f471-49b6-4dfd-b82f-f418bb4f71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210894129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3210894129
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2894156438
Short name T702
Test name
Test status
Simulation time 1292011124 ps
CPU time 6.24 seconds
Started Jul 31 07:38:09 PM PDT 24
Finished Jul 31 07:38:15 PM PDT 24
Peak memory 221076 kb
Host smart-61051409-e639-46a6-854c-e74f6f0d147b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2894156438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2894156438
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3222270962
Short name T823
Test name
Test status
Simulation time 70106466594 ps
CPU time 612.21 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:48:17 PM PDT 24
Peak memory 254212 kb
Host smart-0bb6af01-f668-467a-bb21-daf288954a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222270962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3222270962
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2409673214
Short name T571
Test name
Test status
Simulation time 1717160550 ps
CPU time 25.3 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:31 PM PDT 24
Peak memory 216876 kb
Host smart-72c4ea25-59b5-4d6e-a906-04c461f1ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409673214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2409673214
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3335906172
Short name T712
Test name
Test status
Simulation time 1452898565 ps
CPU time 6.96 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:22 PM PDT 24
Peak memory 216616 kb
Host smart-6d0d5168-dc2c-4da9-bfaf-0efa1c468f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335906172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3335906172
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3898913338
Short name T671
Test name
Test status
Simulation time 314774974 ps
CPU time 1.76 seconds
Started Jul 31 07:38:05 PM PDT 24
Finished Jul 31 07:38:07 PM PDT 24
Peak memory 216692 kb
Host smart-9390d90a-49ea-40d3-8658-a2dbc9f212ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898913338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3898913338
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3178014996
Short name T727
Test name
Test status
Simulation time 24847606 ps
CPU time 0.75 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:08 PM PDT 24
Peak memory 206312 kb
Host smart-d16d4d2c-3fa4-4e7e-9ebe-b3b1d7c0d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178014996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3178014996
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3162830576
Short name T200
Test name
Test status
Simulation time 82244236 ps
CPU time 2.62 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 233144 kb
Host smart-527cc2d2-114e-4566-a2c5-e1aa05da69f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162830576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3162830576
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1673565426
Short name T585
Test name
Test status
Simulation time 18716589 ps
CPU time 0.72 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:13 PM PDT 24
Peak memory 205880 kb
Host smart-b3719236-6e9e-47d8-a64c-818384c4cdc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673565426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1673565426
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3775195974
Short name T960
Test name
Test status
Simulation time 43854139 ps
CPU time 2.75 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:07 PM PDT 24
Peak memory 233060 kb
Host smart-9e775f78-cbc2-4330-8e84-7a971555b60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775195974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3775195974
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1226312182
Short name T494
Test name
Test status
Simulation time 32319693 ps
CPU time 0.77 seconds
Started Jul 31 07:38:03 PM PDT 24
Finished Jul 31 07:38:04 PM PDT 24
Peak memory 207088 kb
Host smart-e8cbcbbc-92dc-4f80-9518-7e30717c2d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226312182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1226312182
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1976299530
Short name T691
Test name
Test status
Simulation time 141024764108 ps
CPU time 260.61 seconds
Started Jul 31 07:38:05 PM PDT 24
Finished Jul 31 07:42:26 PM PDT 24
Peak memory 249544 kb
Host smart-b6b7e66f-1e67-4250-908f-ab020a019cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976299530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1976299530
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1575264470
Short name T179
Test name
Test status
Simulation time 2140624577 ps
CPU time 28.93 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 225172 kb
Host smart-76166fca-651f-453a-802a-ea2108622bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575264470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1575264470
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3708648392
Short name T296
Test name
Test status
Simulation time 581214753 ps
CPU time 7.55 seconds
Started Jul 31 07:38:05 PM PDT 24
Finished Jul 31 07:38:13 PM PDT 24
Peak memory 249564 kb
Host smart-d8145bcd-8aad-4507-9f5f-dc6b20940ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708648392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3708648392
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1686652958
Short name T531
Test name
Test status
Simulation time 4121030223 ps
CPU time 16.18 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:23 PM PDT 24
Peak memory 252628 kb
Host smart-c63883b4-bfb8-428e-8601-51b675fa40b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686652958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1686652958
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.478511597
Short name T550
Test name
Test status
Simulation time 310852321 ps
CPU time 2.58 seconds
Started Jul 31 07:38:08 PM PDT 24
Finished Jul 31 07:38:11 PM PDT 24
Peak memory 232828 kb
Host smart-13f2ae27-3081-40c8-a579-050ef2930dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478511597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.478511597
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3666036548
Short name T1000
Test name
Test status
Simulation time 25169723755 ps
CPU time 44.39 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:51 PM PDT 24
Peak memory 233108 kb
Host smart-a63294f0-804f-40e5-a1d1-6a251c20bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666036548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3666036548
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1314263907
Short name T322
Test name
Test status
Simulation time 32361619 ps
CPU time 2.53 seconds
Started Jul 31 07:38:06 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 232768 kb
Host smart-bc75e232-fd71-4e38-bd80-f9b83f4d2e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314263907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1314263907
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.509691873
Short name T551
Test name
Test status
Simulation time 3290794284 ps
CPU time 8.33 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:15 PM PDT 24
Peak memory 233172 kb
Host smart-e08f3747-7b58-45ba-afd8-957bc0cb23b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509691873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.509691873
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2481663456
Short name T602
Test name
Test status
Simulation time 1256086533 ps
CPU time 8.55 seconds
Started Jul 31 07:38:07 PM PDT 24
Finished Jul 31 07:38:15 PM PDT 24
Peak memory 223000 kb
Host smart-dbb30ac7-e97b-40fe-85f6-b5bcb1f8db4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481663456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2481663456
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3105518007
Short name T890
Test name
Test status
Simulation time 39425140165 ps
CPU time 270.85 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:42:35 PM PDT 24
Peak memory 274204 kb
Host smart-522abe56-f8a7-40c4-baeb-60ca07f774e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105518007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3105518007
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2517541978
Short name T303
Test name
Test status
Simulation time 4203936914 ps
CPU time 11.52 seconds
Started Jul 31 07:38:09 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 216696 kb
Host smart-9c87c02d-26d6-431f-8d2b-f0f937dbc31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517541978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2517541978
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1889751516
Short name T381
Test name
Test status
Simulation time 1929641443 ps
CPU time 10.11 seconds
Started Jul 31 07:38:05 PM PDT 24
Finished Jul 31 07:38:15 PM PDT 24
Peak memory 216716 kb
Host smart-a2e0c0e4-d254-4005-aabf-41c432c9f6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889751516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1889751516
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.257624919
Short name T467
Test name
Test status
Simulation time 365557973 ps
CPU time 6.69 seconds
Started Jul 31 07:38:04 PM PDT 24
Finished Jul 31 07:38:11 PM PDT 24
Peak memory 216720 kb
Host smart-17215a03-1427-4000-88bf-54eea344ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257624919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.257624919
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3845388616
Short name T786
Test name
Test status
Simulation time 67131194 ps
CPU time 0.76 seconds
Started Jul 31 07:38:08 PM PDT 24
Finished Jul 31 07:38:09 PM PDT 24
Peak memory 206360 kb
Host smart-38b2ca0a-2359-4d56-99ea-b294a5af1f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845388616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3845388616
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2212976033
Short name T733
Test name
Test status
Simulation time 78400663 ps
CPU time 2.34 seconds
Started Jul 31 07:38:22 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 223656 kb
Host smart-f1892b1e-d16b-497c-8195-e6b526450dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212976033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2212976033
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3641740057
Short name T564
Test name
Test status
Simulation time 21445555 ps
CPU time 0.69 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:13 PM PDT 24
Peak memory 205808 kb
Host smart-f95be2fd-374f-465c-8e20-f5e77558aa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641740057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3641740057
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1148567850
Short name T243
Test name
Test status
Simulation time 346806556 ps
CPU time 4.21 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:38:17 PM PDT 24
Peak memory 224872 kb
Host smart-87f47c00-92cd-4b41-987d-ee9e3f80861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148567850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1148567850
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.602030464
Short name T766
Test name
Test status
Simulation time 19046096 ps
CPU time 0.8 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 207264 kb
Host smart-b5323284-4358-4416-8590-1e71ddef3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602030464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.602030464
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.667351916
Short name T261
Test name
Test status
Simulation time 44438854515 ps
CPU time 106.57 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:40:00 PM PDT 24
Peak memory 257576 kb
Host smart-6305c3b4-028a-44e0-87d0-f5a8ea5f516e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667351916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.667351916
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3738404366
Short name T59
Test name
Test status
Simulation time 12493767528 ps
CPU time 49.75 seconds
Started Jul 31 07:38:33 PM PDT 24
Finished Jul 31 07:39:23 PM PDT 24
Peak memory 252124 kb
Host smart-0db29f95-9b67-470a-b54e-d4da015065b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738404366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3738404366
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1996066221
Short name T278
Test name
Test status
Simulation time 212616687582 ps
CPU time 570.88 seconds
Started Jul 31 07:38:16 PM PDT 24
Finished Jul 31 07:47:47 PM PDT 24
Peak memory 256648 kb
Host smart-c8cd91e5-12ea-4511-8e04-63dc83f31f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996066221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1996066221
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4040441448
Short name T804
Test name
Test status
Simulation time 1560812664 ps
CPU time 2.94 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:18 PM PDT 24
Peak memory 224924 kb
Host smart-046a9305-8814-4e74-8202-1b6d4941f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040441448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4040441448
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.598935635
Short name T260
Test name
Test status
Simulation time 19757668977 ps
CPU time 167.51 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:41:01 PM PDT 24
Peak memory 262892 kb
Host smart-5bfe0d73-e8ea-484b-a590-4d46897e81ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598935635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.598935635
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4089893160
Short name T330
Test name
Test status
Simulation time 31322515 ps
CPU time 1.99 seconds
Started Jul 31 07:38:11 PM PDT 24
Finished Jul 31 07:38:14 PM PDT 24
Peak memory 218848 kb
Host smart-a7fa647a-a4e0-47e3-ad41-a558df7caa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089893160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4089893160
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1551546718
Short name T959
Test name
Test status
Simulation time 279722489 ps
CPU time 5.52 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:38:19 PM PDT 24
Peak memory 233168 kb
Host smart-6df36c37-e41f-410f-bdc3-a3e9b4ff4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551546718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1551546718
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1547709075
Short name T598
Test name
Test status
Simulation time 3457453540 ps
CPU time 3.99 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 233108 kb
Host smart-5103a711-69ed-4cb7-a7bf-05d593e3ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547709075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1547709075
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1325121090
Short name T902
Test name
Test status
Simulation time 26697606829 ps
CPU time 11.33 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:38:24 PM PDT 24
Peak memory 239892 kb
Host smart-87ff0391-f26e-468a-8291-1f0289338f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325121090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1325121090
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3538853624
Short name T82
Test name
Test status
Simulation time 248879241 ps
CPU time 4.87 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:17 PM PDT 24
Peak memory 220184 kb
Host smart-2409be75-6682-4ef7-b39e-c90aeaa43f8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3538853624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3538853624
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1992408228
Short name T52
Test name
Test status
Simulation time 3359123001 ps
CPU time 21.43 seconds
Started Jul 31 07:38:11 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 216844 kb
Host smart-9f914e95-5cfa-4578-b218-eea3b1bd40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992408228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1992408228
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4077725433
Short name T569
Test name
Test status
Simulation time 2406410330 ps
CPU time 8.58 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:38:22 PM PDT 24
Peak memory 216748 kb
Host smart-5bf47969-0425-4999-84e8-c9cff0d089a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077725433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4077725433
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2261155728
Short name T907
Test name
Test status
Simulation time 185995611 ps
CPU time 1.25 seconds
Started Jul 31 07:38:16 PM PDT 24
Finished Jul 31 07:38:17 PM PDT 24
Peak memory 208320 kb
Host smart-a0cbdf59-655f-4072-abf4-fdc79a4f0919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261155728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2261155728
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.558488521
Short name T567
Test name
Test status
Simulation time 45178476 ps
CPU time 0.8 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:13 PM PDT 24
Peak memory 206484 kb
Host smart-f05073cf-e3ce-4b9b-99f2-ac7fe44d7012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558488521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.558488521
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.732831306
Short name T666
Test name
Test status
Simulation time 32947973 ps
CPU time 2.69 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:24 PM PDT 24
Peak memory 232792 kb
Host smart-8e69159b-e74b-4b67-89f7-26253f711147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732831306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.732831306
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2740641887
Short name T557
Test name
Test status
Simulation time 14864927 ps
CPU time 0.71 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 205796 kb
Host smart-39ec1ceb-19fe-4938-bbae-f320862bc5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740641887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2740641887
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3086942531
Short name T321
Test name
Test status
Simulation time 1608204719 ps
CPU time 10.62 seconds
Started Jul 31 07:38:11 PM PDT 24
Finished Jul 31 07:38:22 PM PDT 24
Peak memory 224848 kb
Host smart-22d88a88-d70b-43ae-92fb-1f31b86f9ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086942531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3086942531
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1881647562
Short name T512
Test name
Test status
Simulation time 14225307 ps
CPU time 0.74 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 206260 kb
Host smart-c5a8f794-d35d-4442-9939-0dc92d0427d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881647562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1881647562
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3158372740
Short name T857
Test name
Test status
Simulation time 3892995243 ps
CPU time 22.73 seconds
Started Jul 31 07:38:22 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 250328 kb
Host smart-517410c9-2130-4a55-98a2-a7adf4fce235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158372740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3158372740
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.302236248
Short name T263
Test name
Test status
Simulation time 19592016852 ps
CPU time 250.35 seconds
Started Jul 31 07:38:13 PM PDT 24
Finished Jul 31 07:42:24 PM PDT 24
Peak memory 253420 kb
Host smart-6451e918-d06f-4c5b-9295-6ea6127f6dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302236248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.302236248
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3569404295
Short name T787
Test name
Test status
Simulation time 59194909169 ps
CPU time 194.77 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:41:29 PM PDT 24
Peak memory 249660 kb
Host smart-f53971b9-0e56-4803-8974-27e25abbacd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569404295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3569404295
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3477373642
Short name T954
Test name
Test status
Simulation time 742457246 ps
CPU time 15.04 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:28 PM PDT 24
Peak memory 224888 kb
Host smart-e4881d59-bd26-4919-bf7e-b3322b94933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477373642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3477373642
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4271240730
Short name T510
Test name
Test status
Simulation time 14817250068 ps
CPU time 35.99 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:38:51 PM PDT 24
Peak memory 249576 kb
Host smart-095fdd6e-7580-4ac3-8b39-370056f80bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271240730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4271240730
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2272112072
Short name T903
Test name
Test status
Simulation time 1956777019 ps
CPU time 6.85 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:28 PM PDT 24
Peak memory 233136 kb
Host smart-320cd0e7-9c87-4768-b99f-301f51bb723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272112072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2272112072
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.224877645
Short name T714
Test name
Test status
Simulation time 1475047759 ps
CPU time 13.02 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 241112 kb
Host smart-1222b5b3-998a-4e5b-8e51-af250312f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224877645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.224877645
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1956474140
Short name T782
Test name
Test status
Simulation time 775410232 ps
CPU time 6.65 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 233036 kb
Host smart-f7516020-1769-46c3-a09e-0b4639fcae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956474140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1956474140
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2105853890
Short name T252
Test name
Test status
Simulation time 9765861993 ps
CPU time 13.24 seconds
Started Jul 31 07:38:11 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 241396 kb
Host smart-ae5146fe-af65-44c2-83ef-8c3d0a7d4201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105853890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2105853890
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1063338872
Short name T618
Test name
Test status
Simulation time 5565074055 ps
CPU time 8.69 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:30 PM PDT 24
Peak memory 221036 kb
Host smart-b0683783-d411-40a4-8966-1b85ec5b641a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1063338872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1063338872
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2854122846
Short name T129
Test name
Test status
Simulation time 3699108048 ps
CPU time 13.94 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:38:28 PM PDT 24
Peak memory 216944 kb
Host smart-7a36de99-145d-4bb5-9b3a-15099fa63750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854122846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2854122846
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3709928378
Short name T485
Test name
Test status
Simulation time 858375729 ps
CPU time 3.91 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 216632 kb
Host smart-c75032e9-e246-417f-845f-c79feee33759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709928378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3709928378
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4056550525
Short name T819
Test name
Test status
Simulation time 57690207 ps
CPU time 0.84 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 206344 kb
Host smart-e5466a94-b5f2-4601-89a8-5701c430b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056550525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4056550525
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.286444292
Short name T170
Test name
Test status
Simulation time 152505312863 ps
CPU time 30.52 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:46 PM PDT 24
Peak memory 233180 kb
Host smart-c692742f-6ec5-4b4b-898b-2ff83c2e7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286444292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.286444292
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3900156019
Short name T400
Test name
Test status
Simulation time 33852709 ps
CPU time 0.68 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:24 PM PDT 24
Peak memory 206148 kb
Host smart-d9deada2-6d99-4e25-be32-22bd2c587e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900156019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3900156019
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1871578713
Short name T738
Test name
Test status
Simulation time 166799632 ps
CPU time 3.91 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 224964 kb
Host smart-1d079623-d3f9-4806-9a32-a42751cc2f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871578713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1871578713
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2780584790
Short name T334
Test name
Test status
Simulation time 37193468 ps
CPU time 0.84 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 206936 kb
Host smart-bf5618ef-018f-4ae3-a73c-7078cec82140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780584790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2780584790
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.469671664
Short name T925
Test name
Test status
Simulation time 4791341427 ps
CPU time 42.82 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:39:06 PM PDT 24
Peak memory 249540 kb
Host smart-803d949b-49ac-4902-949d-e565cfd20377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469671664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.469671664
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.625436333
Short name T216
Test name
Test status
Simulation time 11228605043 ps
CPU time 62.66 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:39:24 PM PDT 24
Peak memory 237000 kb
Host smart-3412d951-b7c8-4ec7-8b23-8cefd3c24a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625436333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.625436333
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2249518062
Short name T141
Test name
Test status
Simulation time 185597691377 ps
CPU time 429.61 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:45:34 PM PDT 24
Peak memory 257828 kb
Host smart-a969b262-9152-4434-9657-97748872cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249518062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2249518062
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3912853163
Short name T444
Test name
Test status
Simulation time 331268150 ps
CPU time 5.1 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 224984 kb
Host smart-e0184587-8a32-42cd-bbb8-6508905db488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912853163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3912853163
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3228877470
Short name T636
Test name
Test status
Simulation time 228562624 ps
CPU time 5.34 seconds
Started Jul 31 07:38:20 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 233060 kb
Host smart-e940ceeb-59e1-414c-b83b-1fda9d49e597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228877470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3228877470
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4148967010
Short name T799
Test name
Test status
Simulation time 25488520830 ps
CPU time 64.74 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:39:26 PM PDT 24
Peak memory 233196 kb
Host smart-0075ad35-87c5-4dc8-953f-a30d7b986000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148967010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4148967010
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.600205647
Short name T473
Test name
Test status
Simulation time 57692448 ps
CPU time 2.57 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:23 PM PDT 24
Peak memory 232796 kb
Host smart-2a3045db-b910-4dbb-a96d-2f8ae55c2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600205647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.600205647
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1203251330
Short name T791
Test name
Test status
Simulation time 3034759885 ps
CPU time 4.55 seconds
Started Jul 31 07:38:14 PM PDT 24
Finished Jul 31 07:38:19 PM PDT 24
Peak memory 224964 kb
Host smart-c9108c06-4c8b-448d-8d8d-d4067129a303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203251330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1203251330
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3661870147
Short name T945
Test name
Test status
Simulation time 14222866537 ps
CPU time 9.35 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 223660 kb
Host smart-a590e039-71f8-417b-9aae-c2ee6a7868d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661870147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3661870147
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1024286549
Short name T775
Test name
Test status
Simulation time 165277454 ps
CPU time 0.95 seconds
Started Jul 31 07:38:20 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 207120 kb
Host smart-8480580d-d6fc-43a4-a115-48e2464eb5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024286549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1024286549
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.963960119
Short name T952
Test name
Test status
Simulation time 18114480187 ps
CPU time 29.53 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 221444 kb
Host smart-47b184c1-c8ef-4696-b4c4-55d639568b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963960119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.963960119
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3243217211
Short name T89
Test name
Test status
Simulation time 4838483443 ps
CPU time 7.97 seconds
Started Jul 31 07:38:12 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 216828 kb
Host smart-0935945e-0a7b-46e4-9e6d-783acb5d1f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243217211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3243217211
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2574849251
Short name T972
Test name
Test status
Simulation time 10468951 ps
CPU time 0.67 seconds
Started Jul 31 07:38:15 PM PDT 24
Finished Jul 31 07:38:16 PM PDT 24
Peak memory 206008 kb
Host smart-e692fc82-b1c5-4b90-9492-647853b7db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574849251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2574849251
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.218799991
Short name T455
Test name
Test status
Simulation time 35744876 ps
CPU time 0.81 seconds
Started Jul 31 07:38:34 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 206308 kb
Host smart-3f4ee7bf-6710-4a6f-98e2-6e1edcd4e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218799991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.218799991
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2084604717
Short name T605
Test name
Test status
Simulation time 5753696456 ps
CPU time 14.03 seconds
Started Jul 31 07:38:22 PM PDT 24
Finished Jul 31 07:38:36 PM PDT 24
Peak memory 248580 kb
Host smart-493e6a45-7000-433e-a81a-341885d54830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084604717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2084604717
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2601616870
Short name T638
Test name
Test status
Simulation time 12377861 ps
CPU time 0.69 seconds
Started Jul 31 07:38:20 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 204856 kb
Host smart-0b2c9386-bb27-4fbf-9958-42e71ebfc21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601616870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2601616870
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.110849663
Short name T608
Test name
Test status
Simulation time 97996282 ps
CPU time 2.88 seconds
Started Jul 31 07:38:27 PM PDT 24
Finished Jul 31 07:38:30 PM PDT 24
Peak memory 233112 kb
Host smart-589ad50c-631b-48eb-93fd-33ad4bfbf8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110849663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.110849663
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1720870873
Short name T865
Test name
Test status
Simulation time 35046213 ps
CPU time 0.75 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:25 PM PDT 24
Peak memory 205888 kb
Host smart-ea8efa3c-dc45-4f8b-b49d-0efdbe6c52d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720870873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1720870873
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2458310334
Short name T62
Test name
Test status
Simulation time 73518513495 ps
CPU time 106.86 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:40:08 PM PDT 24
Peak memory 251424 kb
Host smart-4bfc472f-2e5d-463f-8f39-860f751c5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458310334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2458310334
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2212736194
Short name T772
Test name
Test status
Simulation time 3834815074 ps
CPU time 70.36 seconds
Started Jul 31 07:38:25 PM PDT 24
Finished Jul 31 07:39:35 PM PDT 24
Peak memory 249576 kb
Host smart-4c839163-e633-4fa2-8302-f679752aad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212736194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2212736194
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.329051650
Short name T1003
Test name
Test status
Simulation time 5420110832 ps
CPU time 34.4 seconds
Started Jul 31 07:38:23 PM PDT 24
Finished Jul 31 07:38:58 PM PDT 24
Peak memory 218128 kb
Host smart-449716aa-b56a-4888-90e6-e868a2bc6568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329051650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.329051650
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3042956311
Short name T832
Test name
Test status
Simulation time 863077487 ps
CPU time 9.89 seconds
Started Jul 31 07:38:22 PM PDT 24
Finished Jul 31 07:38:32 PM PDT 24
Peak memory 224908 kb
Host smart-1d4cdb0d-4f1f-4878-9a3c-77ab39dd5ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042956311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3042956311
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1358346602
Short name T835
Test name
Test status
Simulation time 3982984052 ps
CPU time 34.6 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:59 PM PDT 24
Peak memory 235172 kb
Host smart-29cdf5e8-95fd-4897-90dd-4d5a69667615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358346602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1358346602
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.853510889
Short name T606
Test name
Test status
Simulation time 1169666797 ps
CPU time 11.2 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 233180 kb
Host smart-149e905d-f8ef-4d3b-9f66-06069c97d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853510889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.853510889
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2091863739
Short name T452
Test name
Test status
Simulation time 768208248 ps
CPU time 18.21 seconds
Started Jul 31 07:38:23 PM PDT 24
Finished Jul 31 07:38:41 PM PDT 24
Peak memory 249528 kb
Host smart-c3d63fb2-ddd4-430e-a001-a7794273d403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091863739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2091863739
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1827758795
Short name T935
Test name
Test status
Simulation time 33342014 ps
CPU time 2.64 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:27 PM PDT 24
Peak memory 232828 kb
Host smart-54b7f579-e350-4949-8a96-c6bee56999b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827758795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1827758795
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.703298379
Short name T962
Test name
Test status
Simulation time 8391634527 ps
CPU time 13.09 seconds
Started Jul 31 07:38:40 PM PDT 24
Finished Jul 31 07:38:53 PM PDT 24
Peak memory 224936 kb
Host smart-f664be21-0158-4e8e-8360-f71a4339af26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703298379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.703298379
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3757056048
Short name T980
Test name
Test status
Simulation time 5581307211 ps
CPU time 16.43 seconds
Started Jul 31 07:38:38 PM PDT 24
Finished Jul 31 07:38:55 PM PDT 24
Peak memory 222372 kb
Host smart-dbe451fc-3a73-41f2-bc70-626b14583a1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757056048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3757056048
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2413512901
Short name T157
Test name
Test status
Simulation time 155762747631 ps
CPU time 493.59 seconds
Started Jul 31 07:38:27 PM PDT 24
Finished Jul 31 07:46:41 PM PDT 24
Peak memory 265188 kb
Host smart-e0efc9ca-2563-42e9-b738-7fa4e90ad3cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413512901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2413512901
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1868268504
Short name T305
Test name
Test status
Simulation time 16579832973 ps
CPU time 17.1 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 216956 kb
Host smart-44d76655-8293-4335-905b-477f4cfe717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868268504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1868268504
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4192139382
Short name T826
Test name
Test status
Simulation time 134013125 ps
CPU time 1.02 seconds
Started Jul 31 07:38:25 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 207396 kb
Host smart-6ab138d8-5a33-4dbc-a676-4f946234b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192139382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4192139382
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2198381471
Short name T939
Test name
Test status
Simulation time 68827544 ps
CPU time 1 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:22 PM PDT 24
Peak memory 207548 kb
Host smart-97f96847-ca2f-4f82-9006-9f885c2fdd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198381471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2198381471
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4052758883
Short name T988
Test name
Test status
Simulation time 63112516 ps
CPU time 0.82 seconds
Started Jul 31 07:38:25 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 206364 kb
Host smart-d189bdb3-01be-48fb-9a0f-00fa73f16e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052758883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4052758883
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4154436790
Short name T948
Test name
Test status
Simulation time 14132409263 ps
CPU time 11.54 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 225140 kb
Host smart-b3aff499-eba5-4a3a-87d2-64e7beae2f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154436790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4154436790
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.14381111
Short name T802
Test name
Test status
Simulation time 142174373 ps
CPU time 0.72 seconds
Started Jul 31 07:38:34 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 205832 kb
Host smart-e2a83330-7074-45b6-a3e2-67acf754ee99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14381111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.14381111
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3369438412
Short name T716
Test name
Test status
Simulation time 717200442 ps
CPU time 3.04 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:38:35 PM PDT 24
Peak memory 224904 kb
Host smart-85085299-a1b1-434f-b053-0d10bd021053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369438412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3369438412
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.710660778
Short name T580
Test name
Test status
Simulation time 73813371 ps
CPU time 0.82 seconds
Started Jul 31 07:38:27 PM PDT 24
Finished Jul 31 07:38:28 PM PDT 24
Peak memory 206948 kb
Host smart-812b5ab9-89b1-4e63-88bc-9ad7d6840e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710660778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.710660778
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1811963168
Short name T774
Test name
Test status
Simulation time 31540895 ps
CPU time 0.78 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:38:31 PM PDT 24
Peak memory 216136 kb
Host smart-7163cdff-3147-4fe7-8c9b-78501f82ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811963168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1811963168
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4193795018
Short name T769
Test name
Test status
Simulation time 3438126540 ps
CPU time 36.98 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:39:08 PM PDT 24
Peak memory 233156 kb
Host smart-7530321b-7ca7-4725-81d0-f6bc9b838ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193795018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4193795018
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1818048059
Short name T142
Test name
Test status
Simulation time 1657280041 ps
CPU time 7.93 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 233160 kb
Host smart-dd363b9a-6c80-4945-a0cc-7b21b88cf57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818048059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1818048059
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1427970833
Short name T262
Test name
Test status
Simulation time 48122623764 ps
CPU time 71.26 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:39:41 PM PDT 24
Peak memory 253784 kb
Host smart-befa0fa8-6a1c-49b4-b30e-d3bec9a0a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427970833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1427970833
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.759149377
Short name T507
Test name
Test status
Simulation time 1432244927 ps
CPU time 6.18 seconds
Started Jul 31 07:38:32 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 233124 kb
Host smart-2b937399-e497-4947-86fb-c43a9876541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759149377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.759149377
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2378542512
Short name T353
Test name
Test status
Simulation time 15887663967 ps
CPU time 76.75 seconds
Started Jul 31 07:38:36 PM PDT 24
Finished Jul 31 07:39:52 PM PDT 24
Peak memory 233360 kb
Host smart-f72091a7-f30c-4934-9648-d12e5e8662ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378542512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2378542512
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.628833170
Short name T656
Test name
Test status
Simulation time 2705873455 ps
CPU time 13.14 seconds
Started Jul 31 07:38:23 PM PDT 24
Finished Jul 31 07:38:36 PM PDT 24
Peak memory 224968 kb
Host smart-6b423ec7-0473-497f-a4da-45024e50abcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628833170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.628833170
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3461418453
Short name T350
Test name
Test status
Simulation time 77515083 ps
CPU time 2.07 seconds
Started Jul 31 07:38:40 PM PDT 24
Finished Jul 31 07:38:42 PM PDT 24
Peak memory 224572 kb
Host smart-61a72ee6-0ce0-4638-a26e-82c0e94c1112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461418453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3461418453
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1583288454
Short name T495
Test name
Test status
Simulation time 526793478 ps
CPU time 5.94 seconds
Started Jul 31 07:38:32 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 223120 kb
Host smart-09d27674-932c-4598-bfc2-2776d919e532
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1583288454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1583288454
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4126761311
Short name T476
Test name
Test status
Simulation time 3852026466 ps
CPU time 17.58 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:41 PM PDT 24
Peak memory 216696 kb
Host smart-6f573651-324c-4a61-bbdd-9885fbf95c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126761311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4126761311
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1533701238
Short name T132
Test name
Test status
Simulation time 40491146 ps
CPU time 0.75 seconds
Started Jul 31 07:38:20 PM PDT 24
Finished Jul 31 07:38:21 PM PDT 24
Peak memory 206024 kb
Host smart-d6fc3c47-d742-4d64-8ccb-473b77501d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533701238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1533701238
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3351217698
Short name T314
Test name
Test status
Simulation time 79548292 ps
CPU time 1.86 seconds
Started Jul 31 07:38:24 PM PDT 24
Finished Jul 31 07:38:26 PM PDT 24
Peak memory 216628 kb
Host smart-71f76c0b-c370-492b-a004-f42e42721a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351217698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3351217698
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4074208264
Short name T436
Test name
Test status
Simulation time 51208478 ps
CPU time 0.72 seconds
Started Jul 31 07:38:21 PM PDT 24
Finished Jul 31 07:38:22 PM PDT 24
Peak memory 206256 kb
Host smart-27acbbe2-8727-4de1-8a5f-b008de18e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074208264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4074208264
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1889900988
Short name T530
Test name
Test status
Simulation time 1488835966 ps
CPU time 7.96 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 233160 kb
Host smart-5d26ec1d-58e5-403b-b348-38a8db02f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889900988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1889900988
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.230865910
Short name T6
Test name
Test status
Simulation time 40028622 ps
CPU time 0.75 seconds
Started Jul 31 07:38:44 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 206108 kb
Host smart-a59c271c-1e89-4cc7-83f5-f43f5719a909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230865910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.230865910
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2139577343
Short name T3
Test name
Test status
Simulation time 8836308644 ps
CPU time 16.8 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:38:47 PM PDT 24
Peak memory 232996 kb
Host smart-e41cc254-11f9-4339-84f2-1f3dc4a7238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139577343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2139577343
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3484132811
Short name T578
Test name
Test status
Simulation time 17623829 ps
CPU time 0.82 seconds
Started Jul 31 07:38:37 PM PDT 24
Finished Jul 31 07:38:37 PM PDT 24
Peak memory 206920 kb
Host smart-55881b47-5d6d-4070-a6f3-69f66dc142d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484132811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3484132811
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3652704768
Short name T372
Test name
Test status
Simulation time 14041425 ps
CPU time 0.78 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:38:44 PM PDT 24
Peak memory 216092 kb
Host smart-e3f9a850-3343-4158-b1f7-d934016e412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652704768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3652704768
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3033889724
Short name T915
Test name
Test status
Simulation time 32947712465 ps
CPU time 91.88 seconds
Started Jul 31 07:38:42 PM PDT 24
Finished Jul 31 07:40:14 PM PDT 24
Peak memory 260932 kb
Host smart-35d98cc1-348f-402c-bfed-05e4b1bedf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033889724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3033889724
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2182878259
Short name T456
Test name
Test status
Simulation time 15071395396 ps
CPU time 56.64 seconds
Started Jul 31 07:38:42 PM PDT 24
Finished Jul 31 07:39:39 PM PDT 24
Peak memory 257400 kb
Host smart-2fac98b0-45c0-4399-bf6c-e2b72ced2cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182878259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2182878259
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.460753538
Short name T337
Test name
Test status
Simulation time 317284366 ps
CPU time 7.58 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:38:39 PM PDT 24
Peak memory 241276 kb
Host smart-1e658e5c-36aa-42c3-bc73-545d03e3ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460753538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.460753538
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2211154111
Short name T207
Test name
Test status
Simulation time 2099036791 ps
CPU time 11.12 seconds
Started Jul 31 07:38:34 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 235576 kb
Host smart-e1a93660-7ba1-4c77-91cd-8f49cf2c2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211154111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2211154111
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1799803580
Short name T807
Test name
Test status
Simulation time 148285206 ps
CPU time 4.15 seconds
Started Jul 31 07:38:34 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 233116 kb
Host smart-72c5ba10-a322-4bbb-aad2-5fb024519252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799803580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1799803580
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1975394412
Short name T866
Test name
Test status
Simulation time 5289931340 ps
CPU time 26.48 seconds
Started Jul 31 07:38:37 PM PDT 24
Finished Jul 31 07:39:03 PM PDT 24
Peak memory 233116 kb
Host smart-a263e116-a7b3-4638-aa24-3725af33fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975394412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1975394412
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2775967580
Short name T174
Test name
Test status
Simulation time 3050216544 ps
CPU time 8.3 seconds
Started Jul 31 07:38:33 PM PDT 24
Finished Jul 31 07:38:42 PM PDT 24
Peak memory 224892 kb
Host smart-5f45d49b-3aca-4743-9f5b-33a85f99a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775967580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2775967580
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2337183469
Short name T217
Test name
Test status
Simulation time 7368156109 ps
CPU time 21.24 seconds
Started Jul 31 07:38:33 PM PDT 24
Finished Jul 31 07:38:55 PM PDT 24
Peak memory 240996 kb
Host smart-1ae07834-74de-441e-87fc-eec36d10dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337183469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2337183469
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.864515514
Short name T355
Test name
Test status
Simulation time 1179024238 ps
CPU time 11.9 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:38:53 PM PDT 24
Peak memory 222012 kb
Host smart-741277d4-7862-426f-af71-04cc4fe6ef3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=864515514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.864515514
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1751424842
Short name T316
Test name
Test status
Simulation time 3583985553 ps
CPU time 25.64 seconds
Started Jul 31 07:38:34 PM PDT 24
Finished Jul 31 07:38:59 PM PDT 24
Peak memory 216880 kb
Host smart-4106f87d-231d-4218-83ab-9861e287dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751424842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1751424842
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.695644574
Short name T328
Test name
Test status
Simulation time 8609095567 ps
CPU time 7.14 seconds
Started Jul 31 07:38:31 PM PDT 24
Finished Jul 31 07:38:38 PM PDT 24
Peak memory 216852 kb
Host smart-c3d60149-00eb-40ad-8fc6-1e12438bda8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695644574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.695644574
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3841250677
Short name T469
Test name
Test status
Simulation time 29861850 ps
CPU time 0.87 seconds
Started Jul 31 07:38:32 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 206904 kb
Host smart-a9c5bfcb-6118-47dd-b4c3-fb82bbdb4ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841250677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3841250677
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3000856651
Short name T458
Test name
Test status
Simulation time 17052076 ps
CPU time 0.76 seconds
Started Jul 31 07:38:32 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 206360 kb
Host smart-6994b08e-b19a-4c34-bda7-db13e2a1c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000856651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3000856651
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3394081355
Short name T486
Test name
Test status
Simulation time 40358163 ps
CPU time 2.16 seconds
Started Jul 31 07:38:30 PM PDT 24
Finished Jul 31 07:38:33 PM PDT 24
Peak memory 224596 kb
Host smart-7dba090a-1b4d-4279-aa9f-70d6629cfefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394081355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3394081355
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4206114674
Short name T538
Test name
Test status
Simulation time 19850066 ps
CPU time 0.79 seconds
Started Jul 31 07:38:44 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 205328 kb
Host smart-bfa7a26d-98d7-4091-97a5-316a51c7c3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206114674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4206114674
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1584435869
Short name T451
Test name
Test status
Simulation time 96638837 ps
CPU time 2.84 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:38:46 PM PDT 24
Peak memory 233140 kb
Host smart-a3f62812-d56d-4a11-9949-bdec079692f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584435869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1584435869
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1373736719
Short name T720
Test name
Test status
Simulation time 16255482 ps
CPU time 0.8 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:38:42 PM PDT 24
Peak memory 206976 kb
Host smart-97f2a726-afff-406d-9f1a-95ad0f4299f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373736719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1373736719
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.85582929
Short name T85
Test name
Test status
Simulation time 7310395822 ps
CPU time 66.55 seconds
Started Jul 31 07:38:42 PM PDT 24
Finished Jul 31 07:39:49 PM PDT 24
Peak memory 253608 kb
Host smart-0d208da4-6274-467e-8133-0ca2dca7a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85582929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.85582929
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.388118325
Short name T1004
Test name
Test status
Simulation time 9249954886 ps
CPU time 47.83 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:39:31 PM PDT 24
Peak memory 219708 kb
Host smart-a8662202-4cf9-47ce-a68a-88e5b6a65314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388118325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.388118325
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.244166438
Short name T1002
Test name
Test status
Simulation time 3293879034 ps
CPU time 75.88 seconds
Started Jul 31 07:38:44 PM PDT 24
Finished Jul 31 07:40:00 PM PDT 24
Peak memory 255312 kb
Host smart-3c849654-087e-44e3-bfb0-91777d3a9079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244166438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.244166438
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1019039678
Short name T773
Test name
Test status
Simulation time 1631102518 ps
CPU time 20.87 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:39:02 PM PDT 24
Peak memory 237416 kb
Host smart-12becc3c-2402-41c9-9c93-d7b539a26f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019039678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1019039678
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3250719937
Short name T985
Test name
Test status
Simulation time 8900276067 ps
CPU time 34.88 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:39:18 PM PDT 24
Peak memory 237156 kb
Host smart-5bbc6fc2-9921-4c6c-974f-ab15698a9072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250719937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3250719937
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2243196105
Short name T850
Test name
Test status
Simulation time 1179482619 ps
CPU time 13.11 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:38:56 PM PDT 24
Peak memory 233096 kb
Host smart-07326fe8-7840-4bbf-8321-38f796503970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243196105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2243196105
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1832093632
Short name T247
Test name
Test status
Simulation time 2364198203 ps
CPU time 5.83 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:38:46 PM PDT 24
Peak memory 233168 kb
Host smart-366fd9d7-7076-4b9c-80b7-03cdd616120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832093632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1832093632
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.993947321
Short name T728
Test name
Test status
Simulation time 1646925582 ps
CPU time 11.67 seconds
Started Jul 31 07:38:40 PM PDT 24
Finished Jul 31 07:38:51 PM PDT 24
Peak memory 233084 kb
Host smart-86ddca01-c5ab-4a9b-90f0-cc917a57d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993947321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.993947321
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4252066076
Short name T14
Test name
Test status
Simulation time 822409925 ps
CPU time 6.86 seconds
Started Jul 31 07:38:44 PM PDT 24
Finished Jul 31 07:38:51 PM PDT 24
Peak memory 233116 kb
Host smart-25fc36f4-8849-4199-8dba-fd2d5d49e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252066076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4252066076
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2550663022
Short name T653
Test name
Test status
Simulation time 1816032898 ps
CPU time 7.1 seconds
Started Jul 31 07:38:43 PM PDT 24
Finished Jul 31 07:38:51 PM PDT 24
Peak memory 222468 kb
Host smart-eb72d168-0927-4790-9e7d-88c30fe952e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2550663022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2550663022
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.262002978
Short name T910
Test name
Test status
Simulation time 16334972190 ps
CPU time 149.57 seconds
Started Jul 31 07:38:40 PM PDT 24
Finished Jul 31 07:41:09 PM PDT 24
Peak memory 251664 kb
Host smart-b3b8bc62-2f6b-4225-82f2-d69513ce5d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262002978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.262002978
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.301290747
Short name T788
Test name
Test status
Simulation time 17693077241 ps
CPU time 20.94 seconds
Started Jul 31 07:38:44 PM PDT 24
Finished Jul 31 07:39:05 PM PDT 24
Peak memory 216952 kb
Host smart-6ea90c01-d4bb-477c-94e7-f19740b70daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301290747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.301290747
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3553306037
Short name T505
Test name
Test status
Simulation time 726651090 ps
CPU time 3.82 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 216580 kb
Host smart-c49706e2-c58d-4a0d-aab8-f904683a9603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553306037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3553306037
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.576772712
Short name T31
Test name
Test status
Simulation time 195123622 ps
CPU time 9.4 seconds
Started Jul 31 07:38:40 PM PDT 24
Finished Jul 31 07:38:50 PM PDT 24
Peak memory 216532 kb
Host smart-abb57be0-7211-4116-9d3c-f81032ab9802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576772712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.576772712
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3655482573
Short name T398
Test name
Test status
Simulation time 26756204 ps
CPU time 0.81 seconds
Started Jul 31 07:38:39 PM PDT 24
Finished Jul 31 07:38:40 PM PDT 24
Peak memory 206432 kb
Host smart-b14e3833-5a32-43b6-9905-f75b11ba1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655482573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3655482573
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.543361678
Short name T740
Test name
Test status
Simulation time 825517331 ps
CPU time 4.07 seconds
Started Jul 31 07:38:41 PM PDT 24
Finished Jul 31 07:38:45 PM PDT 24
Peak memory 224852 kb
Host smart-f66cb58f-3783-42b6-9d99-1a801ff18a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543361678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.543361678
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.698971833
Short name T599
Test name
Test status
Simulation time 18790179 ps
CPU time 0.72 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:35:24 PM PDT 24
Peak memory 205216 kb
Host smart-ea06470f-79c8-4adf-8a65-6d4b7801956f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698971833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.698971833
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.139511244
Short name T885
Test name
Test status
Simulation time 137619931 ps
CPU time 2.43 seconds
Started Jul 31 07:35:16 PM PDT 24
Finished Jul 31 07:35:19 PM PDT 24
Peak memory 233120 kb
Host smart-d90e19a9-37be-40db-b67a-084a0c5f13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139511244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.139511244
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1868898281
Short name T418
Test name
Test status
Simulation time 15950207 ps
CPU time 0.78 seconds
Started Jul 31 07:35:18 PM PDT 24
Finished Jul 31 07:35:19 PM PDT 24
Peak memory 206812 kb
Host smart-c00dc51b-a163-4fbd-bc90-2c9d16f4865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868898281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1868898281
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1359018003
Short name T654
Test name
Test status
Simulation time 9961915801 ps
CPU time 55.89 seconds
Started Jul 31 07:35:25 PM PDT 24
Finished Jul 31 07:36:21 PM PDT 24
Peak memory 255628 kb
Host smart-f58b8a2d-6bf5-43c0-bb79-d7b3fb5b1014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359018003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1359018003
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.189507491
Short name T694
Test name
Test status
Simulation time 12505778256 ps
CPU time 54.77 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:36:17 PM PDT 24
Peak memory 252336 kb
Host smart-5de5cb00-7c9e-4e68-9caf-0c5c830d049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189507491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.189507491
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2041544269
Short name T565
Test name
Test status
Simulation time 12759629492 ps
CPU time 70.94 seconds
Started Jul 31 07:35:25 PM PDT 24
Finished Jul 31 07:36:36 PM PDT 24
Peak memory 254164 kb
Host smart-23f0c371-b8b7-4d23-8650-a9fbccd6c570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041544269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2041544269
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.458853417
Short name T715
Test name
Test status
Simulation time 3198623179 ps
CPU time 10.64 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:35:32 PM PDT 24
Peak memory 224980 kb
Host smart-ac0c2e46-e115-429b-bbfd-ccb525800e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458853417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.458853417
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.921628875
Short name T768
Test name
Test status
Simulation time 468853215 ps
CPU time 6.34 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:28 PM PDT 24
Peak memory 249508 kb
Host smart-c5146d80-bedf-4a38-a78f-d7fd652cedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921628875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
921628875
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1844036673
Short name T339
Test name
Test status
Simulation time 4429147445 ps
CPU time 14.01 seconds
Started Jul 31 07:35:17 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 233196 kb
Host smart-d401ac67-14c4-4303-bcd3-1e063fe470dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844036673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1844036673
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4275184286
Short name T572
Test name
Test status
Simulation time 4019831262 ps
CPU time 14.28 seconds
Started Jul 31 07:35:13 PM PDT 24
Finished Jul 31 07:35:27 PM PDT 24
Peak memory 220940 kb
Host smart-497c7d77-97ad-4b35-957d-cf15129db19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275184286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4275184286
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2752948751
Short name T620
Test name
Test status
Simulation time 1592794015 ps
CPU time 2.97 seconds
Started Jul 31 07:35:17 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 224860 kb
Host smart-66556729-48ea-4754-aeae-cba46b80be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752948751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2752948751
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2384655321
Short name T204
Test name
Test status
Simulation time 759605461 ps
CPU time 3.25 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:18 PM PDT 24
Peak memory 224884 kb
Host smart-ae0059d0-374a-4cc5-be38-a5e0d31f98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384655321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2384655321
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4281230532
Short name T932
Test name
Test status
Simulation time 445848642 ps
CPU time 6.77 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 223776 kb
Host smart-2939dcaf-d3f7-4fd1-a473-236bd01fd977
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4281230532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4281230532
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.514511597
Short name T673
Test name
Test status
Simulation time 339855237 ps
CPU time 1.26 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:24 PM PDT 24
Peak memory 207688 kb
Host smart-8718b759-8fea-4760-a6ce-e18fdb8d9137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514511597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.514511597
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1485584414
Short name T306
Test name
Test status
Simulation time 29282213758 ps
CPU time 24.26 seconds
Started Jul 31 07:35:18 PM PDT 24
Finished Jul 31 07:35:43 PM PDT 24
Peak memory 220468 kb
Host smart-6ad3da0e-e33e-4ff4-99cb-02b0fa4eefac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485584414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1485584414
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.565517481
Short name T340
Test name
Test status
Simulation time 1084091040 ps
CPU time 5.46 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 216744 kb
Host smart-5204caf4-959b-4aea-a91b-17180dc66ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565517481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.565517481
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2069489909
Short name T53
Test name
Test status
Simulation time 97209765 ps
CPU time 1.55 seconds
Started Jul 31 07:35:18 PM PDT 24
Finished Jul 31 07:35:20 PM PDT 24
Peak memory 216636 kb
Host smart-812f5678-4a8f-4c09-869c-5e28a19270b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069489909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2069489909
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2861402697
Short name T422
Test name
Test status
Simulation time 64904755 ps
CPU time 0.87 seconds
Started Jul 31 07:35:14 PM PDT 24
Finished Jul 31 07:35:15 PM PDT 24
Peak memory 206328 kb
Host smart-b3515e24-77f4-4089-b4b9-521ea01e8ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861402697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2861402697
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2571291462
Short name T44
Test name
Test status
Simulation time 42731285585 ps
CPU time 29.32 seconds
Started Jul 31 07:35:10 PM PDT 24
Finished Jul 31 07:35:39 PM PDT 24
Peak memory 241356 kb
Host smart-0688eb9e-1cf2-41bb-8e68-ee5e9b6f7a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571291462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2571291462
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1594475506
Short name T319
Test name
Test status
Simulation time 40275568 ps
CPU time 0.72 seconds
Started Jul 31 07:35:24 PM PDT 24
Finished Jul 31 07:35:25 PM PDT 24
Peak memory 206088 kb
Host smart-bef0e4e7-d61e-4557-9c0b-a4cec7af8149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594475506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
594475506
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3837432566
Short name T127
Test name
Test status
Simulation time 970532995 ps
CPU time 4.01 seconds
Started Jul 31 07:35:25 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 224812 kb
Host smart-29e45871-a2e8-4f01-96f3-0a4479252e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837432566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3837432566
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2783651364
Short name T369
Test name
Test status
Simulation time 65120583 ps
CPU time 0.77 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:23 PM PDT 24
Peak memory 206988 kb
Host smart-cb6a4ef6-016a-4d1d-9fd8-d00ce4b1d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783651364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2783651364
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1663810774
Short name T273
Test name
Test status
Simulation time 10332747826 ps
CPU time 124.16 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:37:25 PM PDT 24
Peak memory 267584 kb
Host smart-e45a2460-2370-4bb4-bef4-38a8e1ef514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663810774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1663810774
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.270782146
Short name T302
Test name
Test status
Simulation time 3546051475 ps
CPU time 43.48 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:36:06 PM PDT 24
Peak memory 257836 kb
Host smart-103e0765-98fc-4108-8f52-80f7a945ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270782146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
270782146
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3609586366
Short name T875
Test name
Test status
Simulation time 172602903 ps
CPU time 7.02 seconds
Started Jul 31 07:35:26 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 240140 kb
Host smart-a7702412-a883-405e-a897-fd7d08f9e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609586366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3609586366
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3683848392
Short name T525
Test name
Test status
Simulation time 28788360196 ps
CPU time 103.13 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:37:04 PM PDT 24
Peak memory 262784 kb
Host smart-0ff3825c-895c-4c09-80a2-8a962059729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683848392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3683848392
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4026362473
Short name T841
Test name
Test status
Simulation time 8269076998 ps
CPU time 15.09 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 233220 kb
Host smart-8c92934b-bc94-4e8c-8571-a55eb6e892fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026362473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4026362473
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1130490466
Short name T175
Test name
Test status
Simulation time 714635347 ps
CPU time 14.81 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 234196 kb
Host smart-2b8d7b81-f9bd-4ebf-beb3-829847521dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130490466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1130490466
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3861304836
Short name T524
Test name
Test status
Simulation time 33521279 ps
CPU time 2.42 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 232768 kb
Host smart-33fef13e-5e42-42e9-91e0-83f496cbf900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861304836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3861304836
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3180399116
Short name T968
Test name
Test status
Simulation time 5015283447 ps
CPU time 5.86 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 233196 kb
Host smart-3557da4b-b400-4af8-ac78-d5e55d5377f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180399116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3180399116
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.104227990
Short name T795
Test name
Test status
Simulation time 964515429 ps
CPU time 13.81 seconds
Started Jul 31 07:35:24 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 219340 kb
Host smart-6973398d-3cd4-4cd8-88fe-c61c7cf344c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104227990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.104227990
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2754558035
Short name T300
Test name
Test status
Simulation time 28214525022 ps
CPU time 39.55 seconds
Started Jul 31 07:35:24 PM PDT 24
Finished Jul 31 07:36:04 PM PDT 24
Peak memory 216724 kb
Host smart-7ed0f906-77fb-4447-9203-105580acee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754558035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2754558035
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1244783225
Short name T388
Test name
Test status
Simulation time 413204975 ps
CPU time 3.08 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:35:24 PM PDT 24
Peak memory 216640 kb
Host smart-ad8f771e-6e2f-4d93-baa0-3c9cacc8f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244783225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1244783225
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2736514204
Short name T516
Test name
Test status
Simulation time 853369972 ps
CPU time 6.63 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:35:30 PM PDT 24
Peak memory 216708 kb
Host smart-ea9c5171-52b9-4293-9192-4e2957e1bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736514204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2736514204
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1112773026
Short name T859
Test name
Test status
Simulation time 57151443 ps
CPU time 0.82 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:35:24 PM PDT 24
Peak memory 206324 kb
Host smart-08728918-0a37-47cf-9ba6-1f75c14992fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112773026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1112773026
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2987706073
Short name T703
Test name
Test status
Simulation time 8130264120 ps
CPU time 10.83 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 240208 kb
Host smart-25e90e44-44f7-450c-bd48-200e0274b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987706073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2987706073
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2168989050
Short name T338
Test name
Test status
Simulation time 38639534 ps
CPU time 0.7 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:23 PM PDT 24
Peak memory 205216 kb
Host smart-f1b2423b-c2e6-4664-add1-ce80138c7ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168989050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
168989050
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3157678669
Short name T390
Test name
Test status
Simulation time 3221875054 ps
CPU time 3.68 seconds
Started Jul 31 07:35:24 PM PDT 24
Finished Jul 31 07:35:28 PM PDT 24
Peak memory 224836 kb
Host smart-1197afec-8258-42fa-b867-2618c02b4efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157678669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3157678669
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1883470959
Short name T897
Test name
Test status
Simulation time 34162299 ps
CPU time 0.8 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:23 PM PDT 24
Peak memory 205972 kb
Host smart-513df139-90d2-4945-a7dc-e98f662dfa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883470959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1883470959
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3254905029
Short name T246
Test name
Test status
Simulation time 136347788981 ps
CPU time 273.6 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:39:57 PM PDT 24
Peak memory 264472 kb
Host smart-e9d0cab3-bd22-40fb-bb39-0ff83d1bc14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254905029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3254905029
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3402927340
Short name T784
Test name
Test status
Simulation time 1551191348 ps
CPU time 20.43 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:42 PM PDT 24
Peak memory 240832 kb
Host smart-07376e52-66c6-425b-a910-67130c2f49cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402927340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3402927340
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.959994734
Short name T138
Test name
Test status
Simulation time 6629766006 ps
CPU time 104.14 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:37:06 PM PDT 24
Peak memory 256884 kb
Host smart-18179779-2294-4fba-8b4d-9e04d5c3238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959994734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
959994734
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2514244254
Short name T771
Test name
Test status
Simulation time 211602702 ps
CPU time 3.8 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:26 PM PDT 24
Peak memory 233236 kb
Host smart-81cdf220-7c28-4c02-8326-a0b7b816a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514244254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2514244254
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1303552135
Short name T283
Test name
Test status
Simulation time 4778549494 ps
CPU time 60.99 seconds
Started Jul 31 07:35:23 PM PDT 24
Finished Jul 31 07:36:24 PM PDT 24
Peak memory 249552 kb
Host smart-439351b4-db7d-4055-876d-7c7d62045183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303552135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1303552135
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1996923005
Short name T377
Test name
Test status
Simulation time 21847288533 ps
CPU time 17.45 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:39 PM PDT 24
Peak memory 233128 kb
Host smart-2c22c4a2-6640-489c-8ad1-c1726463d867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996923005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1996923005
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.646797079
Short name T489
Test name
Test status
Simulation time 122980249 ps
CPU time 2.49 seconds
Started Jul 31 07:35:24 PM PDT 24
Finished Jul 31 07:35:26 PM PDT 24
Peak memory 232848 kb
Host smart-954a2ae8-a330-4f0b-ba41-60f841056b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646797079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.646797079
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3564274702
Short name T777
Test name
Test status
Simulation time 583770474 ps
CPU time 4.73 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:35 PM PDT 24
Peak memory 224808 kb
Host smart-af89c307-35f9-4898-807d-a2266aa36612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564274702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3564274702
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.295041207
Short name T239
Test name
Test status
Simulation time 4239166834 ps
CPU time 13.7 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:43 PM PDT 24
Peak memory 233160 kb
Host smart-0ad1da94-3e5d-4a72-b8b2-38164dd528d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295041207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.295041207
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.591663157
Short name T144
Test name
Test status
Simulation time 2181427776 ps
CPU time 6.24 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 219608 kb
Host smart-516f953d-daa3-4215-8700-75ad17348739
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=591663157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.591663157
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3140697303
Short name T12
Test name
Test status
Simulation time 59024273 ps
CPU time 1.09 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:32 PM PDT 24
Peak memory 207540 kb
Host smart-91fe96f0-58a0-4ccc-a695-2caf3aeba199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140697303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3140697303
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3497483966
Short name T1006
Test name
Test status
Simulation time 933846510 ps
CPU time 12.47 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 216620 kb
Host smart-b9c58f76-82ae-4258-90e8-54c2508317c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497483966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3497483966
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.22838580
Short name T644
Test name
Test status
Simulation time 2296924352 ps
CPU time 7.84 seconds
Started Jul 31 07:35:21 PM PDT 24
Finished Jul 31 07:35:29 PM PDT 24
Peak memory 216824 kb
Host smart-bdd3b297-c461-4011-a9a1-9dcb2806404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22838580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.22838580
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2678911062
Short name T310
Test name
Test status
Simulation time 302366667 ps
CPU time 4.25 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:27 PM PDT 24
Peak memory 216652 kb
Host smart-1bdf5f6c-2a8d-4e2c-9b86-0bba93d64eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678911062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2678911062
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4199211483
Short name T818
Test name
Test status
Simulation time 27123620 ps
CPU time 0.69 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:22 PM PDT 24
Peak memory 205956 kb
Host smart-a135bcd9-bd18-425b-9007-e456f0fe2bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199211483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4199211483
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.752881325
Short name T384
Test name
Test status
Simulation time 2891007577 ps
CPU time 8.62 seconds
Started Jul 31 07:35:22 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 224964 kb
Host smart-57a89078-eaa0-4938-a777-65b23485cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752881325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.752881325
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2821963092
Short name T333
Test name
Test status
Simulation time 21637098 ps
CPU time 0.72 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:32 PM PDT 24
Peak memory 205768 kb
Host smart-c11a42cd-e128-4040-82c7-1a5fbdf6100c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821963092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
821963092
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.748602993
Short name T701
Test name
Test status
Simulation time 207212211 ps
CPU time 3.98 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:34 PM PDT 24
Peak memory 233144 kb
Host smart-485fc0a5-c059-4f9d-aa18-4140b05ffad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748602993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.748602993
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3946327277
Short name T675
Test name
Test status
Simulation time 13585202 ps
CPU time 0.77 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 206920 kb
Host smart-3bdb5380-37f9-4f02-9662-db992fed3fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946327277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3946327277
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1105805994
Short name T269
Test name
Test status
Simulation time 11224115908 ps
CPU time 157.07 seconds
Started Jul 31 07:35:35 PM PDT 24
Finished Jul 31 07:38:12 PM PDT 24
Peak memory 264796 kb
Host smart-af8f6145-e9d5-4f53-b430-3bac064632f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105805994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1105805994
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3220449663
Short name T744
Test name
Test status
Simulation time 67681681962 ps
CPU time 122.44 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:37:31 PM PDT 24
Peak memory 256124 kb
Host smart-044ca770-9093-42d0-bd7d-91edd0151118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220449663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3220449663
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3452442202
Short name T465
Test name
Test status
Simulation time 13816085057 ps
CPU time 128.81 seconds
Started Jul 31 07:35:33 PM PDT 24
Finished Jul 31 07:37:42 PM PDT 24
Peak memory 249652 kb
Host smart-f0d707bd-5a61-4a91-a0c5-bf2a24d4e8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452442202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3452442202
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4206836272
Short name T210
Test name
Test status
Simulation time 300821809 ps
CPU time 8.5 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 235248 kb
Host smart-f5bf92e4-0a62-4506-9557-e8ea9aa32cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206836272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4206836272
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1014604828
Short name T437
Test name
Test status
Simulation time 1697938720 ps
CPU time 3.88 seconds
Started Jul 31 07:35:34 PM PDT 24
Finished Jul 31 07:35:38 PM PDT 24
Peak memory 224884 kb
Host smart-d1a3534d-65c8-4630-81f8-f09ed57848f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014604828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1014604828
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.56715787
Short name T527
Test name
Test status
Simulation time 2276522118 ps
CPU time 12.44 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:43 PM PDT 24
Peak memory 238364 kb
Host smart-97053dfd-ae11-4dc1-9842-40f3134949d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56715787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.56715787
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3982735211
Short name T203
Test name
Test status
Simulation time 2178062567 ps
CPU time 7.13 seconds
Started Jul 31 07:35:29 PM PDT 24
Finished Jul 31 07:35:37 PM PDT 24
Peak memory 224928 kb
Host smart-0889d9ce-2521-41c7-ad7c-5b9efaabdbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982735211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3982735211
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2107742096
Short name T595
Test name
Test status
Simulation time 527549495 ps
CPU time 6.14 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 220980 kb
Host smart-6ad851fc-9b29-4679-ac6a-235583323d96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107742096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2107742096
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4063075153
Short name T177
Test name
Test status
Simulation time 52514035021 ps
CPU time 141.94 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:37:54 PM PDT 24
Peak memory 253776 kb
Host smart-73c8c564-133b-4fdd-bd0b-0b29eaa6577b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063075153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4063075153
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2704679335
Short name T704
Test name
Test status
Simulation time 20632240811 ps
CPU time 22.66 seconds
Started Jul 31 07:35:27 PM PDT 24
Finished Jul 31 07:35:50 PM PDT 24
Peak memory 216852 kb
Host smart-5a50c437-4c2b-46f8-afe0-e2505e1ec907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704679335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2704679335
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3318313579
Short name T750
Test name
Test status
Simulation time 3711732143 ps
CPU time 8.97 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 216692 kb
Host smart-99bb038b-7a87-426b-ba2b-95d15d9e992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318313579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3318313579
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2306981095
Short name T438
Test name
Test status
Simulation time 25603626 ps
CPU time 1.67 seconds
Started Jul 31 07:35:28 PM PDT 24
Finished Jul 31 07:35:30 PM PDT 24
Peak memory 216636 kb
Host smart-3dfd2168-5e9c-4ea5-a090-35f4d8c4d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306981095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2306981095
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1017138315
Short name T26
Test name
Test status
Simulation time 35110564 ps
CPU time 0.81 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 206432 kb
Host smart-fdd6efc1-17ae-48c5-b62e-ab4d216768f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017138315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1017138315
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2627534542
Short name T711
Test name
Test status
Simulation time 2737616512 ps
CPU time 10.5 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:41 PM PDT 24
Peak memory 233152 kb
Host smart-3ab89494-0d8e-466e-b87f-fcce50ad033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627534542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2627534542
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1907875799
Short name T604
Test name
Test status
Simulation time 55849241 ps
CPU time 0.71 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 205888 kb
Host smart-ab6b4741-b9cc-4499-a62f-8caf87c959cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907875799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
907875799
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3254455486
Short name T223
Test name
Test status
Simulation time 60769929 ps
CPU time 3.08 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:34 PM PDT 24
Peak memory 233084 kb
Host smart-32ce815f-43bf-4eee-8e5a-19353a1dbb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254455486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3254455486
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4280079926
Short name T503
Test name
Test status
Simulation time 18118220 ps
CPU time 0.75 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 206288 kb
Host smart-91269919-f4f6-475c-9273-972e5022a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280079926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4280079926
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2411161655
Short name T133
Test name
Test status
Simulation time 864089733 ps
CPU time 8.3 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 235392 kb
Host smart-25ac856f-2a54-4b96-965b-9455aee1db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411161655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2411161655
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2751515762
Short name T999
Test name
Test status
Simulation time 20010464901 ps
CPU time 248.47 seconds
Started Jul 31 07:35:28 PM PDT 24
Finished Jul 31 07:39:36 PM PDT 24
Peak memory 265188 kb
Host smart-9d6c6cb6-9bb3-4b37-a3b7-b9d3012290cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751515762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2751515762
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4100833018
Short name T50
Test name
Test status
Simulation time 8537795511 ps
CPU time 63.53 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:36:34 PM PDT 24
Peak memory 249656 kb
Host smart-90f16e4c-b4e3-4b28-afd5-43769185f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100833018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4100833018
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.917781301
Short name T320
Test name
Test status
Simulation time 907613648 ps
CPU time 9.51 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 241288 kb
Host smart-8d1057ea-6662-4f02-8e4f-c66ab65aae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917781301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.917781301
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2395033063
Short name T335
Test name
Test status
Simulation time 37580112 ps
CPU time 0.74 seconds
Started Jul 31 07:35:32 PM PDT 24
Finished Jul 31 07:35:33 PM PDT 24
Peak memory 216140 kb
Host smart-53d267e0-18af-4d5f-a40c-bdcf04392a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395033063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2395033063
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2755760942
Short name T639
Test name
Test status
Simulation time 2556318060 ps
CPU time 16.31 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:46 PM PDT 24
Peak memory 224868 kb
Host smart-29da721f-3f69-40ed-a0b4-aec169d24983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755760942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2755760942
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2714396350
Short name T709
Test name
Test status
Simulation time 68441638 ps
CPU time 2.17 seconds
Started Jul 31 07:35:34 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 233100 kb
Host smart-af997258-e2de-467e-a47c-58813acbf57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714396350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2714396350
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2797418040
Short name T416
Test name
Test status
Simulation time 1859189080 ps
CPU time 7.92 seconds
Started Jul 31 07:35:33 PM PDT 24
Finished Jul 31 07:35:41 PM PDT 24
Peak memory 233156 kb
Host smart-ee9be236-8080-4f92-900e-8718083804e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797418040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2797418040
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2157391004
Short name T187
Test name
Test status
Simulation time 1943544367 ps
CPU time 8.64 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:40 PM PDT 24
Peak memory 224880 kb
Host smart-e6f60c67-b615-422f-8023-11f750371081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157391004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2157391004
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.334832656
Short name T145
Test name
Test status
Simulation time 147744555 ps
CPU time 4.26 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:35 PM PDT 24
Peak memory 223468 kb
Host smart-bceefbea-0119-4a9a-9a8d-ce856c1b71c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=334832656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.334832656
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3045670319
Short name T434
Test name
Test status
Simulation time 12263429 ps
CPU time 0.72 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:32 PM PDT 24
Peak memory 206132 kb
Host smart-6fe36fc4-5f48-44a5-8d2a-c0632bb30a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045670319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3045670319
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1398311910
Short name T770
Test name
Test status
Simulation time 26244545506 ps
CPU time 16.88 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:47 PM PDT 24
Peak memory 216876 kb
Host smart-ea83e38d-a3db-47fe-990a-8f75ab82099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398311910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1398311910
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3266344699
Short name T408
Test name
Test status
Simulation time 97420942 ps
CPU time 0.74 seconds
Started Jul 31 07:35:30 PM PDT 24
Finished Jul 31 07:35:31 PM PDT 24
Peak memory 206324 kb
Host smart-498679eb-8946-476b-baf1-a1acd7cf9c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266344699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3266344699
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3914064096
Short name T482
Test name
Test status
Simulation time 220323141 ps
CPU time 0.91 seconds
Started Jul 31 07:35:35 PM PDT 24
Finished Jul 31 07:35:36 PM PDT 24
Peak memory 206312 kb
Host smart-a7947faf-dcfa-46c7-ad93-b89a45df89d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914064096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3914064096
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.359875684
Short name T236
Test name
Test status
Simulation time 11822729484 ps
CPU time 8.23 seconds
Started Jul 31 07:35:31 PM PDT 24
Finished Jul 31 07:35:39 PM PDT 24
Peak memory 224868 kb
Host smart-ddeb13b9-4b6e-4d2c-be48-32fd46416c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359875684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.359875684
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%