Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3706732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4309321

1

T1

953

T2

2904

T3

876

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4527886	1			T1	143		T2	4033		T3	3
values[0x0]	1743460	1			T1	452		T2	438		T3	470
values[0x1]	1744707	1			T1	436		T2	453		T3	409

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2640907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5375146

1

T1

967

T2

3282

T3

876

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31489	1			T2	30		T3	2		T4	431
valid_sources[0x01]	31106	1			T2	14		T3	5		T4	471
valid_sources[0x02]	29871	1			T2	21		T3	3		T4	450
valid_sources[0x03]	32198	1			T2	20		T3	3		T4	451
valid_sources[0x04]	32192	1			T2	9		T3	4		T4	444
valid_sources[0x05]	30845	1			T2	22		T3	1		T4	415
valid_sources[0x06]	29710	1			T2	14		T3	5		T4	450
valid_sources[0x07]	31158	1			T2	20		T3	1		T4	423
valid_sources[0x08]	30654	1			T2	23		T3	8		T4	454
valid_sources[0x09]	28838	1			T2	6		T3	3		T4	474
valid_sources[0x0a]	30487	1			T2	23		T3	4		T4	468
valid_sources[0x0b]	31394	1			T2	12		T3	4		T4	439
valid_sources[0x0c]	28826	1			T2	16		T3	5		T4	452
valid_sources[0x0d]	29299	1			T2	21		T3	2		T4	461
valid_sources[0x0e]	31268	1			T2	16		T3	3		T4	480
valid_sources[0x0f]	28069	1			T2	21		T3	3		T4	425
valid_sources[0x10]	30537	1			T2	19		T3	1		T4	417
valid_sources[0x11]	28785	1			T2	28		T4	427		T10	40
valid_sources[0x12]	30949	1			T2	16		T3	9		T4	415
valid_sources[0x13]	30346	1			T2	18		T4	414		T10	66
valid_sources[0x14]	31312	1			T2	11		T3	3		T4	441
valid_sources[0x15]	30606	1			T2	17		T3	8		T4	429
valid_sources[0x16]	35554	1			T2	25		T3	1		T4	439
valid_sources[0x17]	31392	1			T2	18		T3	2		T4	473
valid_sources[0x18]	27719	1			T2	26		T3	7		T4	420
valid_sources[0x19]	32313	1			T2	13		T3	1		T4	426
valid_sources[0x1a]	27806	1			T2	17		T3	3		T4	441
valid_sources[0x1b]	30791	1			T2	12		T3	5		T4	438
valid_sources[0x1c]	28333	1			T2	20		T3	6		T4	435
valid_sources[0x1d]	28934	1			T2	20		T3	1		T4	456
valid_sources[0x1e]	27714	1			T2	24		T3	3		T4	431
valid_sources[0x1f]	36293	1			T2	18		T3	2		T4	463
valid_sources[0x20]	31421	1			T2	19		T3	9		T4	453
valid_sources[0x21]	27393	1			T2	10		T3	1		T4	450
valid_sources[0x22]	32503	1			T2	9		T3	1		T4	447
valid_sources[0x23]	28825	1			T2	22		T3	3		T4	428
valid_sources[0x24]	28970	1			T2	15		T3	8		T4	428
valid_sources[0x25]	28130	1			T2	8		T3	5		T4	404
valid_sources[0x26]	30598	1			T2	31		T3	3		T4	438
valid_sources[0x27]	27939	1			T2	18		T3	7		T4	442
valid_sources[0x28]	33522	1			T2	15		T3	9		T4	435
valid_sources[0x29]	34576	1			T2	21		T3	3		T4	452
valid_sources[0x2a]	33888	1			T2	16		T3	8		T4	435
valid_sources[0x2b]	29123	1			T2	24		T3	4		T4	456
valid_sources[0x2c]	29181	1			T2	24		T3	10		T4	461
valid_sources[0x2d]	28951	1			T2	21		T3	4		T4	449
valid_sources[0x2e]	34149	1			T2	18		T3	1		T4	495
valid_sources[0x2f]	29244	1			T2	14		T4	401		T10	39
valid_sources[0x30]	31363	1			T2	13		T3	4		T4	463
valid_sources[0x31]	35005	1			T2	16		T3	2		T4	440
valid_sources[0x32]	31450	1			T2	20		T3	6		T4	406
valid_sources[0x33]	29641	1			T2	14		T3	6		T4	440
valid_sources[0x34]	26466	1			T2	15		T3	4		T4	434
valid_sources[0x35]	28578	1			T2	31		T3	3		T4	439
valid_sources[0x36]	27620	1			T2	18		T3	3		T4	507
valid_sources[0x37]	31342	1			T2	21		T3	1		T4	444
valid_sources[0x38]	28700	1			T2	14		T3	6		T4	435
valid_sources[0x39]	33630	1			T2	17		T3	2		T4	458
valid_sources[0x3a]	28148	1			T2	21		T3	1		T4	432
valid_sources[0x3b]	31762	1			T2	21		T3	2		T4	417
valid_sources[0x3c]	31991	1			T2	16		T3	7		T4	441
valid_sources[0x3d]	28896	1			T2	16		T3	1		T4	436
valid_sources[0x3e]	36847	1			T2	15		T3	5		T4	422
valid_sources[0x3f]	28309	1			T2	10		T3	5		T4	450
valid_sources[0x40]	28739	1			T2	20		T3	7		T4	464
valid_sources[0x41]	29173	1			T2	21		T3	3		T4	462
valid_sources[0x42]	40583	1			T2	22		T3	2		T4	472
valid_sources[0x43]	29341	1			T2	21		T3	2		T4	458
valid_sources[0x44]	26667	1			T2	17		T3	4		T4	424
valid_sources[0x45]	30393	1			T2	14		T3	4		T4	415
valid_sources[0x46]	28503	1			T2	5		T3	3		T4	483
valid_sources[0x47]	27804	1			T2	29		T4	427		T10	51
valid_sources[0x48]	33487	1			T2	10		T3	6		T4	426
valid_sources[0x49]	28520	1			T2	26		T3	3		T4	448
valid_sources[0x4a]	27980	1			T2	17		T3	6		T4	438
valid_sources[0x4b]	34681	1			T2	16		T3	6		T4	438
valid_sources[0x4c]	30831	1			T2	16		T3	10		T4	449
valid_sources[0x4d]	35476	1			T2	17		T3	9		T4	403
valid_sources[0x4e]	31485	1			T2	22		T3	4		T4	402
valid_sources[0x4f]	32706	1			T2	26		T3	4		T4	457
valid_sources[0x50]	29374	1			T2	18		T3	4		T4	446
valid_sources[0x51]	29954	1			T2	10		T3	4		T4	505
valid_sources[0x52]	27834	1			T2	12		T3	6		T4	457
valid_sources[0x53]	28986	1			T2	29		T3	3		T4	424
valid_sources[0x54]	28307	1			T2	17		T3	2		T4	449
valid_sources[0x55]	29502	1			T2	22		T4	410		T10	36
valid_sources[0x56]	26723	1			T2	13		T3	3		T4	455
valid_sources[0x57]	29605	1			T2	15		T4	399		T10	39
valid_sources[0x58]	29628	1			T2	26		T3	6		T4	436
valid_sources[0x59]	28193	1			T2	20		T3	1		T4	472
valid_sources[0x5a]	36232	1			T2	31		T4	435		T10	54
valid_sources[0x5b]	94096	1			T2	15		T3	4		T4	406
valid_sources[0x5c]	29716	1			T2	19		T4	429		T10	43
valid_sources[0x5d]	31453	1			T2	15		T4	439		T10	40
valid_sources[0x5e]	29167	1			T2	31		T3	3		T4	438
valid_sources[0x5f]	28180	1			T2	28		T3	7		T4	468
valid_sources[0x60]	31934	1			T2	27		T3	6		T4	421
valid_sources[0x61]	26293	1			T2	15		T3	5		T4	440
valid_sources[0x62]	29893	1			T2	11		T3	1		T4	458
valid_sources[0x63]	36985	1			T2	21		T3	9		T4	459
valid_sources[0x64]	27360	1			T2	20		T3	2		T4	420
valid_sources[0x65]	29250	1			T2	21		T3	4		T4	413
valid_sources[0x66]	28623	1			T2	13		T3	4		T4	433
valid_sources[0x67]	28563	1			T2	19		T3	3		T4	417
valid_sources[0x68]	30665	1			T2	12		T3	6		T4	463
valid_sources[0x69]	31281	1			T2	23		T3	1		T4	428
valid_sources[0x6a]	48365	1			T2	13		T3	5		T4	453
valid_sources[0x6b]	28998	1			T2	27		T3	1		T4	457
valid_sources[0x6c]	53731	1			T2	7		T3	2		T4	439
valid_sources[0x6d]	28384	1			T2	19		T3	4		T4	410
valid_sources[0x6e]	38518	1			T2	24		T3	1		T4	436
valid_sources[0x6f]	27870	1			T2	30		T3	5		T4	454
valid_sources[0x70]	29182	1			T2	11		T3	3		T4	435
valid_sources[0x71]	32355	1			T2	25		T3	6		T4	461
valid_sources[0x72]	28428	1			T2	9		T3	5		T4	401
valid_sources[0x73]	30630	1			T2	12		T3	5		T4	454
valid_sources[0x74]	31641	1			T2	17		T3	1		T4	465
valid_sources[0x75]	28252	1			T2	21		T3	2		T4	413
valid_sources[0x76]	31348	1			T2	13		T3	5		T4	429
valid_sources[0x77]	29121	1			T2	8		T3	8		T4	407
valid_sources[0x78]	31504	1			T2	22		T3	3		T4	397
valid_sources[0x79]	33461	1			T2	22		T3	3		T4	423
valid_sources[0x7a]	29078	1			T2	10		T4	418		T7	128
valid_sources[0x7b]	29662	1			T2	15		T3	1		T4	467
valid_sources[0x7c]	29610	1			T2	23		T3	10		T4	453
valid_sources[0x7d]	27501	1			T2	30		T3	1		T4	427
valid_sources[0x7e]	30872	1			T2	12		T4	428		T10	28
valid_sources[0x7f]	34059	1			T2	15		T3	1		T4	472
valid_sources[0x80]	27579	1			T2	14		T3	4		T4	470

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1151110

1

T1

67

T2

2024

T4

5896

values[0x0]

all_enables

biggest_size

1590918

1

T1

451

T2

432

T3

468

values[0x1]

all_enables

biggest_size

1567293

1

T1

435

T2

448

T3

408