Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3734665

1

T1

78

T2

2020

T3

6

full_word

4311079

1

T1

953

T2

2904

T3

876

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8045414	1			T1	1031		T2	4924		T3	882
auto[TlIntgErrCmd]	120	1			T85	6		T86	7		T87	3
auto[TlIntgErrData]	98	1			T85	2		T86	7		T87	2
auto[TlIntgErrBoth]	112	1			T85	2		T86	6		T87	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4534790

1

T1

143

T2

4033

T3

3

auto[1]

3510954

1

T1

888

T2

891

T3

879

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3383015	1			T1	76		T2	2009		T3	3
auto[TlIntgErrNone]	partial	auto[1]	351345	1			T1	2		T2	11		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1151622	1			T1	67		T2	2024		T4	5896
auto[TlIntgErrNone]	full_word	auto[1]	3159432	1			T1	886		T2	880		T3	876
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T85	4		T86	4		T87	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T85	2		T86	3		T87	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T129	1		T152	1		T155	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T157	2		T158	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T86	3		T87	1		T126	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T85	2		T86	4		T87	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T126	2		T157	1		T153	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T158	1		T153	1		T156	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T85	2		T86	4		T87	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T86	2		T87	2		T126	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T160	1		T161	1		T155	3
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T155	1		T159	1		T162	2