Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T26
1	0	Covered	T4,T11,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Unreachable
1	1	Covered	T4,T11,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T29
1	0	Covered	T4,T11,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T11,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T29
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	757913319	606030142	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	757913319	3646598	0	0
GntImpliesValid_A	757913319	3646598	0	0
GrantKnown_A	757913319	606030142	0	0
IdxKnown_A	757913319	606030142	0	0
IndexIsCorrect_A	757913319	3646598	0	0
LockArbDecision_A	757913319	0	0	0
NoReadyValidNoGrant_A	757913319	0	0	0
ReadyAndValidImplyGrant_A	757913319	3646598	0	0
ReqAndReadyImplyGrant_A	757913319	3646598	0	0
ReqImpliesValid_A	757913319	3646598	0	0
ReqStaysHighUntilGranted0_M	757913319	0	0	0
RoundRobin_A	757913319	7	0	956
ValidKnown_A	757913319	606030142	0	0
gen_data_port_assertion.DataFlow_A	757913319	3646598	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	606030142	0	0
T1	15842	15765	0	0
T2	164294	164243	0	0
T3	240162	240099	0	0
T4	784296	876066	0	0
T5	10619	9010	0	0
T6	138583	82467	0	0
T7	125016	70816	0	0
T8	332344	285425	0	0
T9	11579	8317	0	0
T10	555894	464781	0	0
T11	776150	771581	0	0
T12	438	48	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	606030142	0	0
T1	15842	15765	0	0
T2	164294	164243	0	0
T3	240162	240099	0	0
T4	784296	876066	0	0
T5	10619	9010	0	0
T6	138583	82467	0	0
T7	125016	70816	0	0
T8	332344	285425	0	0
T9	11579	8317	0	0
T10	555894	464781	0	0
T11	776150	771581	0	0
T12	438	48	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	606030142	0	0
T1	15842	15765	0	0
T2	164294	164243	0	0
T3	240162	240099	0	0
T4	784296	876066	0	0
T5	10619	9010	0	0
T6	138583	82467	0	0
T7	125016	70816	0	0
T8	332344	285425	0	0
T9	11579	8317	0	0
T10	555894	464781	0	0
T11	776150	771581	0	0
T12	438	48	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	7	0	956
T13	939037	0	0	1
T26	284694	1	0	1
T27	3612	0	0	1
T28	62080	0	0	1
T32	267658	0	0	1
T34	419235	0	0	1
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	131068	0	0	1
T47	345317	0	0	1
T48	1667	0	0	1
T49	1839	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	606030142	0	0
T1	15842	15765	0	0
T2	164294	164243	0	0
T3	240162	240099	0	0
T4	784296	876066	0	0
T5	10619	9010	0	0
T6	138583	82467	0	0
T7	125016	70816	0	0
T8	332344	285425	0	0
T9	11579	8317	0	0
T10	555894	464781	0	0
T11	776150	771581	0	0
T12	438	48	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757913319	3646598	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	784296	32779	0	0
T5	10619	0	0	0
T6	138583	1344	0	0
T7	125016	1344	0	0
T8	332344	832	0	0
T9	11579	0	0	0
T10	555894	832	0	0
T11	1552300	19381	0	0
T12	876	832	0	0
T13	0	14848	0	0
T26	0	6528	0	0
T27	0	207	0	0
T28	0	2101	0	0
T29	0	5481	0	0
T30	0	5005	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	4585	0	0
T35	0	6399	0	0
T37	166680	0	0	0
T38	0	6005	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T26
1	0	Covered	T4,T11,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Unreachable
1	1	Covered	T4,T11,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T26
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150503477	28406973	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	150503477	596151	0	0
GntImpliesValid_A	150503477	596151	0	0
GrantKnown_A	150503477	28406973	0	0
IdxKnown_A	150503477	28406973	0	0
IndexIsCorrect_A	150503477	596151	0	0
LockArbDecision_A	150503477	0	0	0
NoReadyValidNoGrant_A	150503477	0	0	0
ReadyAndValidImplyGrant_A	150503477	596151	0	0
ReqAndReadyImplyGrant_A	150503477	596151	0	0
ReqImpliesValid_A	150503477	596151	0	0
ReqStaysHighUntilGranted0_M	150503477	0	0	0
RoundRobin_A	150503477	0	0	0
ValidKnown_A	150503477	28406973	0	0
gen_data_port_assertion.DataFlow_A	150503477	596151	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	28406973	0	0
T4	128525	246152	0	0
T5	1167	792	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	936	0	0
T10	90940	0	0	0
T11	776150	62840	0	0
T12	438	0	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	28406973	0	0
T4	128525	246152	0	0
T5	1167	792	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	936	0	0
T10	90940	0	0	0
T11	776150	62840	0	0
T12	438	0	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	28406973	0	0
T4	128525	246152	0	0
T5	1167	792	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	936	0	0
T10	90940	0	0	0
T11	776150	62840	0	0
T12	438	0	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	28406973	0	0
T4	128525	246152	0	0
T5	1167	792	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	936	0	0
T10	90940	0	0	0
T11	776150	62840	0	0
T12	438	0	0	0
T13	0	465208	0	0
T24	0	66832	0	0
T25	0	648	0	0
T26	0	115624	0	0
T27	0	2920	0	0
T28	0	202176	0	0
T37	83340	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	596151	0	0
T4	128525	7382	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	3058	0	0
T12	438	0	0	0
T13	0	5633	0	0
T26	0	5046	0	0
T27	0	207	0	0
T28	0	2101	0	0
T30	0	5005	0	0
T34	0	2491	0	0
T35	0	992	0	0
T37	83340	0	0	0
T38	0	1491	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T29
1	0	Covered	T4,T11,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T11,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T29
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	150503477	120805497	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	150503477	844920	0	0
GntImpliesValid_A	150503477	844920	0	0
GrantKnown_A	150503477	120805497	0	0
IdxKnown_A	150503477	120805497	0	0
IndexIsCorrect_A	150503477	844920	0	0
LockArbDecision_A	150503477	0	0	0
NoReadyValidNoGrant_A	150503477	0	0	0
ReadyAndValidImplyGrant_A	150503477	844920	0	0
ReqAndReadyImplyGrant_A	150503477	844920	0	0
ReqImpliesValid_A	150503477	844920	0	0
ReqStaysHighUntilGranted0_M	150503477	0	0	0
RoundRobin_A	150503477	0	0	0
ValidKnown_A	150503477	120805497	0	0
gen_data_port_assertion.DataFlow_A	150503477	844920	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	120805497	0	0
T1	4208	4208	0	0
T2	20096	20096	0	0
T3	47348	47348	0	0
T4	128525	102681	0	0
T5	1167	0	0	0
T6	56036	56036	0	0
T7	54119	54119	0	0
T8	46848	46848	0	0
T9	2066	0	0	0
T10	90940	90826	0	0
T11	0	708741	0	0
T12	0	48	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	120805497	0	0
T1	4208	4208	0	0
T2	20096	20096	0	0
T3	47348	47348	0	0
T4	128525	102681	0	0
T5	1167	0	0	0
T6	56036	56036	0	0
T7	54119	54119	0	0
T8	46848	46848	0	0
T9	2066	0	0	0
T10	90940	90826	0	0
T11	0	708741	0	0
T12	0	48	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	120805497	0	0
T1	4208	4208	0	0
T2	20096	20096	0	0
T3	47348	47348	0	0
T4	128525	102681	0	0
T5	1167	0	0	0
T6	56036	56036	0	0
T7	54119	54119	0	0
T8	46848	46848	0	0
T9	2066	0	0	0
T10	90940	90826	0	0
T11	0	708741	0	0
T12	0	48	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	120805497	0	0
T1	4208	4208	0	0
T2	20096	20096	0	0
T3	47348	47348	0	0
T4	128525	102681	0	0
T5	1167	0	0	0
T6	56036	56036	0	0
T7	54119	54119	0	0
T8	46848	46848	0	0
T9	2066	0	0	0
T10	90940	90826	0	0
T11	0	708741	0	0
T12	0	48	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	150503477	844920	0	0
T4	128525	6808	0	0
T5	1167	0	0	0
T6	56036	0	0	0
T7	54119	0	0	0
T8	46848	0	0	0
T9	2066	0	0	0
T10	90940	0	0	0
T11	776150	7229	0	0
T12	438	0	0	0
T13	0	9215	0	0
T26	0	1482	0	0
T29	0	5481	0	0
T32	0	830	0	0
T33	0	8856	0	0
T34	0	2094	0	0
T35	0	5407	0	0
T37	83340	0	0	0
T38	0	4514	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T29
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	456906365	456817672	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	456906365	2205527	0	0
GntImpliesValid_A	456906365	2205527	0	0
GrantKnown_A	456906365	456817672	0	0
IdxKnown_A	456906365	456817672	0	0
IndexIsCorrect_A	456906365	2205527	0	0
LockArbDecision_A	456906365	0	0	0
NoReadyValidNoGrant_A	456906365	0	0	0
ReadyAndValidImplyGrant_A	456906365	2205527	0	0
ReqAndReadyImplyGrant_A	456906365	2205527	0	0
ReqImpliesValid_A	456906365	2205527	0	0
ReqStaysHighUntilGranted0_M	456906365	0	0	0
RoundRobin_A	456906365	7	0	956
ValidKnown_A	456906365	456817672	0	0
gen_data_port_assertion.DataFlow_A	456906365	2205527	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	456817672	0	0
T1	11634	11557	0	0
T2	144198	144147	0	0
T3	192814	192751	0	0
T4	527246	527233	0	0
T5	8285	8218	0	0
T6	26511	26431	0	0
T7	16778	16697	0	0
T8	238648	238577	0	0
T9	7447	7381	0	0
T10	374014	373955	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	456817672	0	0
T1	11634	11557	0	0
T2	144198	144147	0	0
T3	192814	192751	0	0
T4	527246	527233	0	0
T5	8285	8218	0	0
T6	26511	26431	0	0
T7	16778	16697	0	0
T8	238648	238577	0	0
T9	7447	7381	0	0
T10	374014	373955	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	456817672	0	0
T1	11634	11557	0	0
T2	144198	144147	0	0
T3	192814	192751	0	0
T4	527246	527233	0	0
T5	8285	8218	0	0
T6	26511	26431	0	0
T7	16778	16697	0	0
T8	238648	238577	0	0
T9	7447	7381	0	0
T10	374014	373955	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	7	0	956
T13	939037	0	0	1
T26	284694	1	0	1
T27	3612	0	0	1
T28	62080	0	0	1
T32	267658	0	0	1
T34	419235	0	0	1
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	131068	0	0	1
T47	345317	0	0	1
T48	1667	0	0	1
T49	1839	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	456817672	0	0
T1	11634	11557	0	0
T2	144198	144147	0	0
T3	192814	192751	0	0
T4	527246	527233	0	0
T5	8285	8218	0	0
T6	26511	26431	0	0
T7	16778	16697	0	0
T8	238648	238577	0	0
T9	7447	7381	0	0
T10	374014	373955	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456906365	2205527	0	0
T1	11634	832	0	0
T2	144198	832	0	0
T3	192814	832	0	0
T4	527246	18589	0	0
T5	8285	0	0	0
T6	26511	1344	0	0
T7	16778	1344	0	0
T8	238648	832	0	0
T9	7447	0	0	0
T10	374014	832	0	0
T11	0	9094	0	0
T12	0	832	0	0