Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
3920 | 
0 | 
0 | 
| T53 | 
9060 | 
285 | 
0 | 
0 | 
| T54 | 
20371 | 
360 | 
0 | 
0 | 
| T55 | 
17871 | 
127 | 
0 | 
0 | 
| T84 | 
12284 | 
118 | 
0 | 
0 | 
| T85 | 
25898 | 
2 | 
0 | 
0 | 
| T88 | 
7266 | 
255 | 
0 | 
0 | 
| T90 | 
5092 | 
195 | 
0 | 
0 | 
| T94 | 
3671 | 
6 | 
0 | 
0 | 
| T95 | 
8000 | 
8 | 
0 | 
0 | 
| T96 | 
4242 | 
1 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2463 | 
0 | 
0 | 
| T96 | 
4242 | 
11 | 
0 | 
0 | 
| T99 | 
270418 | 
651 | 
0 | 
0 | 
| T115 | 
13590 | 
61 | 
0 | 
0 | 
| T124 | 
4417 | 
3 | 
0 | 
0 | 
| T125 | 
76694 | 
505 | 
0 | 
0 | 
| T126 | 
61233 | 
33 | 
0 | 
0 | 
| T127 | 
20638 | 
45 | 
0 | 
0 | 
| T128 | 
11398 | 
20 | 
0 | 
0 | 
| T129 | 
35738 | 
29 | 
0 | 
0 | 
| T130 | 
4905 | 
1 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2525 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
668 | 
0 | 
0 | 
| T106 | 
6112 | 
4 | 
0 | 
0 | 
| T115 | 
13590 | 
29 | 
0 | 
0 | 
| T124 | 
4417 | 
2 | 
0 | 
0 | 
| T125 | 
76694 | 
526 | 
0 | 
0 | 
| T126 | 
61233 | 
50 | 
0 | 
0 | 
| T127 | 
20638 | 
70 | 
0 | 
0 | 
| T128 | 
11398 | 
17 | 
0 | 
0 | 
| T129 | 
35738 | 
49 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
3074 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
715 | 
0 | 
0 | 
| T106 | 
6112 | 
1 | 
0 | 
0 | 
| T115 | 
13590 | 
78 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
573 | 
0 | 
0 | 
| T126 | 
61233 | 
70 | 
0 | 
0 | 
| T127 | 
20638 | 
40 | 
0 | 
0 | 
| T128 | 
11398 | 
17 | 
0 | 
0 | 
| T129 | 
35738 | 
56 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
9337 | 
0 | 
0 | 
| T96 | 
4242 | 
11 | 
0 | 
0 | 
| T99 | 
270418 | 
641 | 
0 | 
0 | 
| T106 | 
6112 | 
140 | 
0 | 
0 | 
| T115 | 
13590 | 
67 | 
0 | 
0 | 
| T124 | 
4417 | 
3 | 
0 | 
0 | 
| T125 | 
76694 | 
522 | 
0 | 
0 | 
| T126 | 
61233 | 
628 | 
0 | 
0 | 
| T127 | 
20638 | 
24 | 
0 | 
0 | 
| T128 | 
11398 | 
22 | 
0 | 
0 | 
| T129 | 
35738 | 
588 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
9815 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
637 | 
0 | 
0 | 
| T106 | 
6112 | 
58 | 
0 | 
0 | 
| T115 | 
13590 | 
24 | 
0 | 
0 | 
| T124 | 
4417 | 
152 | 
0 | 
0 | 
| T125 | 
76694 | 
603 | 
0 | 
0 | 
| T126 | 
61233 | 
678 | 
0 | 
0 | 
| T127 | 
20638 | 
92 | 
0 | 
0 | 
| T128 | 
11398 | 
245 | 
0 | 
0 | 
| T129 | 
35738 | 
447 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
10129 | 
0 | 
0 | 
| T96 | 
4242 | 
137 | 
0 | 
0 | 
| T99 | 
270418 | 
693 | 
0 | 
0 | 
| T106 | 
6112 | 
79 | 
0 | 
0 | 
| T115 | 
13590 | 
66 | 
0 | 
0 | 
| T124 | 
4417 | 
100 | 
0 | 
0 | 
| T125 | 
76694 | 
545 | 
0 | 
0 | 
| T126 | 
61233 | 
624 | 
0 | 
0 | 
| T127 | 
20638 | 
32 | 
0 | 
0 | 
| T128 | 
11398 | 
145 | 
0 | 
0 | 
| T129 | 
35738 | 
677 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
10772 | 
0 | 
0 | 
| T96 | 
4242 | 
5 | 
0 | 
0 | 
| T99 | 
270418 | 
637 | 
0 | 
0 | 
| T106 | 
6112 | 
13 | 
0 | 
0 | 
| T115 | 
13590 | 
46 | 
0 | 
0 | 
| T124 | 
4417 | 
110 | 
0 | 
0 | 
| T125 | 
76694 | 
608 | 
0 | 
0 | 
| T126 | 
61233 | 
490 | 
0 | 
0 | 
| T127 | 
20638 | 
83 | 
0 | 
0 | 
| T128 | 
11398 | 
117 | 
0 | 
0 | 
| T129 | 
35738 | 
924 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
11165 | 
0 | 
0 | 
| T96 | 
4242 | 
86 | 
0 | 
0 | 
| T99 | 
270418 | 
710 | 
0 | 
0 | 
| T106 | 
6112 | 
9 | 
0 | 
0 | 
| T115 | 
13590 | 
45 | 
0 | 
0 | 
| T124 | 
4417 | 
9 | 
0 | 
0 | 
| T125 | 
76694 | 
537 | 
0 | 
0 | 
| T126 | 
61233 | 
699 | 
0 | 
0 | 
| T127 | 
20638 | 
77 | 
0 | 
0 | 
| T128 | 
11398 | 
128 | 
0 | 
0 | 
| T129 | 
35738 | 
934 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
10611 | 
0 | 
0 | 
| T96 | 
4242 | 
14 | 
0 | 
0 | 
| T99 | 
270418 | 
613 | 
0 | 
0 | 
| T106 | 
6112 | 
128 | 
0 | 
0 | 
| T115 | 
13590 | 
33 | 
0 | 
0 | 
| T124 | 
4417 | 
106 | 
0 | 
0 | 
| T125 | 
76694 | 
516 | 
0 | 
0 | 
| T126 | 
61233 | 
1090 | 
0 | 
0 | 
| T127 | 
20638 | 
89 | 
0 | 
0 | 
| T128 | 
11398 | 
260 | 
0 | 
0 | 
| T129 | 
35738 | 
843 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
9747 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
653 | 
0 | 
0 | 
| T106 | 
6112 | 
63 | 
0 | 
0 | 
| T115 | 
13590 | 
20 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
561 | 
0 | 
0 | 
| T126 | 
61233 | 
795 | 
0 | 
0 | 
| T127 | 
20638 | 
61 | 
0 | 
0 | 
| T128 | 
11398 | 
118 | 
0 | 
0 | 
| T129 | 
35738 | 
473 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
9680 | 
0 | 
0 | 
| T96 | 
4242 | 
7 | 
0 | 
0 | 
| T99 | 
270418 | 
676 | 
0 | 
0 | 
| T106 | 
6112 | 
73 | 
0 | 
0 | 
| T115 | 
13590 | 
31 | 
0 | 
0 | 
| T124 | 
4417 | 
127 | 
0 | 
0 | 
| T125 | 
76694 | 
523 | 
0 | 
0 | 
| T126 | 
61233 | 
640 | 
0 | 
0 | 
| T127 | 
20638 | 
32 | 
0 | 
0 | 
| T128 | 
11398 | 
251 | 
0 | 
0 | 
| T129 | 
35738 | 
394 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5479 | 
0 | 
0 | 
| T96 | 
4242 | 
5 | 
0 | 
0 | 
| T99 | 
270418 | 
700 | 
0 | 
0 | 
| T106 | 
6112 | 
14 | 
0 | 
0 | 
| T115 | 
13590 | 
33 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
603 | 
0 | 
0 | 
| T126 | 
61233 | 
327 | 
0 | 
0 | 
| T127 | 
20638 | 
75 | 
0 | 
0 | 
| T128 | 
11398 | 
24 | 
0 | 
0 | 
| T129 | 
35738 | 
294 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5528 | 
0 | 
0 | 
| T96 | 
4242 | 
4 | 
0 | 
0 | 
| T99 | 
270418 | 
611 | 
0 | 
0 | 
| T106 | 
6112 | 
4 | 
0 | 
0 | 
| T115 | 
13590 | 
68 | 
0 | 
0 | 
| T124 | 
4417 | 
62 | 
0 | 
0 | 
| T125 | 
76694 | 
501 | 
0 | 
0 | 
| T126 | 
61233 | 
165 | 
0 | 
0 | 
| T127 | 
20638 | 
64 | 
0 | 
0 | 
| T128 | 
11398 | 
22 | 
0 | 
0 | 
| T129 | 
35738 | 
260 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5346 | 
0 | 
0 | 
| T96 | 
4242 | 
10 | 
0 | 
0 | 
| T99 | 
270418 | 
681 | 
0 | 
0 | 
| T106 | 
6112 | 
8 | 
0 | 
0 | 
| T115 | 
13590 | 
17 | 
0 | 
0 | 
| T124 | 
4417 | 
38 | 
0 | 
0 | 
| T125 | 
76694 | 
511 | 
0 | 
0 | 
| T126 | 
61233 | 
382 | 
0 | 
0 | 
| T127 | 
20638 | 
86 | 
0 | 
0 | 
| T128 | 
11398 | 
70 | 
0 | 
0 | 
| T129 | 
35738 | 
236 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5065 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
642 | 
0 | 
0 | 
| T106 | 
6112 | 
45 | 
0 | 
0 | 
| T115 | 
13590 | 
45 | 
0 | 
0 | 
| T124 | 
4417 | 
1 | 
0 | 
0 | 
| T125 | 
76694 | 
545 | 
0 | 
0 | 
| T126 | 
61233 | 
306 | 
0 | 
0 | 
| T127 | 
20638 | 
83 | 
0 | 
0 | 
| T128 | 
11398 | 
74 | 
0 | 
0 | 
| T129 | 
35738 | 
112 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5784 | 
0 | 
0 | 
| T96 | 
4242 | 
43 | 
0 | 
0 | 
| T99 | 
270418 | 
666 | 
0 | 
0 | 
| T106 | 
6112 | 
12 | 
0 | 
0 | 
| T115 | 
13590 | 
42 | 
0 | 
0 | 
| T124 | 
4417 | 
53 | 
0 | 
0 | 
| T125 | 
76694 | 
609 | 
0 | 
0 | 
| T126 | 
61233 | 
431 | 
0 | 
0 | 
| T127 | 
20638 | 
67 | 
0 | 
0 | 
| T128 | 
11398 | 
98 | 
0 | 
0 | 
| T129 | 
35738 | 
296 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5116 | 
0 | 
0 | 
| T96 | 
4242 | 
1 | 
0 | 
0 | 
| T99 | 
270418 | 
657 | 
0 | 
0 | 
| T106 | 
6112 | 
5 | 
0 | 
0 | 
| T115 | 
13590 | 
17 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
567 | 
0 | 
0 | 
| T126 | 
61233 | 
201 | 
0 | 
0 | 
| T127 | 
20638 | 
86 | 
0 | 
0 | 
| T128 | 
11398 | 
119 | 
0 | 
0 | 
| T129 | 
35738 | 
186 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5884 | 
0 | 
0 | 
| T96 | 
4242 | 
29 | 
0 | 
0 | 
| T99 | 
270418 | 
703 | 
0 | 
0 | 
| T115 | 
13590 | 
34 | 
0 | 
0 | 
| T124 | 
4417 | 
54 | 
0 | 
0 | 
| T125 | 
76694 | 
587 | 
0 | 
0 | 
| T126 | 
61233 | 
240 | 
0 | 
0 | 
| T127 | 
20638 | 
56 | 
0 | 
0 | 
| T128 | 
11398 | 
64 | 
0 | 
0 | 
| T129 | 
35738 | 
249 | 
0 | 
0 | 
| T130 | 
4905 | 
41 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5799 | 
0 | 
0 | 
| T96 | 
4242 | 
7 | 
0 | 
0 | 
| T99 | 
270418 | 
671 | 
0 | 
0 | 
| T106 | 
6112 | 
1 | 
0 | 
0 | 
| T115 | 
13590 | 
26 | 
0 | 
0 | 
| T124 | 
4417 | 
8 | 
0 | 
0 | 
| T125 | 
76694 | 
600 | 
0 | 
0 | 
| T126 | 
61233 | 
321 | 
0 | 
0 | 
| T127 | 
20638 | 
94 | 
0 | 
0 | 
| T128 | 
11398 | 
100 | 
0 | 
0 | 
| T129 | 
35738 | 
281 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5387 | 
0 | 
0 | 
| T96 | 
4242 | 
51 | 
0 | 
0 | 
| T99 | 
270418 | 
663 | 
0 | 
0 | 
| T106 | 
6112 | 
27 | 
0 | 
0 | 
| T115 | 
13590 | 
35 | 
0 | 
0 | 
| T124 | 
4417 | 
48 | 
0 | 
0 | 
| T125 | 
76694 | 
538 | 
0 | 
0 | 
| T126 | 
61233 | 
298 | 
0 | 
0 | 
| T127 | 
20638 | 
52 | 
0 | 
0 | 
| T128 | 
11398 | 
61 | 
0 | 
0 | 
| T129 | 
35738 | 
251 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5406 | 
0 | 
0 | 
| T96 | 
4242 | 
59 | 
0 | 
0 | 
| T99 | 
270418 | 
708 | 
0 | 
0 | 
| T106 | 
6112 | 
12 | 
0 | 
0 | 
| T115 | 
13590 | 
48 | 
0 | 
0 | 
| T124 | 
4417 | 
69 | 
0 | 
0 | 
| T125 | 
76694 | 
507 | 
0 | 
0 | 
| T126 | 
61233 | 
360 | 
0 | 
0 | 
| T127 | 
20638 | 
53 | 
0 | 
0 | 
| T128 | 
11398 | 
24 | 
0 | 
0 | 
| T129 | 
35738 | 
113 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
6015 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
725 | 
0 | 
0 | 
| T106 | 
6112 | 
1 | 
0 | 
0 | 
| T115 | 
13590 | 
27 | 
0 | 
0 | 
| T124 | 
4417 | 
56 | 
0 | 
0 | 
| T125 | 
76694 | 
573 | 
0 | 
0 | 
| T126 | 
61233 | 
482 | 
0 | 
0 | 
| T127 | 
20638 | 
35 | 
0 | 
0 | 
| T128 | 
11398 | 
78 | 
0 | 
0 | 
| T129 | 
35738 | 
192 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5570 | 
0 | 
0 | 
| T96 | 
4242 | 
48 | 
0 | 
0 | 
| T99 | 
270418 | 
637 | 
0 | 
0 | 
| T106 | 
6112 | 
18 | 
0 | 
0 | 
| T115 | 
13590 | 
27 | 
0 | 
0 | 
| T124 | 
4417 | 
8 | 
0 | 
0 | 
| T125 | 
76694 | 
542 | 
0 | 
0 | 
| T126 | 
61233 | 
193 | 
0 | 
0 | 
| T127 | 
20638 | 
70 | 
0 | 
0 | 
| T128 | 
11398 | 
56 | 
0 | 
0 | 
| T129 | 
35738 | 
295 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5571 | 
0 | 
0 | 
| T96 | 
4242 | 
2 | 
0 | 
0 | 
| T99 | 
270418 | 
728 | 
0 | 
0 | 
| T106 | 
6112 | 
12 | 
0 | 
0 | 
| T115 | 
13590 | 
30 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
595 | 
0 | 
0 | 
| T126 | 
61233 | 
279 | 
0 | 
0 | 
| T127 | 
20638 | 
87 | 
0 | 
0 | 
| T128 | 
11398 | 
77 | 
0 | 
0 | 
| T129 | 
35738 | 
251 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5143 | 
0 | 
0 | 
| T96 | 
4242 | 
8 | 
0 | 
0 | 
| T99 | 
270418 | 
667 | 
0 | 
0 | 
| T106 | 
6112 | 
17 | 
0 | 
0 | 
| T115 | 
13590 | 
39 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
585 | 
0 | 
0 | 
| T126 | 
61233 | 
225 | 
0 | 
0 | 
| T127 | 
20638 | 
45 | 
0 | 
0 | 
| T128 | 
11398 | 
62 | 
0 | 
0 | 
| T129 | 
35738 | 
323 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5591 | 
0 | 
0 | 
| T96 | 
4242 | 
13 | 
0 | 
0 | 
| T99 | 
270418 | 
633 | 
0 | 
0 | 
| T106 | 
6112 | 
66 | 
0 | 
0 | 
| T115 | 
13590 | 
52 | 
0 | 
0 | 
| T124 | 
4417 | 
9 | 
0 | 
0 | 
| T125 | 
76694 | 
528 | 
0 | 
0 | 
| T126 | 
61233 | 
394 | 
0 | 
0 | 
| T127 | 
20638 | 
36 | 
0 | 
0 | 
| T128 | 
11398 | 
11 | 
0 | 
0 | 
| T129 | 
35738 | 
262 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5731 | 
0 | 
0 | 
| T96 | 
4242 | 
7 | 
0 | 
0 | 
| T99 | 
270418 | 
667 | 
0 | 
0 | 
| T106 | 
6112 | 
56 | 
0 | 
0 | 
| T115 | 
13590 | 
28 | 
0 | 
0 | 
| T124 | 
4417 | 
49 | 
0 | 
0 | 
| T125 | 
76694 | 
508 | 
0 | 
0 | 
| T126 | 
61233 | 
370 | 
0 | 
0 | 
| T127 | 
20638 | 
58 | 
0 | 
0 | 
| T128 | 
11398 | 
69 | 
0 | 
0 | 
| T129 | 
35738 | 
170 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5681 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
672 | 
0 | 
0 | 
| T106 | 
6112 | 
12 | 
0 | 
0 | 
| T115 | 
13590 | 
66 | 
0 | 
0 | 
| T124 | 
4417 | 
1 | 
0 | 
0 | 
| T125 | 
76694 | 
556 | 
0 | 
0 | 
| T126 | 
61233 | 
211 | 
0 | 
0 | 
| T127 | 
20638 | 
55 | 
0 | 
0 | 
| T128 | 
11398 | 
126 | 
0 | 
0 | 
| T129 | 
35738 | 
162 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5440 | 
0 | 
0 | 
| T96 | 
4242 | 
47 | 
0 | 
0 | 
| T99 | 
270418 | 
662 | 
0 | 
0 | 
| T106 | 
6112 | 
70 | 
0 | 
0 | 
| T115 | 
13590 | 
19 | 
0 | 
0 | 
| T124 | 
4417 | 
1 | 
0 | 
0 | 
| T125 | 
76694 | 
537 | 
0 | 
0 | 
| T126 | 
61233 | 
292 | 
0 | 
0 | 
| T127 | 
20638 | 
57 | 
0 | 
0 | 
| T128 | 
11398 | 
19 | 
0 | 
0 | 
| T129 | 
35738 | 
316 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5387 | 
0 | 
0 | 
| T96 | 
4242 | 
59 | 
0 | 
0 | 
| T99 | 
270418 | 
708 | 
0 | 
0 | 
| T115 | 
13590 | 
22 | 
0 | 
0 | 
| T124 | 
4417 | 
46 | 
0 | 
0 | 
| T125 | 
76694 | 
592 | 
0 | 
0 | 
| T126 | 
61233 | 
186 | 
0 | 
0 | 
| T127 | 
20638 | 
98 | 
0 | 
0 | 
| T128 | 
11398 | 
49 | 
0 | 
0 | 
| T129 | 
35738 | 
249 | 
0 | 
0 | 
| T130 | 
4905 | 
60 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5796 | 
0 | 
0 | 
| T96 | 
4242 | 
14 | 
0 | 
0 | 
| T99 | 
270418 | 
661 | 
0 | 
0 | 
| T106 | 
6112 | 
51 | 
0 | 
0 | 
| T115 | 
13590 | 
30 | 
0 | 
0 | 
| T124 | 
4417 | 
58 | 
0 | 
0 | 
| T125 | 
76694 | 
527 | 
0 | 
0 | 
| T126 | 
61233 | 
222 | 
0 | 
0 | 
| T127 | 
20638 | 
65 | 
0 | 
0 | 
| T128 | 
11398 | 
117 | 
0 | 
0 | 
| T129 | 
35738 | 
387 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5549 | 
0 | 
0 | 
| T96 | 
4242 | 
6 | 
0 | 
0 | 
| T99 | 
270418 | 
610 | 
0 | 
0 | 
| T106 | 
6112 | 
35 | 
0 | 
0 | 
| T115 | 
13590 | 
11 | 
0 | 
0 | 
| T124 | 
4417 | 
8 | 
0 | 
0 | 
| T125 | 
76694 | 
503 | 
0 | 
0 | 
| T126 | 
61233 | 
309 | 
0 | 
0 | 
| T127 | 
20638 | 
47 | 
0 | 
0 | 
| T128 | 
11398 | 
55 | 
0 | 
0 | 
| T129 | 
35738 | 
279 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5635 | 
0 | 
0 | 
| T96 | 
4242 | 
1 | 
0 | 
0 | 
| T99 | 
270418 | 
618 | 
0 | 
0 | 
| T106 | 
6112 | 
26 | 
0 | 
0 | 
| T115 | 
13590 | 
76 | 
0 | 
0 | 
| T124 | 
4417 | 
74 | 
0 | 
0 | 
| T125 | 
76694 | 
507 | 
0 | 
0 | 
| T126 | 
61233 | 
286 | 
0 | 
0 | 
| T127 | 
20638 | 
39 | 
0 | 
0 | 
| T128 | 
11398 | 
67 | 
0 | 
0 | 
| T129 | 
35738 | 
281 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5082 | 
0 | 
0 | 
| T99 | 
270418 | 
720 | 
0 | 
0 | 
| T106 | 
6112 | 
14 | 
0 | 
0 | 
| T115 | 
13590 | 
24 | 
0 | 
0 | 
| T124 | 
4417 | 
49 | 
0 | 
0 | 
| T125 | 
76694 | 
516 | 
0 | 
0 | 
| T126 | 
61233 | 
309 | 
0 | 
0 | 
| T127 | 
20638 | 
46 | 
0 | 
0 | 
| T128 | 
11398 | 
73 | 
0 | 
0 | 
| T129 | 
35738 | 
171 | 
0 | 
0 | 
| T130 | 
4905 | 
1 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5342 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
675 | 
0 | 
0 | 
| T106 | 
6112 | 
24 | 
0 | 
0 | 
| T115 | 
13590 | 
21 | 
0 | 
0 | 
| T124 | 
4417 | 
45 | 
0 | 
0 | 
| T125 | 
76694 | 
544 | 
0 | 
0 | 
| T126 | 
61233 | 
272 | 
0 | 
0 | 
| T127 | 
20638 | 
26 | 
0 | 
0 | 
| T128 | 
11398 | 
16 | 
0 | 
0 | 
| T129 | 
35738 | 
251 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2884 | 
0 | 
0 | 
| T96 | 
4242 | 
11 | 
0 | 
0 | 
| T99 | 
270418 | 
718 | 
0 | 
0 | 
| T106 | 
6112 | 
8 | 
0 | 
0 | 
| T115 | 
13590 | 
59 | 
0 | 
0 | 
| T124 | 
4417 | 
9 | 
0 | 
0 | 
| T125 | 
76694 | 
519 | 
0 | 
0 | 
| T126 | 
61233 | 
83 | 
0 | 
0 | 
| T127 | 
20638 | 
46 | 
0 | 
0 | 
| T128 | 
11398 | 
15 | 
0 | 
0 | 
| T129 | 
35738 | 
50 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2798 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
695 | 
0 | 
0 | 
| T106 | 
6112 | 
7 | 
0 | 
0 | 
| T115 | 
13590 | 
43 | 
0 | 
0 | 
| T124 | 
4417 | 
7 | 
0 | 
0 | 
| T125 | 
76694 | 
555 | 
0 | 
0 | 
| T126 | 
61233 | 
52 | 
0 | 
0 | 
| T127 | 
20638 | 
77 | 
0 | 
0 | 
| T128 | 
11398 | 
30 | 
0 | 
0 | 
| T129 | 
35738 | 
53 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2864 | 
0 | 
0 | 
| T96 | 
4242 | 
20 | 
0 | 
0 | 
| T99 | 
270418 | 
628 | 
0 | 
0 | 
| T106 | 
6112 | 
12 | 
0 | 
0 | 
| T115 | 
13590 | 
40 | 
0 | 
0 | 
| T124 | 
4417 | 
17 | 
0 | 
0 | 
| T125 | 
76694 | 
483 | 
0 | 
0 | 
| T126 | 
61233 | 
100 | 
0 | 
0 | 
| T127 | 
20638 | 
62 | 
0 | 
0 | 
| T128 | 
11398 | 
23 | 
0 | 
0 | 
| T129 | 
35738 | 
66 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2852 | 
0 | 
0 | 
| T96 | 
4242 | 
12 | 
0 | 
0 | 
| T99 | 
270418 | 
697 | 
0 | 
0 | 
| T106 | 
6112 | 
9 | 
0 | 
0 | 
| T115 | 
13590 | 
35 | 
0 | 
0 | 
| T124 | 
4417 | 
1 | 
0 | 
0 | 
| T125 | 
76694 | 
493 | 
0 | 
0 | 
| T126 | 
61233 | 
56 | 
0 | 
0 | 
| T127 | 
20638 | 
53 | 
0 | 
0 | 
| T128 | 
11398 | 
22 | 
0 | 
0 | 
| T129 | 
35738 | 
53 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
3244 | 
0 | 
0 | 
| T96 | 
4242 | 
18 | 
0 | 
0 | 
| T99 | 
270418 | 
719 | 
0 | 
0 | 
| T106 | 
6112 | 
5 | 
0 | 
0 | 
| T115 | 
13590 | 
42 | 
0 | 
0 | 
| T124 | 
4417 | 
27 | 
0 | 
0 | 
| T125 | 
76694 | 
526 | 
0 | 
0 | 
| T126 | 
61233 | 
107 | 
0 | 
0 | 
| T127 | 
20638 | 
94 | 
0 | 
0 | 
| T128 | 
11398 | 
21 | 
0 | 
0 | 
| T129 | 
35738 | 
142 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
5442 | 
0 | 
0 | 
| T20 | 
0 | 
30 | 
0 | 
0 | 
| T56 | 
285346 | 
33 | 
0 | 
0 | 
| T65 | 
11530 | 
0 | 
0 | 
0 | 
| T66 | 
337262 | 
0 | 
0 | 
0 | 
| T67 | 
171489 | 
0 | 
0 | 
0 | 
| T68 | 
24818 | 
0 | 
0 | 
0 | 
| T76 | 
206964 | 
0 | 
0 | 
0 | 
| T113 | 
0 | 
8 | 
0 | 
0 | 
| T131 | 
0 | 
73 | 
0 | 
0 | 
| T132 | 
0 | 
61 | 
0 | 
0 | 
| T133 | 
0 | 
83 | 
0 | 
0 | 
| T134 | 
0 | 
24 | 
0 | 
0 | 
| T135 | 
0 | 
14 | 
0 | 
0 | 
| T136 | 
0 | 
14 | 
0 | 
0 | 
| T137 | 
0 | 
42 | 
0 | 
0 | 
| T138 | 
207007 | 
0 | 
0 | 
0 | 
| T139 | 
1732 | 
0 | 
0 | 
0 | 
| T140 | 
75680 | 
0 | 
0 | 
0 | 
| T141 | 
74355 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2795 | 
0 | 
0 | 
| T96 | 
4242 | 
6 | 
0 | 
0 | 
| T99 | 
270418 | 
696 | 
0 | 
0 | 
| T106 | 
6112 | 
10 | 
0 | 
0 | 
| T115 | 
13590 | 
22 | 
0 | 
0 | 
| T124 | 
4417 | 
5 | 
0 | 
0 | 
| T125 | 
76694 | 
561 | 
0 | 
0 | 
| T126 | 
61233 | 
62 | 
0 | 
0 | 
| T127 | 
20638 | 
56 | 
0 | 
0 | 
| T128 | 
11398 | 
17 | 
0 | 
0 | 
| T129 | 
35738 | 
50 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2876 | 
0 | 
0 | 
| T96 | 
4242 | 
11 | 
0 | 
0 | 
| T99 | 
270418 | 
630 | 
0 | 
0 | 
| T106 | 
6112 | 
17 | 
0 | 
0 | 
| T115 | 
13590 | 
81 | 
0 | 
0 | 
| T124 | 
4417 | 
8 | 
0 | 
0 | 
| T125 | 
76694 | 
524 | 
0 | 
0 | 
| T126 | 
61233 | 
48 | 
0 | 
0 | 
| T127 | 
20638 | 
56 | 
0 | 
0 | 
| T128 | 
11398 | 
20 | 
0 | 
0 | 
| T129 | 
35738 | 
67 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2643 | 
0 | 
0 | 
| T96 | 
4242 | 
11 | 
0 | 
0 | 
| T99 | 
270418 | 
618 | 
0 | 
0 | 
| T106 | 
6112 | 
2 | 
0 | 
0 | 
| T115 | 
13590 | 
50 | 
0 | 
0 | 
| T124 | 
4417 | 
2 | 
0 | 
0 | 
| T125 | 
76694 | 
584 | 
0 | 
0 | 
| T126 | 
61233 | 
39 | 
0 | 
0 | 
| T127 | 
20638 | 
102 | 
0 | 
0 | 
| T128 | 
11398 | 
27 | 
0 | 
0 | 
| T129 | 
35738 | 
45 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2668 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
722 | 
0 | 
0 | 
| T106 | 
6112 | 
2 | 
0 | 
0 | 
| T115 | 
13590 | 
28 | 
0 | 
0 | 
| T124 | 
4417 | 
5 | 
0 | 
0 | 
| T125 | 
76694 | 
591 | 
0 | 
0 | 
| T126 | 
61233 | 
38 | 
0 | 
0 | 
| T127 | 
20638 | 
66 | 
0 | 
0 | 
| T128 | 
11398 | 
18 | 
0 | 
0 | 
| T129 | 
35738 | 
37 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2566 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
683 | 
0 | 
0 | 
| T115 | 
13590 | 
29 | 
0 | 
0 | 
| T124 | 
4417 | 
5 | 
0 | 
0 | 
| T125 | 
76694 | 
555 | 
0 | 
0 | 
| T126 | 
61233 | 
31 | 
0 | 
0 | 
| T127 | 
20638 | 
81 | 
0 | 
0 | 
| T128 | 
11398 | 
18 | 
0 | 
0 | 
| T129 | 
35738 | 
38 | 
0 | 
0 | 
| T130 | 
4905 | 
9 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2576 | 
0 | 
0 | 
| T96 | 
4242 | 
5 | 
0 | 
0 | 
| T99 | 
270418 | 
671 | 
0 | 
0 | 
| T106 | 
6112 | 
2 | 
0 | 
0 | 
| T115 | 
13590 | 
41 | 
0 | 
0 | 
| T125 | 
76694 | 
494 | 
0 | 
0 | 
| T126 | 
61233 | 
74 | 
0 | 
0 | 
| T127 | 
20638 | 
74 | 
0 | 
0 | 
| T128 | 
11398 | 
10 | 
0 | 
0 | 
| T129 | 
35738 | 
58 | 
0 | 
0 | 
| T130 | 
4905 | 
9 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
3419 | 
0 | 
0 | 
| T96 | 
4242 | 
21 | 
0 | 
0 | 
| T99 | 
270418 | 
666 | 
0 | 
0 | 
| T106 | 
6112 | 
6 | 
0 | 
0 | 
| T115 | 
13590 | 
83 | 
0 | 
0 | 
| T124 | 
4417 | 
15 | 
0 | 
0 | 
| T125 | 
76694 | 
512 | 
0 | 
0 | 
| T126 | 
61233 | 
123 | 
0 | 
0 | 
| T127 | 
20638 | 
92 | 
0 | 
0 | 
| T128 | 
11398 | 
42 | 
0 | 
0 | 
| T129 | 
35738 | 
68 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2568 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
648 | 
0 | 
0 | 
| T106 | 
6112 | 
2 | 
0 | 
0 | 
| T115 | 
13590 | 
22 | 
0 | 
0 | 
| T124 | 
4417 | 
5 | 
0 | 
0 | 
| T125 | 
76694 | 
543 | 
0 | 
0 | 
| T126 | 
61233 | 
25 | 
0 | 
0 | 
| T127 | 
20638 | 
62 | 
0 | 
0 | 
| T128 | 
11398 | 
14 | 
0 | 
0 | 
| T129 | 
35738 | 
40 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
3659 | 
0 | 
0 | 
| T96 | 
4242 | 
21 | 
0 | 
0 | 
| T99 | 
270418 | 
675 | 
0 | 
0 | 
| T106 | 
6112 | 
10 | 
0 | 
0 | 
| T115 | 
13590 | 
14 | 
0 | 
0 | 
| T124 | 
4417 | 
2 | 
0 | 
0 | 
| T125 | 
76694 | 
543 | 
0 | 
0 | 
| T126 | 
61233 | 
143 | 
0 | 
0 | 
| T127 | 
20638 | 
81 | 
0 | 
0 | 
| T128 | 
11398 | 
19 | 
0 | 
0 | 
| T129 | 
35738 | 
129 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2749 | 
0 | 
0 | 
| T96 | 
4242 | 
19 | 
0 | 
0 | 
| T99 | 
270418 | 
631 | 
0 | 
0 | 
| T106 | 
6112 | 
10 | 
0 | 
0 | 
| T115 | 
13590 | 
32 | 
0 | 
0 | 
| T124 | 
4417 | 
9 | 
0 | 
0 | 
| T125 | 
76694 | 
546 | 
0 | 
0 | 
| T126 | 
61233 | 
48 | 
0 | 
0 | 
| T127 | 
20638 | 
52 | 
0 | 
0 | 
| T128 | 
11398 | 
16 | 
0 | 
0 | 
| T129 | 
35738 | 
36 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2603 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
753 | 
0 | 
0 | 
| T106 | 
6112 | 
15 | 
0 | 
0 | 
| T115 | 
13590 | 
53 | 
0 | 
0 | 
| T124 | 
4417 | 
6 | 
0 | 
0 | 
| T125 | 
76694 | 
517 | 
0 | 
0 | 
| T126 | 
61233 | 
35 | 
0 | 
0 | 
| T127 | 
20638 | 
43 | 
0 | 
0 | 
| T128 | 
11398 | 
12 | 
0 | 
0 | 
| T129 | 
35738 | 
26 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2468 | 
0 | 
0 | 
| T96 | 
4242 | 
3 | 
0 | 
0 | 
| T99 | 
270418 | 
703 | 
0 | 
0 | 
| T106 | 
6112 | 
15 | 
0 | 
0 | 
| T115 | 
13590 | 
45 | 
0 | 
0 | 
| T124 | 
4417 | 
4 | 
0 | 
0 | 
| T125 | 
76694 | 
510 | 
0 | 
0 | 
| T126 | 
61233 | 
48 | 
0 | 
0 | 
| T127 | 
20638 | 
26 | 
0 | 
0 | 
| T128 | 
11398 | 
16 | 
0 | 
0 | 
| T129 | 
35738 | 
27 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2607 | 
0 | 
0 | 
| T96 | 
4242 | 
7 | 
0 | 
0 | 
| T99 | 
270418 | 
654 | 
0 | 
0 | 
| T106 | 
6112 | 
4 | 
0 | 
0 | 
| T115 | 
13590 | 
42 | 
0 | 
0 | 
| T124 | 
4417 | 
1 | 
0 | 
0 | 
| T125 | 
76694 | 
509 | 
0 | 
0 | 
| T126 | 
61233 | 
50 | 
0 | 
0 | 
| T127 | 
20638 | 
73 | 
0 | 
0 | 
| T128 | 
11398 | 
27 | 
0 | 
0 | 
| T129 | 
35738 | 
37 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2390 | 
0 | 
0 | 
| T96 | 
4242 | 
2 | 
0 | 
0 | 
| T99 | 
270418 | 
645 | 
0 | 
0 | 
| T115 | 
13590 | 
29 | 
0 | 
0 | 
| T124 | 
4417 | 
4 | 
0 | 
0 | 
| T125 | 
76694 | 
495 | 
0 | 
0 | 
| T126 | 
61233 | 
30 | 
0 | 
0 | 
| T127 | 
20638 | 
68 | 
0 | 
0 | 
| T128 | 
11398 | 
17 | 
0 | 
0 | 
| T129 | 
35738 | 
32 | 
0 | 
0 | 
| T130 | 
4905 | 
1 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2466 | 
0 | 
0 | 
| T96 | 
4242 | 
4 | 
0 | 
0 | 
| T99 | 
270418 | 
639 | 
0 | 
0 | 
| T115 | 
13590 | 
76 | 
0 | 
0 | 
| T124 | 
4417 | 
10 | 
0 | 
0 | 
| T125 | 
76694 | 
549 | 
0 | 
0 | 
| T126 | 
61233 | 
39 | 
0 | 
0 | 
| T127 | 
20638 | 
96 | 
0 | 
0 | 
| T128 | 
11398 | 
19 | 
0 | 
0 | 
| T129 | 
35738 | 
23 | 
0 | 
0 | 
| T130 | 
4905 | 
4 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
459348419 | 
2484 | 
0 | 
0 | 
| T96 | 
4242 | 
9 | 
0 | 
0 | 
| T99 | 
270418 | 
680 | 
0 | 
0 | 
| T106 | 
6112 | 
8 | 
0 | 
0 | 
| T115 | 
13590 | 
46 | 
0 | 
0 | 
| T124 | 
4417 | 
5 | 
0 | 
0 | 
| T125 | 
76694 | 
583 | 
0 | 
0 | 
| T126 | 
61233 | 
9 | 
0 | 
0 | 
| T127 | 
20638 | 
21 | 
0 | 
0 | 
| T128 | 
11398 | 
7 | 
0 | 
0 | 
| T129 | 
35738 | 
31 | 
0 | 
0 |