Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3742435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4380830

1

T1

882

T2

2

T3

2821

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4502866	1			T1	13		T2	1		T3	3878
values[0x0]	1808448	1			T1	462		T2	1		T3	427
values[0x1]	1811951	1			T1	415		T3	463		T4	462

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2657840	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5465425

1

T1

884

T2

2

T3

3221

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29953	1			T5	8		T6	8		T7	44
valid_sources[0x01]	38642	1			T5	12		T6	12		T7	53
valid_sources[0x02]	29230	1			T1	10		T5	6		T6	12
valid_sources[0x03]	30773	1			T5	7		T6	10		T7	39
valid_sources[0x04]	31661	1			T1	5		T5	13		T6	8
valid_sources[0x05]	31318	1			T5	10		T6	8		T7	33
valid_sources[0x06]	31103	1			T5	10		T6	14		T7	22
valid_sources[0x07]	33494	1			T5	6		T6	14		T7	48
valid_sources[0x08]	31355	1			T5	8		T6	15		T7	22
valid_sources[0x09]	34064	1			T5	9		T6	9		T7	50
valid_sources[0x0a]	31908	1			T5	6		T6	11		T7	47
valid_sources[0x0b]	29134	1			T5	6		T6	17		T7	45
valid_sources[0x0c]	30920	1			T5	14		T6	12		T7	39
valid_sources[0x0d]	30047	1			T1	26		T5	14		T6	17
valid_sources[0x0e]	30064	1			T5	7		T6	11		T7	55
valid_sources[0x0f]	30803	1			T1	14		T5	9		T6	15
valid_sources[0x10]	29825	1			T5	9		T6	18		T7	40
valid_sources[0x11]	27944	1			T5	13		T6	11		T7	39
valid_sources[0x12]	30812	1			T5	11		T6	17		T7	34
valid_sources[0x13]	30403	1			T5	9		T6	10		T7	36
valid_sources[0x14]	29351	1			T5	10		T6	10		T7	42
valid_sources[0x15]	31702	1			T5	14		T6	15		T7	57
valid_sources[0x16]	29428	1			T5	11		T6	12		T7	54
valid_sources[0x17]	37052	1			T5	14		T6	9		T7	59
valid_sources[0x18]	31467	1			T4	1		T5	8		T6	16
valid_sources[0x19]	29707	1			T5	9		T6	11		T7	43
valid_sources[0x1a]	29567	1			T1	59		T5	13		T6	10
valid_sources[0x1b]	34029	1			T5	13		T6	16		T7	45
valid_sources[0x1c]	30965	1			T5	12		T6	8		T7	30
valid_sources[0x1d]	29864	1			T5	14		T6	9		T7	49
valid_sources[0x1e]	29595	1			T5	4		T6	14		T7	49
valid_sources[0x1f]	29924	1			T1	12		T5	7		T6	14
valid_sources[0x20]	29395	1			T5	7		T6	12		T7	48
valid_sources[0x21]	28622	1			T2	2		T5	5		T6	13
valid_sources[0x22]	28997	1			T5	6		T6	18		T7	72
valid_sources[0x23]	33091	1			T5	4		T6	10		T7	31
valid_sources[0x24]	33621	1			T5	12		T6	15		T7	71
valid_sources[0x25]	29097	1			T5	18		T6	7		T7	33
valid_sources[0x26]	30875	1			T5	9		T6	8		T7	40
valid_sources[0x27]	29279	1			T5	10		T6	13		T7	56
valid_sources[0x28]	31975	1			T1	14		T5	16		T6	7
valid_sources[0x29]	29582	1			T5	6		T6	18		T7	54
valid_sources[0x2a]	29156	1			T5	9		T6	13		T7	22
valid_sources[0x2b]	29496	1			T5	10		T6	19		T7	44
valid_sources[0x2c]	33381	1			T5	15		T6	10		T7	39
valid_sources[0x2d]	28102	1			T5	14		T6	15		T7	49
valid_sources[0x2e]	29610	1			T5	12		T6	9		T7	44
valid_sources[0x2f]	31393	1			T5	12		T6	11		T7	58
valid_sources[0x30]	34849	1			T1	14		T5	9		T6	8
valid_sources[0x31]	29438	1			T5	15		T6	20		T7	39
valid_sources[0x32]	31850	1			T5	8		T6	12		T7	37
valid_sources[0x33]	32509	1			T5	14		T6	16		T7	35
valid_sources[0x34]	34975	1			T5	18		T6	19		T7	61
valid_sources[0x35]	29326	1			T5	11		T6	17		T7	38
valid_sources[0x36]	30637	1			T5	14		T6	13		T7	64
valid_sources[0x37]	34754	1			T1	1		T5	11		T6	8
valid_sources[0x38]	31707	1			T5	7		T6	5		T7	49
valid_sources[0x39]	30393	1			T5	6		T6	19		T7	44
valid_sources[0x3a]	28820	1			T1	10		T5	10		T6	16
valid_sources[0x3b]	30197	1			T5	12		T6	14		T7	46
valid_sources[0x3c]	30857	1			T5	6		T6	5		T7	44
valid_sources[0x3d]	31657	1			T5	12		T6	11		T7	52
valid_sources[0x3e]	29996	1			T5	10		T6	17		T7	36
valid_sources[0x3f]	30384	1			T5	9		T6	19		T7	44
valid_sources[0x40]	32307	1			T5	5		T6	13		T7	48
valid_sources[0x41]	28287	1			T5	6		T6	14		T7	55
valid_sources[0x42]	37174	1			T5	7		T6	13		T7	35
valid_sources[0x43]	31985	1			T5	8		T6	9		T7	30
valid_sources[0x44]	31140	1			T4	416		T5	10		T6	12
valid_sources[0x45]	29636	1			T5	13		T6	11		T7	31
valid_sources[0x46]	29883	1			T5	12		T6	10		T7	58
valid_sources[0x47]	31024	1			T4	1212		T5	18		T6	13
valid_sources[0x48]	29908	1			T1	18		T5	6		T6	6
valid_sources[0x49]	29254	1			T1	3		T5	9		T6	14
valid_sources[0x4a]	29699	1			T5	8		T6	15		T7	52
valid_sources[0x4b]	29283	1			T5	5		T6	9		T7	43
valid_sources[0x4c]	31212	1			T1	3		T5	12		T6	17
valid_sources[0x4d]	34030	1			T5	6		T6	10		T7	60
valid_sources[0x4e]	51285	1			T5	11		T6	7		T7	49
valid_sources[0x4f]	30148	1			T5	11		T6	14		T7	55
valid_sources[0x50]	31638	1			T5	12		T6	5		T7	45
valid_sources[0x51]	30116	1			T5	13		T6	13		T7	45
valid_sources[0x52]	32347	1			T5	16		T6	16		T7	40
valid_sources[0x53]	29995	1			T5	11		T6	16		T7	43
valid_sources[0x54]	28961	1			T5	6		T6	12		T7	42
valid_sources[0x55]	31253	1			T5	10		T6	10		T7	51
valid_sources[0x56]	33165	1			T1	2		T5	11		T6	9
valid_sources[0x57]	33570	1			T1	38		T5	18		T6	22
valid_sources[0x58]	29803	1			T5	10		T6	10		T7	49
valid_sources[0x59]	39814	1			T5	11		T6	16		T7	45
valid_sources[0x5a]	30254	1			T5	2		T6	9		T7	29
valid_sources[0x5b]	29443	1			T5	6		T6	10		T7	49
valid_sources[0x5c]	29309	1			T5	12		T6	20		T7	46
valid_sources[0x5d]	30791	1			T5	15		T6	10		T7	43
valid_sources[0x5e]	30252	1			T1	9		T5	12		T6	10
valid_sources[0x5f]	34357	1			T5	11		T6	9		T7	54
valid_sources[0x60]	29144	1			T1	21		T5	10		T6	12
valid_sources[0x61]	30493	1			T5	10		T6	6		T7	42
valid_sources[0x62]	32570	1			T5	12		T6	15		T7	67
valid_sources[0x63]	28999	1			T5	11		T6	14		T7	49
valid_sources[0x64]	31156	1			T5	9		T6	13		T7	60
valid_sources[0x65]	29703	1			T5	11		T6	13		T7	30
valid_sources[0x66]	36100	1			T5	10		T6	13		T7	43
valid_sources[0x67]	28133	1			T5	10		T6	16		T7	36
valid_sources[0x68]	31832	1			T5	15		T6	16		T7	42
valid_sources[0x69]	31013	1			T5	5		T6	13		T7	25
valid_sources[0x6a]	31659	1			T5	6		T6	12		T7	61
valid_sources[0x6b]	28244	1			T5	4		T6	25		T7	50
valid_sources[0x6c]	29954	1			T5	6		T6	17		T7	42
valid_sources[0x6d]	30605	1			T5	10		T6	15		T7	31
valid_sources[0x6e]	32822	1			T1	16		T5	16		T6	11
valid_sources[0x6f]	29603	1			T5	9		T6	19		T7	51
valid_sources[0x70]	30526	1			T5	14		T6	12		T7	51
valid_sources[0x71]	29618	1			T5	5		T6	15		T7	56
valid_sources[0x72]	33489	1			T5	9		T6	10		T7	41
valid_sources[0x73]	32867	1			T5	12		T6	13		T7	51
valid_sources[0x74]	29476	1			T1	21		T5	21		T6	14
valid_sources[0x75]	30142	1			T1	15		T5	12		T6	7
valid_sources[0x76]	29410	1			T1	32		T5	6		T6	11
valid_sources[0x77]	29927	1			T5	6		T6	7		T7	52
valid_sources[0x78]	28469	1			T5	13		T6	7		T7	38
valid_sources[0x79]	31130	1			T5	9		T6	16		T7	32
valid_sources[0x7a]	30825	1			T5	7		T6	10		T7	42
valid_sources[0x7b]	30921	1			T5	15		T6	11		T7	43
valid_sources[0x7c]	39869	1			T1	2		T3	4768		T5	5
valid_sources[0x7d]	28742	1			T5	13		T6	7		T7	39
valid_sources[0x7e]	29627	1			T5	6		T6	16		T7	38
valid_sources[0x7f]	32004	1			T5	13		T6	7		T7	52
valid_sources[0x80]	34592	1			T5	7		T6	16		T7	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1106472

1

T1

7

T2

1

T3

1941

values[0x0]

all_enables

biggest_size

1649319

1

T1

462

T2

1

T3

424

values[0x1]

all_enables

biggest_size

1625039

1

T1

413

T3

456

T4

461