Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3765052

1

T1

8

T3

1947

T4

601

full_word

4382183

1

T1

882

T2

2

T3

2821

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8146765	1			T1	890		T2	2		T3	4768
auto[TlIntgErrCmd]	149	1			T109	5		T110	3		T111	2
auto[TlIntgErrData]	165	1			T109	12		T110	10		T111	4
auto[TlIntgErrBoth]	156	1			T109	13		T110	7		T111	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4507916

1

T1

13

T2

1

T3

3878

auto[1]

3639319

1

T1

877

T2

1

T3

890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3400868	1			T1	6		T3	1937		T4	598
auto[TlIntgErrNone]	partial	auto[1]	363755	1			T1	2		T3	10		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	1106825	1			T1	7		T2	1		T3	1941
auto[TlIntgErrNone]	full_word	auto[1]	3275317	1			T1	875		T2	1		T3	880
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T109	3		T110	1		T123	5
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T110	2		T111	2		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T109	1		T162	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T109	1		T126	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T109	7		T110	4		T111	2
auto[TlIntgErrData]	partial	auto[1]	70	1			T109	5		T110	4		T111	2
auto[TlIntgErrData]	full_word	auto[0]	10	1			T110	1		T123	1		T164	1
auto[TlIntgErrData]	full_word	auto[1]	12	1			T110	1		T123	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	68	1			T109	5		T110	2		T123	8
auto[TlIntgErrBoth]	partial	auto[1]	80	1			T109	6		T110	4		T111	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T109	2		T180	1		T181	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T110	1		T123	1		T182	1