Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T7,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T10
1	0	Unreachable
1	1	Covered	T7,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T12
1	0	Covered	T7,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T7,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	785395256	631783565	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	785395256	3821977	0	0
GntImpliesValid_A	785395256	3821977	0	0
GrantKnown_A	785395256	631783565	0	0
IdxKnown_A	785395256	631783565	0	0
IndexIsCorrect_A	785395256	3821977	0	0
LockArbDecision_A	785395256	0	0	0
NoReadyValidNoGrant_A	785395256	0	0	0
ReadyAndValidImplyGrant_A	785395256	3821977	0	0
ReqAndReadyImplyGrant_A	785395256	3821977	0	0
ReqImpliesValid_A	785395256	3821977	0	0
ReqStaysHighUntilGranted0_M	785395256	0	0	0
RoundRobin_A	785395256	4	0	956
ValidKnown_A	785395256	631783565	0	0
gen_data_port_assertion.DataFlow_A	785395256	3821977	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	631783565	0	0
T1	29122	29050	0	0
T2	1383	1294	0	0
T3	145337	145266	0	0
T4	939159	938794	0	0
T5	53484	53423	0	0
T6	63595	63040	0	0
T7	794992	663173	0	0
T8	173996	101231	0	0
T9	98582	77943	0	0
T10	700389	394671	0	0
T11	62416	30788	0	0
T12	193329	190666	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	631783565	0	0
T1	29122	29050	0	0
T2	1383	1294	0	0
T3	145337	145266	0	0
T4	939159	938794	0	0
T5	53484	53423	0	0
T6	63595	63040	0	0
T7	794992	663173	0	0
T8	173996	101231	0	0
T9	98582	77943	0	0
T10	700389	394671	0	0
T11	62416	30788	0	0
T12	193329	190666	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	631783565	0	0
T1	29122	29050	0	0
T2	1383	1294	0	0
T3	145337	145266	0	0
T4	939159	938794	0	0
T5	53484	53423	0	0
T6	63595	63040	0	0
T7	794992	663173	0	0
T8	173996	101231	0	0
T9	98582	77943	0	0
T10	700389	394671	0	0
T11	62416	30788	0	0
T12	193329	190666	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	4	0	956
T44	754615	0	0	1
T62	188426	1	0	1
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	80710	0	0	1
T67	61385	0	0	1
T68	44065	0	0	1
T69	124512	0	0	1
T70	8776	0	0	1
T71	11036	0	0	1
T72	290381	0	0	1
T73	748	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	631783565	0	0
T1	29122	29050	0	0
T2	1383	1294	0	0
T3	145337	145266	0	0
T4	939159	938794	0	0
T5	53484	53423	0	0
T6	63595	63040	0	0
T7	794992	663173	0	0
T8	173996	101231	0	0
T9	98582	77943	0	0
T10	700389	394671	0	0
T11	62416	30788	0	0
T12	193329	190666	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785395256	3821977	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	794992	2566	0	0
T8	173996	832	0	0
T9	98582	878	0	0
T10	700389	6066	0	0
T11	62416	832	0	0
T12	386658	6381	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	1002244	3914	0	0
T31	679334	5821	0	0
T32	32784	828	0	0
T33	0	4393	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	8936	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T7,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T10
1	0	Unreachable
1	1	Covered	T7,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T7,T9,T10

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152047705	30858305	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	152047705	688324	0	0
GntImpliesValid_A	152047705	688324	0	0
GrantKnown_A	152047705	30858305	0	0
IdxKnown_A	152047705	30858305	0	0
IndexIsCorrect_A	152047705	688324	0	0
LockArbDecision_A	152047705	0	0	0
NoReadyValidNoGrant_A	152047705	0	0	0
ReadyAndValidImplyGrant_A	152047705	688324	0	0
ReqAndReadyImplyGrant_A	152047705	688324	0	0
ReqImpliesValid_A	152047705	688324	0	0
ReqStaysHighUntilGranted0_M	152047705	0	0	0
RoundRobin_A	152047705	0	0	0
ValidKnown_A	152047705	30858305	0	0
gen_data_port_assertion.DataFlow_A	152047705	688324	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	30858305	0	0
T7	130834	31608	0	0
T8	72698	0	0	0
T9	19326	18064	0	0
T10	302589	141576	0	0
T11	31208	0	0	0
T12	193329	39728	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	30858305	0	0
T7	130834	31608	0	0
T8	72698	0	0	0
T9	19326	18064	0	0
T10	302589	141576	0	0
T11	31208	0	0	0
T12	193329	39728	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	30858305	0	0
T7	130834	31608	0	0
T8	72698	0	0	0
T9	19326	18064	0	0
T10	302589	141576	0	0
T11	31208	0	0	0
T12	193329	39728	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	30858305	0	0
T7	130834	31608	0	0
T8	72698	0	0	0
T9	19326	18064	0	0
T10	302589	141576	0	0
T11	31208	0	0	0
T12	193329	39728	0	0
T30	501122	347496	0	0
T31	339667	89512	0	0
T32	16392	16392	0	0
T33	0	69680	0	0
T34	0	96504	0	0
T36	0	96928	0	0
T50	4468	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	688324	0	0
T7	130834	1142	0	0
T8	72698	0	0	0
T9	19326	542	0	0
T10	302589	1490	0	0
T11	31208	0	0	0
T12	193329	1507	0	0
T30	501122	3906	0	0
T31	339667	4143	0	0
T32	16392	828	0	0
T33	0	2958	0	0
T34	0	3461	0	0
T41	0	2620	0	0
T50	4468	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T12
1	0	Covered	T7,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T7,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	152047705	119712142	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	152047705	807515	0	0
GntImpliesValid_A	152047705	807515	0	0
GrantKnown_A	152047705	119712142	0	0
IdxKnown_A	152047705	119712142	0	0
IndexIsCorrect_A	152047705	807515	0	0
LockArbDecision_A	152047705	0	0	0
NoReadyValidNoGrant_A	152047705	0	0	0
ReadyAndValidImplyGrant_A	152047705	807515	0	0
ReqAndReadyImplyGrant_A	152047705	807515	0	0
ReqImpliesValid_A	152047705	807515	0	0
ReqStaysHighUntilGranted0_M	152047705	0	0	0
RoundRobin_A	152047705	0	0	0
ValidKnown_A	152047705	119712142	0	0
gen_data_port_assertion.DataFlow_A	152047705	807515	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	119712142	0	0
T1	13105	13105	0	0
T3	17814	17814	0	0
T4	133321	133044	0	0
T5	12462	12462	0	0
T6	41077	40583	0	0
T7	130834	98296	0	0
T8	72698	72698	0	0
T9	19326	0	0	0
T10	302589	157969	0	0
T11	31208	30788	0	0
T12	0	150938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	119712142	0	0
T1	13105	13105	0	0
T3	17814	17814	0	0
T4	133321	133044	0	0
T5	12462	12462	0	0
T6	41077	40583	0	0
T7	130834	98296	0	0
T8	72698	72698	0	0
T9	19326	0	0	0
T10	302589	157969	0	0
T11	31208	30788	0	0
T12	0	150938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	119712142	0	0
T1	13105	13105	0	0
T3	17814	17814	0	0
T4	133321	133044	0	0
T5	12462	12462	0	0
T6	41077	40583	0	0
T7	130834	98296	0	0
T8	72698	72698	0	0
T9	19326	0	0	0
T10	302589	157969	0	0
T11	31208	30788	0	0
T12	0	150938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	119712142	0	0
T1	13105	13105	0	0
T3	17814	17814	0	0
T4	133321	133044	0	0
T5	12462	12462	0	0
T6	41077	40583	0	0
T7	130834	98296	0	0
T8	72698	72698	0	0
T9	19326	0	0	0
T10	302589	157969	0	0
T11	31208	30788	0	0
T12	0	150938	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152047705	807515	0	0
T7	130834	5	0	0
T8	72698	0	0	0
T9	19326	0	0	0
T10	302589	1159	0	0
T11	31208	0	0	0
T12	193329	4874	0	0
T13	0	7933	0	0
T14	0	2602	0	0
T30	501122	8	0	0
T31	339667	1678	0	0
T32	16392	0	0	0
T33	0	1435	0	0
T50	4468	0	0	0
T60	0	2	0	0
T61	0	1456	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T9,T10
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	481299846	481213118	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	481299846	2326138	0	0
GntImpliesValid_A	481299846	2326138	0	0
GrantKnown_A	481299846	481213118	0	0
IdxKnown_A	481299846	481213118	0	0
IndexIsCorrect_A	481299846	2326138	0	0
LockArbDecision_A	481299846	0	0	0
NoReadyValidNoGrant_A	481299846	0	0	0
ReadyAndValidImplyGrant_A	481299846	2326138	0	0
ReqAndReadyImplyGrant_A	481299846	2326138	0	0
ReqImpliesValid_A	481299846	2326138	0	0
ReqStaysHighUntilGranted0_M	481299846	0	0	0
RoundRobin_A	481299846	4	0	956
ValidKnown_A	481299846	481213118	0	0
gen_data_port_assertion.DataFlow_A	481299846	2326138	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	481213118	0	0
T1	16017	15945	0	0
T2	1383	1294	0	0
T3	127523	127452	0	0
T4	805838	805750	0	0
T5	41022	40961	0	0
T6	22518	22457	0	0
T7	533324	533269	0	0
T8	28600	28533	0	0
T9	59930	59879	0	0
T10	95211	95126	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	481213118	0	0
T1	16017	15945	0	0
T2	1383	1294	0	0
T3	127523	127452	0	0
T4	805838	805750	0	0
T5	41022	40961	0	0
T6	22518	22457	0	0
T7	533324	533269	0	0
T8	28600	28533	0	0
T9	59930	59879	0	0
T10	95211	95126	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	481213118	0	0
T1	16017	15945	0	0
T2	1383	1294	0	0
T3	127523	127452	0	0
T4	805838	805750	0	0
T5	41022	40961	0	0
T6	22518	22457	0	0
T7	533324	533269	0	0
T8	28600	28533	0	0
T9	59930	59879	0	0
T10	95211	95126	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	4	0	956
T44	754615	0	0	1
T62	188426	1	0	1
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	80710	0	0	1
T67	61385	0	0	1
T68	44065	0	0	1
T69	124512	0	0	1
T70	8776	0	0	1
T71	11036	0	0	1
T72	290381	0	0	1
T73	748	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	481213118	0	0
T1	16017	15945	0	0
T2	1383	1294	0	0
T3	127523	127452	0	0
T4	805838	805750	0	0
T5	41022	40961	0	0
T6	22518	22457	0	0
T7	533324	533269	0	0
T8	28600	28533	0	0
T9	59930	59879	0	0
T10	95211	95126	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481299846	2326138	0	0
T1	16017	832	0	0
T2	1383	0	0	0
T3	127523	832	0	0
T4	805838	832	0	0
T5	41022	832	0	0
T6	22518	2624	0	0
T7	533324	1419	0	0
T8	28600	832	0	0
T9	59930	336	0	0
T10	95211	3417	0	0
T11	0	832	0	0