Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
3399 |
0 |
0 |
T77 |
13276 |
9 |
0 |
0 |
T78 |
11252 |
4 |
0 |
0 |
T79 |
7978 |
94 |
0 |
0 |
T109 |
29630 |
6 |
0 |
0 |
T110 |
55802 |
4 |
0 |
0 |
T112 |
5794 |
71 |
0 |
0 |
T121 |
29725 |
4 |
0 |
0 |
T122 |
4503 |
1 |
0 |
0 |
T123 |
29552 |
5 |
0 |
0 |
T162 |
19062 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2768 |
0 |
0 |
T111 |
38220 |
39 |
0 |
0 |
T116 |
15932 |
7 |
0 |
0 |
T124 |
34295 |
33 |
0 |
0 |
T129 |
269520 |
715 |
0 |
0 |
T130 |
9653 |
11 |
0 |
0 |
T131 |
8733 |
12 |
0 |
0 |
T136 |
181132 |
454 |
0 |
0 |
T153 |
19746 |
104 |
0 |
0 |
T154 |
18567 |
28 |
0 |
0 |
T163 |
13823 |
68 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2548 |
0 |
0 |
T111 |
38220 |
58 |
0 |
0 |
T124 |
34295 |
24 |
0 |
0 |
T129 |
269520 |
700 |
0 |
0 |
T130 |
9653 |
2 |
0 |
0 |
T131 |
8733 |
3 |
0 |
0 |
T136 |
181132 |
427 |
0 |
0 |
T137 |
7999 |
9 |
0 |
0 |
T153 |
19746 |
61 |
0 |
0 |
T154 |
18567 |
45 |
0 |
0 |
T163 |
13823 |
28 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
3119 |
0 |
0 |
T111 |
38220 |
75 |
0 |
0 |
T116 |
15932 |
6 |
0 |
0 |
T124 |
34295 |
64 |
0 |
0 |
T129 |
269520 |
677 |
0 |
0 |
T130 |
9653 |
15 |
0 |
0 |
T131 |
8733 |
12 |
0 |
0 |
T136 |
181132 |
493 |
0 |
0 |
T153 |
19746 |
145 |
0 |
0 |
T154 |
18567 |
49 |
0 |
0 |
T163 |
13823 |
62 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
8706 |
0 |
0 |
T111 |
38220 |
619 |
0 |
0 |
T124 |
34295 |
679 |
0 |
0 |
T129 |
269520 |
647 |
0 |
0 |
T130 |
9653 |
99 |
0 |
0 |
T131 |
8733 |
93 |
0 |
0 |
T136 |
181132 |
451 |
0 |
0 |
T137 |
7999 |
278 |
0 |
0 |
T153 |
19746 |
43 |
0 |
0 |
T154 |
18567 |
31 |
0 |
0 |
T163 |
13823 |
44 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
9125 |
0 |
0 |
T111 |
38220 |
975 |
0 |
0 |
T124 |
34295 |
787 |
0 |
0 |
T129 |
269520 |
660 |
0 |
0 |
T130 |
9653 |
72 |
0 |
0 |
T131 |
8733 |
118 |
0 |
0 |
T136 |
181132 |
446 |
0 |
0 |
T137 |
7999 |
149 |
0 |
0 |
T153 |
19746 |
70 |
0 |
0 |
T154 |
18567 |
35 |
0 |
0 |
T163 |
13823 |
80 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
8595 |
0 |
0 |
T111 |
38220 |
791 |
0 |
0 |
T124 |
34295 |
743 |
0 |
0 |
T129 |
269520 |
689 |
0 |
0 |
T130 |
9653 |
89 |
0 |
0 |
T131 |
8733 |
214 |
0 |
0 |
T136 |
181132 |
414 |
0 |
0 |
T137 |
7999 |
232 |
0 |
0 |
T153 |
19746 |
78 |
0 |
0 |
T154 |
18567 |
18 |
0 |
0 |
T163 |
13823 |
25 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
8876 |
0 |
0 |
T111 |
38220 |
411 |
0 |
0 |
T124 |
34295 |
506 |
0 |
0 |
T129 |
269520 |
607 |
0 |
0 |
T130 |
9653 |
108 |
0 |
0 |
T131 |
8733 |
127 |
0 |
0 |
T136 |
181132 |
411 |
0 |
0 |
T137 |
7999 |
1 |
0 |
0 |
T153 |
19746 |
75 |
0 |
0 |
T154 |
18567 |
41 |
0 |
0 |
T163 |
13823 |
31 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
8194 |
0 |
0 |
T111 |
38220 |
227 |
0 |
0 |
T124 |
34295 |
360 |
0 |
0 |
T129 |
269520 |
629 |
0 |
0 |
T130 |
9653 |
41 |
0 |
0 |
T131 |
8733 |
239 |
0 |
0 |
T136 |
181132 |
454 |
0 |
0 |
T137 |
7999 |
134 |
0 |
0 |
T153 |
19746 |
100 |
0 |
0 |
T154 |
18567 |
13 |
0 |
0 |
T163 |
13823 |
72 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
8684 |
0 |
0 |
T111 |
38220 |
673 |
0 |
0 |
T124 |
34295 |
243 |
0 |
0 |
T129 |
269520 |
710 |
0 |
0 |
T130 |
9653 |
7 |
0 |
0 |
T131 |
8733 |
123 |
0 |
0 |
T136 |
181132 |
441 |
0 |
0 |
T137 |
7999 |
141 |
0 |
0 |
T153 |
19746 |
83 |
0 |
0 |
T154 |
18567 |
36 |
0 |
0 |
T163 |
13823 |
87 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
10104 |
0 |
0 |
T111 |
38220 |
701 |
0 |
0 |
T124 |
34295 |
686 |
0 |
0 |
T129 |
269520 |
702 |
0 |
0 |
T130 |
9653 |
89 |
0 |
0 |
T131 |
8733 |
129 |
0 |
0 |
T136 |
181132 |
468 |
0 |
0 |
T137 |
7999 |
129 |
0 |
0 |
T153 |
19746 |
31 |
0 |
0 |
T154 |
18567 |
24 |
0 |
0 |
T163 |
13823 |
54 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
9488 |
0 |
0 |
T111 |
38220 |
718 |
0 |
0 |
T124 |
34295 |
977 |
0 |
0 |
T129 |
269520 |
734 |
0 |
0 |
T130 |
9653 |
77 |
0 |
0 |
T131 |
8733 |
133 |
0 |
0 |
T136 |
181132 |
410 |
0 |
0 |
T137 |
7999 |
9 |
0 |
0 |
T153 |
19746 |
57 |
0 |
0 |
T154 |
18567 |
26 |
0 |
0 |
T163 |
13823 |
35 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5063 |
0 |
0 |
T111 |
38220 |
256 |
0 |
0 |
T124 |
34295 |
239 |
0 |
0 |
T129 |
269520 |
653 |
0 |
0 |
T130 |
9653 |
23 |
0 |
0 |
T131 |
8733 |
5 |
0 |
0 |
T136 |
181132 |
431 |
0 |
0 |
T137 |
7999 |
5 |
0 |
0 |
T153 |
19746 |
60 |
0 |
0 |
T154 |
18567 |
11 |
0 |
0 |
T163 |
13823 |
42 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5413 |
0 |
0 |
T111 |
38220 |
298 |
0 |
0 |
T124 |
34295 |
274 |
0 |
0 |
T129 |
269520 |
683 |
0 |
0 |
T130 |
9653 |
81 |
0 |
0 |
T131 |
8733 |
63 |
0 |
0 |
T136 |
181132 |
439 |
0 |
0 |
T137 |
7999 |
70 |
0 |
0 |
T153 |
19746 |
99 |
0 |
0 |
T154 |
18567 |
31 |
0 |
0 |
T163 |
13823 |
51 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5367 |
0 |
0 |
T111 |
38220 |
401 |
0 |
0 |
T124 |
34295 |
238 |
0 |
0 |
T129 |
269520 |
627 |
0 |
0 |
T130 |
9653 |
77 |
0 |
0 |
T131 |
8733 |
111 |
0 |
0 |
T136 |
181132 |
449 |
0 |
0 |
T137 |
7999 |
53 |
0 |
0 |
T153 |
19746 |
60 |
0 |
0 |
T154 |
18567 |
24 |
0 |
0 |
T163 |
13823 |
46 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5299 |
0 |
0 |
T111 |
38220 |
423 |
0 |
0 |
T124 |
34295 |
283 |
0 |
0 |
T129 |
269520 |
686 |
0 |
0 |
T131 |
8733 |
3 |
0 |
0 |
T136 |
181132 |
449 |
0 |
0 |
T137 |
7999 |
61 |
0 |
0 |
T153 |
19746 |
129 |
0 |
0 |
T154 |
18567 |
39 |
0 |
0 |
T163 |
13823 |
64 |
0 |
0 |
T164 |
30655 |
115 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5127 |
0 |
0 |
T111 |
38220 |
218 |
0 |
0 |
T124 |
34295 |
258 |
0 |
0 |
T129 |
269520 |
663 |
0 |
0 |
T130 |
9653 |
70 |
0 |
0 |
T131 |
8733 |
47 |
0 |
0 |
T136 |
181132 |
437 |
0 |
0 |
T137 |
7999 |
41 |
0 |
0 |
T153 |
19746 |
53 |
0 |
0 |
T154 |
18567 |
45 |
0 |
0 |
T163 |
13823 |
2 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5379 |
0 |
0 |
T111 |
38220 |
271 |
0 |
0 |
T124 |
34295 |
67 |
0 |
0 |
T129 |
269520 |
646 |
0 |
0 |
T130 |
9653 |
53 |
0 |
0 |
T131 |
8733 |
95 |
0 |
0 |
T136 |
181132 |
478 |
0 |
0 |
T137 |
7999 |
53 |
0 |
0 |
T153 |
19746 |
69 |
0 |
0 |
T154 |
18567 |
54 |
0 |
0 |
T163 |
13823 |
46 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
4840 |
0 |
0 |
T111 |
38220 |
374 |
0 |
0 |
T124 |
34295 |
216 |
0 |
0 |
T129 |
269520 |
728 |
0 |
0 |
T130 |
9653 |
45 |
0 |
0 |
T131 |
8733 |
9 |
0 |
0 |
T136 |
181132 |
403 |
0 |
0 |
T137 |
7999 |
102 |
0 |
0 |
T153 |
19746 |
59 |
0 |
0 |
T154 |
18567 |
46 |
0 |
0 |
T163 |
13823 |
63 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5069 |
0 |
0 |
T111 |
38220 |
328 |
0 |
0 |
T124 |
34295 |
237 |
0 |
0 |
T129 |
269520 |
683 |
0 |
0 |
T130 |
9653 |
14 |
0 |
0 |
T131 |
8733 |
119 |
0 |
0 |
T136 |
181132 |
505 |
0 |
0 |
T137 |
7999 |
63 |
0 |
0 |
T153 |
19746 |
53 |
0 |
0 |
T154 |
18567 |
56 |
0 |
0 |
T163 |
13823 |
11 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5053 |
0 |
0 |
T111 |
38220 |
241 |
0 |
0 |
T124 |
34295 |
399 |
0 |
0 |
T129 |
269520 |
607 |
0 |
0 |
T130 |
9653 |
3 |
0 |
0 |
T131 |
8733 |
10 |
0 |
0 |
T136 |
181132 |
472 |
0 |
0 |
T137 |
7999 |
12 |
0 |
0 |
T153 |
19746 |
75 |
0 |
0 |
T154 |
18567 |
29 |
0 |
0 |
T163 |
13823 |
35 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5564 |
0 |
0 |
T111 |
38220 |
209 |
0 |
0 |
T124 |
34295 |
199 |
0 |
0 |
T129 |
269520 |
689 |
0 |
0 |
T130 |
9653 |
45 |
0 |
0 |
T131 |
8733 |
109 |
0 |
0 |
T136 |
181132 |
499 |
0 |
0 |
T137 |
7999 |
3 |
0 |
0 |
T153 |
19746 |
81 |
0 |
0 |
T154 |
18567 |
18 |
0 |
0 |
T163 |
13823 |
84 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5173 |
0 |
0 |
T111 |
38220 |
305 |
0 |
0 |
T124 |
34295 |
379 |
0 |
0 |
T129 |
269520 |
679 |
0 |
0 |
T130 |
9653 |
67 |
0 |
0 |
T131 |
8733 |
113 |
0 |
0 |
T136 |
181132 |
440 |
0 |
0 |
T137 |
7999 |
99 |
0 |
0 |
T153 |
19746 |
56 |
0 |
0 |
T154 |
18567 |
43 |
0 |
0 |
T163 |
13823 |
64 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5255 |
0 |
0 |
T111 |
38220 |
312 |
0 |
0 |
T124 |
34295 |
318 |
0 |
0 |
T129 |
269520 |
635 |
0 |
0 |
T130 |
9653 |
53 |
0 |
0 |
T131 |
8733 |
55 |
0 |
0 |
T136 |
181132 |
460 |
0 |
0 |
T137 |
7999 |
125 |
0 |
0 |
T153 |
19746 |
68 |
0 |
0 |
T154 |
18567 |
21 |
0 |
0 |
T163 |
13823 |
52 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5437 |
0 |
0 |
T111 |
38220 |
217 |
0 |
0 |
T124 |
34295 |
276 |
0 |
0 |
T129 |
269520 |
662 |
0 |
0 |
T130 |
9653 |
95 |
0 |
0 |
T131 |
8733 |
52 |
0 |
0 |
T136 |
181132 |
483 |
0 |
0 |
T137 |
7999 |
53 |
0 |
0 |
T153 |
19746 |
58 |
0 |
0 |
T154 |
18567 |
45 |
0 |
0 |
T163 |
13823 |
27 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5277 |
0 |
0 |
T111 |
38220 |
363 |
0 |
0 |
T124 |
34295 |
242 |
0 |
0 |
T129 |
269520 |
672 |
0 |
0 |
T130 |
9653 |
30 |
0 |
0 |
T131 |
8733 |
94 |
0 |
0 |
T136 |
181132 |
515 |
0 |
0 |
T137 |
7999 |
105 |
0 |
0 |
T153 |
19746 |
67 |
0 |
0 |
T154 |
18567 |
10 |
0 |
0 |
T163 |
13823 |
23 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5141 |
0 |
0 |
T111 |
38220 |
265 |
0 |
0 |
T124 |
34295 |
127 |
0 |
0 |
T129 |
269520 |
704 |
0 |
0 |
T130 |
9653 |
83 |
0 |
0 |
T131 |
8733 |
35 |
0 |
0 |
T136 |
181132 |
427 |
0 |
0 |
T137 |
7999 |
117 |
0 |
0 |
T153 |
19746 |
45 |
0 |
0 |
T154 |
18567 |
36 |
0 |
0 |
T163 |
13823 |
36 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5089 |
0 |
0 |
T111 |
38220 |
304 |
0 |
0 |
T124 |
34295 |
130 |
0 |
0 |
T129 |
269520 |
716 |
0 |
0 |
T130 |
9653 |
49 |
0 |
0 |
T131 |
8733 |
93 |
0 |
0 |
T136 |
181132 |
433 |
0 |
0 |
T137 |
7999 |
107 |
0 |
0 |
T153 |
19746 |
81 |
0 |
0 |
T154 |
18567 |
47 |
0 |
0 |
T163 |
13823 |
26 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5241 |
0 |
0 |
T111 |
38220 |
214 |
0 |
0 |
T124 |
34295 |
360 |
0 |
0 |
T129 |
269520 |
620 |
0 |
0 |
T130 |
9653 |
78 |
0 |
0 |
T131 |
8733 |
3 |
0 |
0 |
T136 |
181132 |
382 |
0 |
0 |
T137 |
7999 |
138 |
0 |
0 |
T153 |
19746 |
39 |
0 |
0 |
T154 |
18567 |
28 |
0 |
0 |
T163 |
13823 |
16 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5622 |
0 |
0 |
T111 |
38220 |
238 |
0 |
0 |
T124 |
34295 |
197 |
0 |
0 |
T129 |
269520 |
659 |
0 |
0 |
T130 |
9653 |
60 |
0 |
0 |
T131 |
8733 |
80 |
0 |
0 |
T136 |
181132 |
430 |
0 |
0 |
T137 |
7999 |
99 |
0 |
0 |
T153 |
19746 |
61 |
0 |
0 |
T154 |
18567 |
20 |
0 |
0 |
T163 |
13823 |
39 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
4926 |
0 |
0 |
T111 |
38220 |
214 |
0 |
0 |
T124 |
34295 |
148 |
0 |
0 |
T129 |
269520 |
675 |
0 |
0 |
T130 |
9653 |
12 |
0 |
0 |
T131 |
8733 |
107 |
0 |
0 |
T136 |
181132 |
500 |
0 |
0 |
T137 |
7999 |
10 |
0 |
0 |
T153 |
19746 |
81 |
0 |
0 |
T154 |
18567 |
19 |
0 |
0 |
T163 |
13823 |
81 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
4881 |
0 |
0 |
T111 |
38220 |
138 |
0 |
0 |
T124 |
34295 |
213 |
0 |
0 |
T129 |
269520 |
725 |
0 |
0 |
T130 |
9653 |
24 |
0 |
0 |
T131 |
8733 |
123 |
0 |
0 |
T136 |
181132 |
477 |
0 |
0 |
T137 |
7999 |
76 |
0 |
0 |
T153 |
19746 |
108 |
0 |
0 |
T154 |
18567 |
40 |
0 |
0 |
T163 |
13823 |
54 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5412 |
0 |
0 |
T111 |
38220 |
208 |
0 |
0 |
T124 |
34295 |
314 |
0 |
0 |
T129 |
269520 |
684 |
0 |
0 |
T130 |
9653 |
8 |
0 |
0 |
T131 |
8733 |
82 |
0 |
0 |
T136 |
181132 |
457 |
0 |
0 |
T137 |
7999 |
61 |
0 |
0 |
T153 |
19746 |
116 |
0 |
0 |
T154 |
18567 |
53 |
0 |
0 |
T163 |
13823 |
63 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5117 |
0 |
0 |
T111 |
38220 |
283 |
0 |
0 |
T124 |
34295 |
283 |
0 |
0 |
T129 |
269520 |
628 |
0 |
0 |
T130 |
9653 |
18 |
0 |
0 |
T131 |
8733 |
46 |
0 |
0 |
T136 |
181132 |
441 |
0 |
0 |
T137 |
7999 |
93 |
0 |
0 |
T153 |
19746 |
44 |
0 |
0 |
T154 |
18567 |
8 |
0 |
0 |
T163 |
13823 |
35 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5860 |
0 |
0 |
T111 |
38220 |
473 |
0 |
0 |
T124 |
34295 |
256 |
0 |
0 |
T129 |
269520 |
648 |
0 |
0 |
T130 |
9653 |
69 |
0 |
0 |
T131 |
8733 |
4 |
0 |
0 |
T136 |
181132 |
423 |
0 |
0 |
T137 |
7999 |
4 |
0 |
0 |
T153 |
19746 |
60 |
0 |
0 |
T154 |
18567 |
50 |
0 |
0 |
T163 |
13823 |
61 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
5159 |
0 |
0 |
T111 |
38220 |
348 |
0 |
0 |
T124 |
34295 |
91 |
0 |
0 |
T129 |
269520 |
723 |
0 |
0 |
T130 |
9653 |
48 |
0 |
0 |
T131 |
8733 |
45 |
0 |
0 |
T136 |
181132 |
406 |
0 |
0 |
T137 |
7999 |
109 |
0 |
0 |
T153 |
19746 |
51 |
0 |
0 |
T154 |
18567 |
28 |
0 |
0 |
T163 |
13823 |
62 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2804 |
0 |
0 |
T111 |
38220 |
67 |
0 |
0 |
T124 |
34295 |
50 |
0 |
0 |
T129 |
269520 |
681 |
0 |
0 |
T130 |
9653 |
19 |
0 |
0 |
T131 |
8733 |
15 |
0 |
0 |
T136 |
181132 |
452 |
0 |
0 |
T137 |
7999 |
15 |
0 |
0 |
T153 |
19746 |
136 |
0 |
0 |
T154 |
18567 |
37 |
0 |
0 |
T163 |
13823 |
25 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2810 |
0 |
0 |
T111 |
38220 |
65 |
0 |
0 |
T124 |
34295 |
51 |
0 |
0 |
T129 |
269520 |
724 |
0 |
0 |
T130 |
9653 |
11 |
0 |
0 |
T131 |
8733 |
10 |
0 |
0 |
T136 |
181132 |
461 |
0 |
0 |
T137 |
7999 |
14 |
0 |
0 |
T153 |
19746 |
75 |
0 |
0 |
T154 |
18567 |
12 |
0 |
0 |
T163 |
13823 |
27 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2665 |
0 |
0 |
T111 |
38220 |
47 |
0 |
0 |
T124 |
34295 |
45 |
0 |
0 |
T129 |
269520 |
627 |
0 |
0 |
T130 |
9653 |
4 |
0 |
0 |
T131 |
8733 |
11 |
0 |
0 |
T136 |
181132 |
418 |
0 |
0 |
T137 |
7999 |
4 |
0 |
0 |
T153 |
19746 |
43 |
0 |
0 |
T154 |
18567 |
33 |
0 |
0 |
T163 |
13823 |
34 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2745 |
0 |
0 |
T111 |
38220 |
65 |
0 |
0 |
T124 |
34295 |
61 |
0 |
0 |
T129 |
269520 |
579 |
0 |
0 |
T130 |
9653 |
2 |
0 |
0 |
T131 |
8733 |
19 |
0 |
0 |
T136 |
181132 |
449 |
0 |
0 |
T137 |
7999 |
12 |
0 |
0 |
T153 |
19746 |
69 |
0 |
0 |
T154 |
18567 |
38 |
0 |
0 |
T163 |
13823 |
38 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
3434 |
0 |
0 |
T111 |
38220 |
118 |
0 |
0 |
T124 |
34295 |
125 |
0 |
0 |
T129 |
269520 |
718 |
0 |
0 |
T130 |
9653 |
14 |
0 |
0 |
T131 |
8733 |
7 |
0 |
0 |
T136 |
181132 |
484 |
0 |
0 |
T137 |
7999 |
45 |
0 |
0 |
T153 |
19746 |
73 |
0 |
0 |
T154 |
18567 |
10 |
0 |
0 |
T163 |
13823 |
37 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
4827 |
0 |
0 |
T14 |
248708 |
28 |
0 |
0 |
T15 |
0 |
33 |
0 |
0 |
T16 |
0 |
46 |
0 |
0 |
T18 |
0 |
85 |
0 |
0 |
T27 |
842574 |
0 |
0 |
0 |
T28 |
3056 |
0 |
0 |
0 |
T29 |
6104 |
0 |
0 |
0 |
T37 |
77180 |
0 |
0 |
0 |
T61 |
147897 |
0 |
0 |
0 |
T74 |
89340 |
0 |
0 |
0 |
T143 |
1023 |
0 |
0 |
0 |
T144 |
1366 |
0 |
0 |
0 |
T165 |
0 |
29 |
0 |
0 |
T166 |
0 |
37 |
0 |
0 |
T167 |
0 |
41 |
0 |
0 |
T168 |
0 |
52 |
0 |
0 |
T169 |
0 |
30 |
0 |
0 |
T170 |
0 |
26 |
0 |
0 |
T171 |
9198 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2900 |
0 |
0 |
T111 |
38220 |
63 |
0 |
0 |
T124 |
34295 |
63 |
0 |
0 |
T129 |
269520 |
663 |
0 |
0 |
T130 |
9653 |
7 |
0 |
0 |
T131 |
8733 |
6 |
0 |
0 |
T136 |
181132 |
418 |
0 |
0 |
T137 |
7999 |
18 |
0 |
0 |
T153 |
19746 |
78 |
0 |
0 |
T154 |
18567 |
12 |
0 |
0 |
T163 |
13823 |
62 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2829 |
0 |
0 |
T111 |
38220 |
53 |
0 |
0 |
T124 |
34295 |
57 |
0 |
0 |
T129 |
269520 |
675 |
0 |
0 |
T130 |
9653 |
13 |
0 |
0 |
T131 |
8733 |
18 |
0 |
0 |
T136 |
181132 |
456 |
0 |
0 |
T137 |
7999 |
17 |
0 |
0 |
T153 |
19746 |
37 |
0 |
0 |
T154 |
18567 |
53 |
0 |
0 |
T163 |
13823 |
46 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2353 |
0 |
0 |
T111 |
38220 |
36 |
0 |
0 |
T124 |
34295 |
28 |
0 |
0 |
T129 |
269520 |
625 |
0 |
0 |
T130 |
9653 |
5 |
0 |
0 |
T131 |
8733 |
9 |
0 |
0 |
T136 |
181132 |
443 |
0 |
0 |
T137 |
7999 |
9 |
0 |
0 |
T153 |
19746 |
58 |
0 |
0 |
T154 |
18567 |
34 |
0 |
0 |
T163 |
13823 |
38 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2461 |
0 |
0 |
T111 |
38220 |
26 |
0 |
0 |
T124 |
34295 |
34 |
0 |
0 |
T129 |
269520 |
660 |
0 |
0 |
T130 |
9653 |
3 |
0 |
0 |
T131 |
8733 |
9 |
0 |
0 |
T136 |
181132 |
421 |
0 |
0 |
T137 |
7999 |
12 |
0 |
0 |
T153 |
19746 |
31 |
0 |
0 |
T154 |
18567 |
33 |
0 |
0 |
T163 |
13823 |
51 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2570 |
0 |
0 |
T111 |
38220 |
36 |
0 |
0 |
T124 |
34295 |
39 |
0 |
0 |
T129 |
269520 |
678 |
0 |
0 |
T130 |
9653 |
3 |
0 |
0 |
T131 |
8733 |
11 |
0 |
0 |
T136 |
181132 |
486 |
0 |
0 |
T137 |
7999 |
2 |
0 |
0 |
T153 |
19746 |
13 |
0 |
0 |
T154 |
18567 |
38 |
0 |
0 |
T163 |
13823 |
45 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2476 |
0 |
0 |
T111 |
38220 |
37 |
0 |
0 |
T124 |
34295 |
45 |
0 |
0 |
T129 |
269520 |
672 |
0 |
0 |
T130 |
9653 |
8 |
0 |
0 |
T131 |
8733 |
7 |
0 |
0 |
T136 |
181132 |
424 |
0 |
0 |
T137 |
7999 |
4 |
0 |
0 |
T153 |
19746 |
34 |
0 |
0 |
T154 |
18567 |
45 |
0 |
0 |
T163 |
13823 |
30 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
3361 |
0 |
0 |
T111 |
38220 |
55 |
0 |
0 |
T124 |
34295 |
98 |
0 |
0 |
T129 |
269520 |
679 |
0 |
0 |
T130 |
9653 |
1 |
0 |
0 |
T131 |
8733 |
2 |
0 |
0 |
T136 |
181132 |
498 |
0 |
0 |
T137 |
7999 |
10 |
0 |
0 |
T153 |
19746 |
93 |
0 |
0 |
T154 |
18567 |
43 |
0 |
0 |
T163 |
13823 |
41 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2599 |
0 |
0 |
T111 |
38220 |
33 |
0 |
0 |
T124 |
34295 |
54 |
0 |
0 |
T129 |
269520 |
642 |
0 |
0 |
T130 |
9653 |
5 |
0 |
0 |
T131 |
8733 |
12 |
0 |
0 |
T136 |
181132 |
408 |
0 |
0 |
T137 |
7999 |
5 |
0 |
0 |
T153 |
19746 |
74 |
0 |
0 |
T154 |
18567 |
48 |
0 |
0 |
T163 |
13823 |
69 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
3572 |
0 |
0 |
T111 |
38220 |
106 |
0 |
0 |
T124 |
34295 |
99 |
0 |
0 |
T129 |
269520 |
696 |
0 |
0 |
T130 |
9653 |
19 |
0 |
0 |
T131 |
8733 |
17 |
0 |
0 |
T136 |
181132 |
446 |
0 |
0 |
T137 |
7999 |
20 |
0 |
0 |
T153 |
19746 |
74 |
0 |
0 |
T154 |
18567 |
40 |
0 |
0 |
T163 |
13823 |
43 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2840 |
0 |
0 |
T111 |
38220 |
46 |
0 |
0 |
T124 |
34295 |
35 |
0 |
0 |
T129 |
269520 |
721 |
0 |
0 |
T130 |
9653 |
1 |
0 |
0 |
T131 |
8733 |
15 |
0 |
0 |
T136 |
181132 |
450 |
0 |
0 |
T137 |
7999 |
1 |
0 |
0 |
T153 |
19746 |
70 |
0 |
0 |
T154 |
18567 |
38 |
0 |
0 |
T163 |
13823 |
84 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2567 |
0 |
0 |
T111 |
38220 |
30 |
0 |
0 |
T124 |
34295 |
34 |
0 |
0 |
T129 |
269520 |
680 |
0 |
0 |
T130 |
9653 |
9 |
0 |
0 |
T131 |
8733 |
4 |
0 |
0 |
T136 |
181132 |
460 |
0 |
0 |
T137 |
7999 |
3 |
0 |
0 |
T153 |
19746 |
45 |
0 |
0 |
T154 |
18567 |
27 |
0 |
0 |
T163 |
13823 |
58 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2708 |
0 |
0 |
T111 |
38220 |
23 |
0 |
0 |
T124 |
34295 |
30 |
0 |
0 |
T129 |
269520 |
717 |
0 |
0 |
T131 |
8733 |
8 |
0 |
0 |
T136 |
181132 |
466 |
0 |
0 |
T137 |
7999 |
10 |
0 |
0 |
T153 |
19746 |
68 |
0 |
0 |
T154 |
18567 |
31 |
0 |
0 |
T163 |
13823 |
54 |
0 |
0 |
T164 |
30655 |
14 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2684 |
0 |
0 |
T111 |
38220 |
35 |
0 |
0 |
T124 |
34295 |
39 |
0 |
0 |
T129 |
269520 |
671 |
0 |
0 |
T130 |
9653 |
3 |
0 |
0 |
T131 |
8733 |
8 |
0 |
0 |
T136 |
181132 |
468 |
0 |
0 |
T137 |
7999 |
7 |
0 |
0 |
T153 |
19746 |
45 |
0 |
0 |
T154 |
18567 |
36 |
0 |
0 |
T163 |
13823 |
71 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2531 |
0 |
0 |
T111 |
38220 |
39 |
0 |
0 |
T124 |
34295 |
26 |
0 |
0 |
T129 |
269520 |
622 |
0 |
0 |
T130 |
9653 |
5 |
0 |
0 |
T131 |
8733 |
7 |
0 |
0 |
T136 |
181132 |
415 |
0 |
0 |
T137 |
7999 |
2 |
0 |
0 |
T153 |
19746 |
67 |
0 |
0 |
T154 |
18567 |
37 |
0 |
0 |
T163 |
13823 |
61 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2715 |
0 |
0 |
T111 |
38220 |
52 |
0 |
0 |
T124 |
34295 |
39 |
0 |
0 |
T129 |
269520 |
694 |
0 |
0 |
T130 |
9653 |
6 |
0 |
0 |
T131 |
8733 |
7 |
0 |
0 |
T136 |
181132 |
475 |
0 |
0 |
T137 |
7999 |
14 |
0 |
0 |
T153 |
19746 |
30 |
0 |
0 |
T154 |
18567 |
36 |
0 |
0 |
T163 |
13823 |
83 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
483896972 |
2481 |
0 |
0 |
T111 |
38220 |
35 |
0 |
0 |
T124 |
34295 |
33 |
0 |
0 |
T129 |
269520 |
653 |
0 |
0 |
T130 |
9653 |
8 |
0 |
0 |
T131 |
8733 |
1 |
0 |
0 |
T136 |
181132 |
454 |
0 |
0 |
T137 |
7999 |
10 |
0 |
0 |
T153 |
19746 |
50 |
0 |
0 |
T154 |
18567 |
34 |
0 |
0 |
T163 |
13823 |
21 |
0 |
0 |